diff options
| author | Scott Larson <[email protected]> | 2020-08-14 09:10:48 -0700 |
|---|---|---|
| committer | Scott Larson <[email protected]> | 2020-08-14 09:10:48 -0700 |
| commit | 40a402b827d96ce5b4d149767cdcec64427bb6c4 (patch) | |
| tree | 3a67c3aa698fd8eee1b91b87181e9833a92985c1 | |
| parent | 6a018a4cfda937c0d8cbdee761187c5c5843e115 (diff) | |
apply 6.0.2 patch
227 files changed, 2232 insertions, 3212 deletions
diff --git a/common/inc/tx_api.h b/common/inc/tx_api.h index 75b443d2..7aa923b3 100644 --- a/common/inc/tx_api.h +++ b/common/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE C */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -47,6 +47,9 @@ /* 06-30-2020 William E. Lamie Modified comment(s), and */ /* updated product constants, */ /* resulting in version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), and */ +/* updated product constants, */ +/* resulting in version 6.0.2 */ /* */ /**************************************************************************/ @@ -79,7 +82,7 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 #define THREADX_MINOR_VERSION 0 -#define THREADX_PATCH_VERSION 1 +#define THREADX_PATCH_VERSION 2 /* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX diff --git a/common_smp/inc/tx_api.h b/common_smp/inc/tx_api.h index b6994109..75daa1c2 100644 --- a/common_smp/inc/tx_api.h +++ b/common_smp/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE SMP */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -44,6 +44,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 08-14-2020 William E. Lamie Modified comment(s), and */ +/* updated product constants, */ +/* resulting in version 6.0.2 */ /* */ /**************************************************************************/ @@ -80,9 +83,13 @@ extern "C" { /* Define the major/minor version information that can be used by the application and the ThreadX source as well. */ +#define AZURE_RTOS_THREADX +#define THREADX_MAJOR_VERSION 6 +#define THREADX_MINOR_VERSION 0 +#define THREADX_PATCH_VERSION 2 + +/* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX -#define THREADX_MAJOR_VERSION 5 -#define THREADX_MINOR_VERSION 9 /* API input parameters and general constants. */ diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s index 61c57b5f..7c1a82e6 100644 --- a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -20,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; ; IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory @@ -87,7 +77,7 @@ __tx_vectors DCD __tx_IntHandler ; Int 0 DCD __tx_IntHandler ; Int 1 DCD __tx_IntHandler ; Int 2 - DCD __tx_IntHandler ; Int 3 + DCD __tx_IntHandler ; Int 3 ; ; AREA ||.text||, CODE, READONLY @@ -96,13 +86,13 @@ Reset_Handler CPSID i LDR R0, =__main BX R0 - + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -136,29 +126,32 @@ Reset_Handler ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ EXPORT _tx_initialize_low_level _tx_initialize_low_level -; +; ; /* Ensure that interrupts are disabled. */ ; CPSID i ; Disable interrupts ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| ; Build first free address - ADDS r1, r1, #4 ; + ADDS r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; LDR r0, =0xE000ED08 ; Build address of NVIC registers LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address + STR r1, [r0] ; Set vector table address ; ; /* Enable the cycle count register. */ ; @@ -166,15 +159,15 @@ _tx_initialize_low_level ; LDR r1, [r0] ; Pickup the current value ; MOVS r2, #1 ; ORRS r1, r1, r2 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Setup Vector Table Offset Register. */ -; +; LDR r0, =0xE000E000 ; Build address of NVIC registers LDR r2, =0xD08 ; Offset to vector base register ADD r0, r0, r2 ; Build vector base register LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address + STR r1, [r0] ; Set vector table address ; ; /* Set system stack pointer from vector value. */ ; @@ -195,30 +188,30 @@ _tx_initialize_low_level ; LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD18 ; - ADD r0, r0, r2 ; + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD1C ; - ADD r0, r0, r2 ; + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers ; Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD20 ; - ADD r0, r0, r2 ; + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; -; +; ;/* Define initial heap/stack routine for the ARM RVCT startup code. ; This routine will set the initial stack and heap locations */ ; @@ -239,14 +232,14 @@ __tx_BadHandler EXPORT __tx_SVCallHandler __tx_SVCallHandler - B __tx_SVCallHandler + B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {r0, lr} - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -269,7 +262,7 @@ SysTick_Handler BX lr ; } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler @@ -280,5 +273,3 @@ __tx_DBGHandler ALIGN LTORG END - - diff --git a/ports/cortex_m0/ac5/readme_threadx.txt b/ports/cortex_m0/ac5/readme_threadx.txt index fb2f95c3..a5ddf83c 100644 --- a/ports/cortex_m0/ac5/readme_threadx.txt +++ b/ports/cortex_m0/ac5/readme_threadx.txt @@ -133,6 +133,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M0/AC5 port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC5 tools. diff --git a/ports/cortex_m0/ac5/src/tx_thread_context_restore.s b/ports/cortex_m0/ac5/src/tx_thread_context_restore.s index 4ef66308..a461fc2a 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m0/ac5/src/tx_thread_context_restore.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_exit ENDIF @@ -42,13 +32,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -75,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -98,4 +93,3 @@ _tx_thread_context_restore ALIGN LTORG END - diff --git a/ports/cortex_m0/ac5/src/tx_thread_context_save.s b/ports/cortex_m0/ac5/src/tx_thread_context_save.s index 52fd2828..0b9606dd 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m0/ac5/src/tx_thread_context_save.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_enter ENDIF @@ -43,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -92,10 +87,9 @@ _tx_thread_context_save ENDIF ; ; /* Return to interrupt processing. */ -; +; BX lr ; Return to interrupt processing caller ;} ALIGN LTORG END - diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s index 7b360417..a615bda2 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -84,4 +79,3 @@ _tx_thread_interrupt_control ALIGN LTORG END - diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s index b28496d6..60c8eb0d 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s index 29d0f590..8357b420 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m0/ac5/src/tx_thread_schedule.s b/ports/cortex_m0/ac5/src/tx_thread_schedule.s index abcb7c2c..7c8c468a 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m0/ac5/src/tx_thread_schedule.s @@ -21,15 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice @@ -37,7 +28,7 @@ IMPORT _tx_thread_preempt_disable IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_thread_enter - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; @@ -48,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,6 +73,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -94,7 +88,7 @@ _tx_thread_schedule ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOVS r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -102,7 +96,7 @@ _tx_thread_schedule ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; LDR r0, =0x10000000 ; Load PENDSVSET bit @@ -112,22 +106,22 @@ _tx_thread_schedule ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here B __tx_wait_here ; Wait for the PendSV to happen ;} ; -; /* Generic context switch-out switch-in handler... Note that this handler is +; /* Generic context switch-out switch-in handler... Note that this handler is ; common for both PendSV and SVCall. */ -; +; EXPORT PendSV_Handler EXPORT __tx_PendSVHandler PendSV_Handler __tx_PendSVHandler ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler +; +__tx_ts_handler IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -137,7 +131,7 @@ __tx_ts_handler PUSH {r0, lr} ; Save LR (and r0 just for alignment) BL _tx_execution_thread_exit ; Call the thread exit function POP {r0, r1} ; Recover LR - MOV lr, r1 ; + MOV lr, r1 ; CPSIE i ; Enable interrupts ENDIF LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address @@ -146,9 +140,9 @@ __tx_ts_handler LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CMP r1,#0 ; If NULL, skip preservation - BEQ __tx_ts_new ; + BEQ __tx_ts_new ; ; ; /* Recover PSP and preserve current thread context. */ ; @@ -156,15 +150,15 @@ __tx_ts_handler MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 ; Allocate stack space STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4,r8 ; - MOV r5,r9 ; - MOV r6,r10 ; - MOV r7,r11 ; + MOV r4,r8 ; + MOV r5,r9 ; + MOV r6,r10 ; + MOV r7,r11 ; SUBS r3, r3, #32 ; Allocate stack space - STM r3!, {r4-r7} ; + STM r3!, {r4-r7} ; SUBS r3, r3, #20 ; Allocate stack space - MOV r5, LR ; - STR r5, [r3] ; Save LR on the stack + MOV r5, LR ; + STR r5, [r3] ; Save LR on the stack STR r3, [r1, #8] ; Save its stack pointer ; ; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ @@ -172,7 +166,7 @@ __tx_ts_handler LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable LDR r5, [r4] ; Pickup current time-slice CMP r5, #0 ; If not active, skip processing - BEQ __tx_ts_new ; + BEQ __tx_ts_new ; ; ; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ ; @@ -183,7 +177,6 @@ __tx_ts_handler MOVS r5, #0 ; Build clear value STR r5, [r4] ; Clear time-slice ; -; ; /* Executing thread is now completely preserved!!! */ ; __tx_ts_new @@ -192,7 +185,7 @@ __tx_ts_new ; CPSID i ; Disable interrupts LDR r1, [r2] ; Is there another thread ready to execute? - CMP r1, #0 ; + CMP r1, #0 ; BEQ __tx_ts_wait ; No, skip to the wait processing ; ; /* Yes, another thread is ready for else, make the current thread the new thread. */ @@ -229,26 +222,26 @@ __tx_ts_restore ADDS r3, r3, #4 ; Position past LR MOV lr, r5 ; Restore LR LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11) - MOV r11,r7 ; - MOV r10,r6 ; - MOV r9,r5 ; - MOV r8,r4 ; - LDM r3!,{r4-r7} ; + MOV r11,r7 ; + MOV r10,r6 ; + MOV r9,r5 ; + MOV r8,r4 ; + LDM r3!,{r4-r7} ; MSR PSP, r3 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait CPSID i ; Disable interrupts LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer - CMP r1, #0 ; If non-NULL, a new thread is ready! + CMP r1, #0 ; If non-NULL, a new thread is ready! BNE __tx_ts_ready ; IF :DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions @@ -259,20 +252,19 @@ __tx_ts_ISB CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready LDR r7, =0x08000000 ; Build clear PendSV value LDR r5, =0xE000ED04 ; Build base NVIC address - STR r7, [r5] ; Clear any PendSV + STR r7, [r5] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ALIGN LTORG END - diff --git a/ports/cortex_m0/ac5/src/tx_thread_stack_build.s b/ports/cortex_m0/ac5/src/tx_thread_stack_build.s index 524eb9f5..142c48a4 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m0/ac5/src/tx_thread_stack_build.s @@ -21,22 +21,13 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -76,11 +70,11 @@ EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M0 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r8 Initial value for r8 ; r9 Initial value for r9 @@ -102,7 +96,7 @@ _tx_thread_stack_build ; Stack Bottom: (higher memory address) */ ; LDR r2, [r0, #16] ; Pickup end of stack area - MOVS r3, #0x7 ; + MOVS r3, #0x7 ; BICS r2, r2, r3 ; Align frame for 8-byte alignment SUBS r2, r2, #68 ; Subtract frame size LDR r3, =0xFFFFFFFD ; Build initial LR value @@ -143,4 +137,3 @@ _tx_thread_stack_build ALIGN LTORG END - diff --git a/ports/cortex_m0/ac5/src/tx_thread_system_return.s b/ports/cortex_m0/ac5/src/tx_thread_system_return.s index a1e11054..58db7a75 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m0/ac5/src/tx_thread_system_return.s @@ -20,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -37,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -77,9 +70,9 @@ EXPORT _tx_thread_system_return _tx_thread_system_return ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; LDR r0, =0x10000000 ; Load PENDSVSET bit LDR r1, =0xE000ED04 ; Load NVIC base STR r0, [r1] ; Set PENDSVBIT in ICSR @@ -90,8 +83,7 @@ _tx_thread_system_return CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context - BX lr ; Return to caller + BX lr ; Return to caller NOP ;} - END - + END diff --git a/ports/cortex_m0/ac5/src/tx_timer_interrupt.s b/ports/cortex_m0/ac5/src/tx_timer_interrupt.s index d5844d9c..eff615bf 100644 --- a/ports/cortex_m0/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m0/ac5/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; IMPORT _tx_timer_time_slice IMPORT _tx_timer_system_clock @@ -53,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,6 +77,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -111,7 +103,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -229,18 +221,18 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); ; BL _tx_thread_time_slice ; Call time-slice processing LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag LDR r1, [r0] ; Is the preempt disable flag set? - CMP r1, #0 ; + CMP r1, #0 ; BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address LDR r1, [r0] ; Pickup the current thread pointer @@ -271,4 +263,3 @@ __tx_timer_nothing_expired ALIGN LTORG END - diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S index b561aaca..2ed5b0b4 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -20,16 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_initialize.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ @ .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory @@ -48,8 +38,8 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* FUNCTION RELEASE */ @/* */ -@/* _tx_initialize_low_level Cortex-M0/GNU */ -@/* 6.0.1 */ +@/* _tx_initialize_low_level Cortex-M0/AC6 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,6 +73,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), and */ +@/* commented out code for */ +@/* enabling DWT, */ +@/* resulting in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -96,27 +90,27 @@ _tx_initialize_low_level: CPSID i @ @ /* Set base of available memory to end of non-initialised RAM area. */ -@ +@ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address - ADDS r1, r1, #4 @ + ADDS r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer @ @ /* Enable the cycle count register. */ -@ - LDR r0, =0xE0001000 @ Build address of DWT register - LDR r1, [r0] @ Pickup the current value - MOVS r2, #1 - ORRS r1, r1, r2 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register +@ /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */ +@ LDR r0, =0xE0001000 @ Build address of DWT register +@ LDR r1, [r0] @ Pickup the current value +@ MOVS r2, #1 +@ ORRS r1, r1, r2 @ Set the CYCCNTENA bit +@ STR r1, [r0] @ Enable the cycle count register @ @ /* Setup Vector Table Offset Register. */ -@ +@ LDR r0, =0xE000E000 @ Build address of NVIC registers LDR r2, =0xD08 @ Offset to vector base register ADD r0, r0, r2 @ Build vector base register LDR r1, =vector_table @ Pickup address of vector table - STR r1, [r0] @ Set vector table address + STR r1, [r0] @ Set vector table address @ @ /* Set system stack pointer from vector value. */ @ @@ -138,25 +132,24 @@ _tx_initialize_low_level: LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 @ Build address of NVIC registers LDR r2, =0xD18 @ - ADD r0, r0, r2 @ + ADD r0, r0, r2 @ STR r1, [r0] @ Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 @ Build address of NVIC registers - LDR r2, =0xD1C @ - ADD r0, r0, r2 @ + LDR r2, =0xD1C @ + ADD r0, r0, r2 @ STR r1, [r0] @ Setup System Handlers 8-11 Priority Registers @ Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 @ Build address of NVIC registers - LDR r2, =0xD20 @ - ADD r0, r0, r2 @ + LDR r2, =0xD20 @ + ADD r0, r0, r2 @ STR r1, [r0] @ Setup System Handlers 12-15 Priority Registers @ Note: PnSV must be lowest priority, which is 0xFF - @ @ /* Return to caller. */ -@ - BX lr +@ + BX lr @} @ @ /* System Tick timer interrupt handler */ diff --git a/ports/cortex_m0/ac6/readme_threadx.txt b/ports/cortex_m0/ac6/readme_threadx.txt index fb6e237d..a68481bf 100644 --- a/ports/cortex_m0/ac6/readme_threadx.txt +++ b/ports/cortex_m0/ac6/readme_threadx.txt @@ -148,6 +148,12 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M0/AC6 port. The following files were + changed/added for port specific version 6.0.2: + + tx_initialize_low_level.S Comment out DWT code. + *.S Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC6 tools. diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_restore.S b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S index 80d41fd5..1432d485 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_system_stack_ptr @@ -48,13 +38,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M0/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function restores the interrupt context if it is processing a */ @/* nested interrupt. If not, it returns to the interrupt thread if no */ @/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -81,6 +73,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -92,4 +87,3 @@ _tx_thread_context_restore: @ /* Not needed for this port - just return! */ BX lr @} - diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_save.S b/ports/cortex_m0/ac6/src/tx_thread_context_save.S index 476fbbcb..6374ef8e 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m0/ac6/src/tx_thread_context_save.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr @ @@ -43,13 +33,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M0/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function saves the context of an executing thread in the */ @/* beginning of interrupt processing. The function also ensures that */ @/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @@ -84,6 +79,5 @@ _tx_thread_context_save: @ @ /* Not needed for this port - just return! */ - BX lr + BX lr @} - diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S index f16dd873..716ee64b 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -38,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M0/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +61,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) @@ -89,6 +84,3 @@ _tx_thread_interrupt_control: BX lr @ Return to caller @/* } */ - - - diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S index d5ce5e56..6712d457 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -38,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-M0/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,6 +60,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_disable(VOID) @@ -83,6 +78,3 @@ _tx_thread_interrupt_disable: BX lr @/* } */ - - - diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S index d3dcff80..da390d82 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -38,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-M0/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +61,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_interrupt_restore(UINT old_posture) @@ -81,6 +76,3 @@ _tx_thread_interrupt_restore: BX lr @/* } */ - - - diff --git a/ports/cortex_m0/ac6/src/tx_thread_schedule.S b/ports/cortex_m0/ac6/src/tx_thread_schedule.S index 70f3292c..7fbe0bb6 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m0/ac6/src/tx_thread_schedule.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -44,7 +35,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M0/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,6 +69,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -91,7 +85,7 @@ _tx_thread_schedule: @ from the PendSV handling routines below. */ @ @ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -@ +@ MOVS r0, #0 @ Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag STR r0, [r2, #0] @ Clear preempt disable flag @@ -99,7 +93,7 @@ _tx_thread_schedule: @ /* Enable interrupts */ @ CPSIE i -@ +@ @ /* Enter the scheduler for the first time. */ @ LDR r0, =0x10000000 @ Load PENDSVSET bit @@ -109,29 +103,29 @@ _tx_thread_schedule: ISB @ Flush pipeline @ @ /* Wait here for the PendSV to take place. */ -@ +@ __tx_wait_here: B __tx_wait_here @ Wait for the PendSV to happen @} @ -@ /* Generic context switch-out switch-in handler... Note that this handler is +@ /* Generic context switch-out switch-in handler... Note that this handler is @ common for both PendSV and SVCall. */ -@ - .global PendSV_Handler +@ + .global PendSV_Handler .thumb_func .thumb_func PendSV_Handler: .global __tx_PendSVHandler .global __tx_SVCallHandler .thumb_func -__tx_PendSVHandler: +__tx_PendSVHandler: .thumb_func __tx_SVCallHandler: @ @ /* Get current thread value and new thread pointer. */ -@ +@ .thumb_func -__tx_ts_handler: +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @@ -141,7 +135,7 @@ __tx_ts_handler: PUSH {r0, lr} @ Save LR (and r0 just for alignment) BL _tx_execution_thread_exit @ Call the thread exit function POP {r0, r1} @ Recover LR - MOV lr, r1 @ + MOV lr, r1 @ CPSIE i @ Enable interrupts #endif LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address @@ -150,9 +144,9 @@ __tx_ts_handler: LDR r1, [r0] @ Pickup current thread pointer @ @ /* Determine if there is a current thread to finish preserving. */ -@ +@ CMP r1,#0 @ If NULL, skip preservation - BEQ __tx_ts_new @ + BEQ __tx_ts_new @ @ @ /* Recover PSP and preserve current thread context. */ @ @@ -160,12 +154,12 @@ __tx_ts_handler: MRS r3, PSP @ Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 @ Allocate stack space STM r3!, {r4-r7} @ Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4,r8 @ - MOV r5,r9 @ - MOV r6,r10 @ - MOV r7,r11 @ + MOV r4,r8 @ + MOV r5,r9 @ + MOV r6,r10 @ + MOV r7,r11 @ SUBS r3, r3, #32 @ Allocate stack space - STM r3!,{r4-r7} @ + STM r3!,{r4-r7} @ SUBS r3, r3, #20 @ Allocate stack space MOV r5, lr @ Move LR into R4 STR r5, [r3] @ Save LR @@ -176,7 +170,7 @@ __tx_ts_handler: LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable LDR r5, [r4] @ Pickup current time-slice CMP r5, #0 @ If not active, skip processing - BEQ __tx_ts_new @ + BEQ __tx_ts_new @ @ @ /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ @ @@ -186,16 +180,16 @@ __tx_ts_handler: @ MOVS r5, #0 @ Build clear value STR r5, [r4] @ Clear time-slice -@ +@ @ /* Executing thread is now completely preserved!!! */ @ -__tx_ts_new: +__tx_ts_new: @ @ /* Now we are looking for a new thread to execute! */ @ CPSID i @ Disable interrupts LDR r1, [r2] @ Is there another thread ready to execute? - CMP r1, #0 @ + CMP r1, #0 @ BEQ __tx_ts_wait @ No, skip to the wait processing @ @ /* Yes, another thread is ready for else, make the current thread the new thread. */ @@ -205,7 +199,7 @@ __tx_ts_new: @ @ /* Increment the thread run count. */ @ -__tx_ts_restore: +__tx_ts_restore: LDR r7, [r1, #4] @ Pickup the current thread run count LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable LDR r5, [r1, #24] @ Pickup thread's current time-slice @@ -232,26 +226,26 @@ __tx_ts_restore: ADDS r3, r3, #4 @ Position past LR MOV lr, r5 @ Restore LR LDM r3!,{r4-r7} @ Recover thread's registers (r4-r11) - MOV r11,r7 @ - MOV r10,r6 @ - MOV r9,r5 @ + MOV r11,r7 @ + MOV r10,r6 @ + MOV r9,r5 @ MOV r8,r4 @ - LDM r3!,{r4-r7} @ + LDM r3!,{r4-r7} @ MSR PSP, r3 @ Setup the thread's stack pointer @ @ /* Return to thread. */ -@ +@ BX lr @ Return to thread! @ @ /* The following is the idle wait processing... in this case, no threads are ready for execution and the -@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts @ are disabled to allow use of WFI for waiting for a thread to arrive. */ @ -__tx_ts_wait: +__tx_ts_wait: CPSID i @ Disable interrupts LDR r1, [r2] @ Pickup the next thread to execute pointer STR r1, [r0] @ Store it in the current pointer - CMP r1, #0 @ If non-NULL, a new thread is ready! + CMP r1, #0 @ If non-NULL, a new thread is ready! BNE __tx_ts_ready @ #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions @@ -261,16 +255,15 @@ __tx_ts_wait: CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ -@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are @ already in the handler! */ @ -__tx_ts_ready: +__tx_ts_ready: LDR r7, =0x08000000 @ Build clear PendSV value LDR r5, =0xE000ED04 @ Build base NVIC address - STR r7, [r5] @ Clear any PendSV + STR r7, [r5] @ Clear any PendSV @ @ /* Re-enable interrupts and restore new thread. */ -@ +@ CPSIE i @ Enable interrupts B __tx_ts_restore @ Restore the thread - diff --git a/ports/cortex_m0/ac6/src/tx_thread_stack_build.S b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S index b12ad10a..7e6e0244 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ .text .align 4 .syntax unified @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M0/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -79,11 +73,11 @@ .thumb_func _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-M0 should look like the following after it is built: -@ -@ Stack Top: +@ +@ Stack Top: @ LR Interrupted LR (LR at time of PENDSV) @ r8 Initial value for r8 @ r9 Initial value for r9 @@ -105,7 +99,7 @@ _tx_thread_stack_build: @ Stack Bottom: (higher memory address) */ @ LDR r2, [r0, #16] @ Pickup end of stack area - MOVS r3, #0x7 @ + MOVS r3, #0x7 @ BICS r2, r2, r3 @ Align frame for 8-byte alignment SUBS r2, r2, #68 @ Subtract frame size LDR r3, =0xFFFFFFFD @ Build initial LR value @@ -143,5 +137,3 @@ _tx_thread_stack_build: @ control block BX lr @ Return to caller @} - - diff --git a/ports/cortex_m0/ac6/src/tx_thread_system_return.S b/ports/cortex_m0/ac6/src/tx_thread_system_return.S index c11d15ac..d9e87e43 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m0/ac6/src/tx_thread_system_return.S @@ -11,7 +11,7 @@ @ @ @/**************************************************************************/ -@@/**************************************************************************/ +@/**************************************************************************/ @/** */ @/** ThreadX Component */ @/** */ @@ -19,15 +19,6 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@/* #define TX_SOURCE_CODE */ -@ -@ -@/* Include necessary system files. */ -@ -@/* #include "tx_api.h" -@ #include "tx_thread.h" -@ #include "tx_timer.h" */ .text @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M0/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @@ -79,9 +73,9 @@ .thumb_func _tx_thread_system_return: @ -@ /* Return to real scheduler via PendSV. Note that this routine is often +@ /* Return to real scheduler via PendSV. Note that this routine is often @ replaced with in-line assembly in tx_port.h to improved performance. */ -@ +@ LDR r0, =0x10000000 @ Load PENDSVSET bit LDR r1, =0xE000ED04 @ Load NVIC base STR r0, [r1] @ Set PENDSVBIT in ICSR @@ -92,6 +86,5 @@ _tx_thread_system_return: CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture _isr_context: - BX lr @ Return to caller + BX lr @ Return to caller @/* } */ - diff --git a/ports/cortex_m0/ac6/src/tx_timer_interrupt.S b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S index 4894d9ae..acfee45e 100644 --- a/ports/cortex_m0/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S @@ -20,17 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ -@Define Assembly language external references... @ .global _tx_timer_time_slice .global _tx_timer_system_clock @@ -51,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M0/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +75,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -110,7 +102,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3, #0] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -228,18 +220,18 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired LDR r2, [r3, #0] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing @ @ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); BL _tx_thread_time_slice @ Call time-slice processing LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag LDR r1, [r0] @ Is the preempt disable flag set? - CMP r1, #0 @ + CMP r1, #0 @ BNE __tx_timer_skip_time_slice @ Yes, skip the PendSV logic LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address LDR r1, [r0] @ Pickup the current thread pointer @@ -267,5 +259,3 @@ __tx_timer_nothing_expired: BX lr @ Return to caller @ @} - - diff --git a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S index 9698d64c..c9e5ec34 100644 --- a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S @@ -51,7 +51,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -85,6 +85,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), and */ +@/* commented out code for */ +@/* enabling DWT, */ +@/* resulting in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -105,12 +109,12 @@ _tx_initialize_low_level: STR r1, [r0] @ Setup first unused memory pointer @ @ /* Enable the cycle count register. */ -@ - LDR r0, =0xE0001000 @ Build address of DWT register - LDR r1, [r0] @ Pickup the current value - MOVS r2, #1 - ORRS r1, r1, r2 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register +@ /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */ +@ LDR r0, =0xE0001000 @ Build address of DWT register +@ LDR r1, [r0] @ Pickup the current value +@ MOVS r2, #1 +@ ORRS r1, r1, r2 @ Set the CYCCNTENA bit +@ STR r1, [r0] @ Enable the cycle count register @ @ /* Setup Vector Table Offset Register. */ @ diff --git a/ports/cortex_m0/gnu/readme_threadx.txt b/ports/cortex_m0/gnu/readme_threadx.txt index 3dd7fbf1..cdafb926 100644 --- a/ports/cortex_m0/gnu/readme_threadx.txt +++ b/ports/cortex_m0/gnu/readme_threadx.txt @@ -145,6 +145,12 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M0/GNU port. The following files were + changed/added for port specific version 6.0.2: + + tx_initialize_low_level.S Comment out DWT code. + *.S Modified comments and whitespace. + 05/19/2020 Initial ThreadX 6.0 version for Cortex-M0 using GNU tools. diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S index 5581cdaf..19d94db9 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_system_stack_ptr @@ -49,13 +39,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function restores the interrupt context if it is processing a */ @/* nested interrupt. If not, it returns to the interrupt thread if no */ @/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -82,6 +74,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -93,4 +88,3 @@ _tx_thread_context_restore: @ /* Not needed for this port - just return! */ BX lr @} - diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_save.S b/ports/cortex_m0/gnu/src/tx_thread_context_save.S index 1d48d8fd..501e826f 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_save.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_execution_isr_enter @@ -44,13 +34,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function saves the context of an executing thread in the */ @/* beginning of interrupt processing. The function also ensures that */ @/* the system stack is used upon return to the calling ISR. */ @@ -76,6 +68,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @@ -85,6 +80,5 @@ _tx_thread_context_save: @ @ /* Not needed for this port - just return! */ - BX lr + BX lr @} - diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S index f609c227..828a080a 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -38,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +61,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) @@ -89,6 +84,3 @@ _tx_thread_interrupt_control: BX lr @ Return to caller @/* } */ - - - diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S index 7cea30dc..8d6ffd0c 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -38,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,6 +60,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_disable(VOID) @@ -83,6 +78,3 @@ _tx_thread_interrupt_disable: BX lr @/* } */ - - - diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S index 70d6b2eb..c6163fb7 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -38,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +61,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_interrupt_restore(UINT old_posture) @@ -81,6 +76,3 @@ _tx_thread_interrupt_restore: BX lr @/* } */ - - - diff --git a/ports/cortex_m0/gnu/src/tx_thread_schedule.S b/ports/cortex_m0/gnu/src/tx_thread_schedule.S index 61f3b113..3b850788 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m0/gnu/src/tx_thread_schedule.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -46,7 +37,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -80,6 +71,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -93,7 +87,7 @@ _tx_thread_schedule: @ from the PendSV handling routines below. */ @ @ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -@ +@ MOVS r0, #0 @ Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag STR r0, [r2, #0] @ Clear preempt disable flag @@ -101,7 +95,7 @@ _tx_thread_schedule: @ /* Enable interrupts */ @ CPSIE i -@ +@ @ /* Enter the scheduler for the first time. */ @ LDR r0, =#0x10000000 @ Load PENDSVSET bit @@ -111,29 +105,29 @@ _tx_thread_schedule: ISB @ Flush pipeline @ @ /* Wait here for the PendSV to take place. */ -@ +@ __tx_wait_here: B __tx_wait_here @ Wait for the PendSV to happen @} @ -@ /* Generic context switch-out switch-in handler... Note that this handler is +@ /* Generic context switch-out switch-in handler... Note that this handler is @ common for both PendSV and SVCall. */ -@ - .global PendSV_Handler +@ + .global PendSV_Handler .thumb_func .thumb_func PendSV_Handler: .global __tx_PendSVHandler .global __tx_SVCallHandler .thumb_func -__tx_PendSVHandler: +__tx_PendSVHandler: .thumb_func __tx_SVCallHandler: @ @ /* Get current thread value and new thread pointer. */ -@ +@ .thumb_func -__tx_ts_handler: +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @@ -143,7 +137,7 @@ __tx_ts_handler: PUSH {r0, lr} @ Save LR (and r0 just for alignment) BL _tx_execution_thread_exit @ Call the thread exit function POP {r0, r1} @ Recover LR - MOV lr, r1 @ + MOV lr, r1 @ CPSIE i @ Enable interrupts #endif LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address @@ -152,9 +146,9 @@ __tx_ts_handler: LDR r1, [r0] @ Pickup current thread pointer @ @ /* Determine if there is a current thread to finish preserving. */ -@ +@ CMP r1,#0 @ If NULL, skip preservation - BEQ __tx_ts_new @ + BEQ __tx_ts_new @ @ @ /* Recover PSP and preserve current thread context. */ @ @@ -162,12 +156,12 @@ __tx_ts_handler: MRS r3, PSP @ Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 @ Allocate stack space STM r3!, {r4-r7} @ Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4,r8 @ - MOV r5,r9 @ - MOV r6,r10 @ - MOV r7,r11 @ + MOV r4,r8 @ + MOV r5,r9 @ + MOV r6,r10 @ + MOV r7,r11 @ SUBS r3, r3, #32 @ Allocate stack space - STM r3!,{r4-r7} @ + STM r3!,{r4-r7} @ SUBS r3, r3, #20 @ Allocate stack space MOV r5, lr @ Move LR into R4 STR r5, [r3] @ Save LR @@ -178,7 +172,7 @@ __tx_ts_handler: LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable LDR r5, [r4] @ Pickup current time-slice CMP r5, #0 @ If not active, skip processing - BEQ __tx_ts_new @ + BEQ __tx_ts_new @ @ @ /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ @ @@ -188,16 +182,16 @@ __tx_ts_handler: @ MOVS r5, #0 @ Build clear value STR r5, [r4] @ Clear time-slice -@ +@ @ /* Executing thread is now completely preserved!!! */ @ -__tx_ts_new: +__tx_ts_new: @ @ /* Now we are looking for a new thread to execute! */ @ CPSID i @ Disable interrupts LDR r1, [r2] @ Is there another thread ready to execute? - CMP r1, #0 @ + CMP r1, #0 @ BEQ __tx_ts_wait @ No, skip to the wait processing @ @ /* Yes, another thread is ready for else, make the current thread the new thread. */ @@ -207,7 +201,7 @@ __tx_ts_new: @ @ /* Increment the thread run count. */ @ -__tx_ts_restore: +__tx_ts_restore: LDR r7, [r1, #4] @ Pickup the current thread run count LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable LDR r5, [r1, #24] @ Pickup thread's current time-slice @@ -234,26 +228,26 @@ __tx_ts_restore: ADDS r3, r3, #4 @ Position past LR MOV lr, r5 @ Restore LR LDM r3!,{r4-r7} @ Recover thread's registers (r4-r11) - MOV r11,r7 @ - MOV r10,r6 @ - MOV r9,r5 @ + MOV r11,r7 @ + MOV r10,r6 @ + MOV r9,r5 @ MOV r8,r4 @ - LDM r3!,{r4-r7} @ + LDM r3!,{r4-r7} @ MSR PSP, r3 @ Setup the thread's stack pointer @ @ /* Return to thread. */ -@ +@ BX lr @ Return to thread! @ @ /* The following is the idle wait processing... in this case, no threads are ready for execution and the -@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts @ are disabled to allow use of WFI for waiting for a thread to arrive. */ @ -__tx_ts_wait: +__tx_ts_wait: CPSID i @ Disable interrupts LDR r1, [r2] @ Pickup the next thread to execute pointer STR r1, [r0] @ Store it in the current pointer - CMP r1, #0 @ If non-NULL, a new thread is ready! + CMP r1, #0 @ If non-NULL, a new thread is ready! BNE __tx_ts_ready @ #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions @@ -263,16 +257,15 @@ __tx_ts_wait: CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ -@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are @ already in the handler! */ @ -__tx_ts_ready: +__tx_ts_ready: LDR r7, =0x08000000 @ Build clear PendSV value LDR r5, =0xE000ED04 @ Build base NVIC address - STR r7, [r5] @ Clear any PendSV + STR r7, [r5] @ Clear any PendSV @ @ /* Re-enable interrupts and restore new thread. */ -@ +@ CPSIE i @ Enable interrupts B __tx_ts_restore @ Restore the thread - diff --git a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S index 85dbba6f..bb0c6395 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ .text .align 4 .syntax unified @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M0/GNU */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -76,6 +67,9 @@ @/* needed. Removed references */ @/* to stack frame, resulting */ @/* in version 6.0.1 */ +@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -84,11 +78,11 @@ .thumb_func _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-M0 should look like the following after it is built: -@ -@ Stack Top: +@ +@ Stack Top: @ LR Interrupted LR (LR at time of PENDSV) @ r8 Initial value for r8 @ r9 Initial value for r9 @@ -110,7 +104,7 @@ _tx_thread_stack_build: @ Stack Bottom: (higher memory address) */ @ LDR r2, [r0, #16] @ Pickup end of stack area - MOVS r3, #0x7 @ + MOVS r3, #0x7 @ BICS r2, r2, r3 @ Align frame for 8-byte alignment SUBS r2, r2, #68 @ Subtract frame size LDR r3, =0xFFFFFFFD @ Build initial LR value @@ -148,5 +142,3 @@ _tx_thread_stack_build: @ control block BX lr @ Return to caller @} - - diff --git a/ports/cortex_m0/gnu/src/tx_thread_system_return.S b/ports/cortex_m0/gnu/src/tx_thread_system_return.S index 6de1b19b..e8cb536f 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m0/gnu/src/tx_thread_system_return.S @@ -11,7 +11,7 @@ @ @ @/**************************************************************************/ -@@/**************************************************************************/ +@/**************************************************************************/ @/** */ @/** ThreadX Component */ @/** */ @@ -19,15 +19,6 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@/* #define TX_SOURCE_CODE */ -@ -@ -@/* Include necessary system files. */ -@ -@/* #include "tx_api.h" -@ #include "tx_thread.h" -@ #include "tx_timer.h" */ .text 32 @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @@ -79,9 +73,9 @@ .global _tx_thread_system_return _tx_thread_system_return: @ -@ /* Return to real scheduler via PendSV. Note that this routine is often +@ /* Return to real scheduler via PendSV. Note that this routine is often @ replaced with in-line assembly in tx_port.h to improved performance. */ -@ +@ LDR r0, =0x10000000 @ Load PENDSVSET bit LDR r1, =0xE000ED04 @ Load NVIC base STR r0, [r1] @ Set PENDSVBIT in ICSR @@ -92,6 +86,5 @@ _tx_thread_system_return: CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture _isr_context: - BX lr @ Return to caller + BX lr @ Return to caller @/* } */ - diff --git a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S index ab85d97d..27fa6ec1 100755 --- a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S @@ -20,17 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ -@Define Assembly language external references... @ .global _tx_timer_time_slice .global _tx_timer_system_clock @@ -51,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +75,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -110,7 +102,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3, #0] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -228,18 +220,18 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired LDR r2, [r3, #0] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing @ @ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); BL _tx_thread_time_slice @ Call time-slice processing LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag LDR r1, [r0] @ Is the preempt disable flag set? - CMP r1, #0 @ + CMP r1, #0 @ BNE __tx_timer_skip_time_slice @ Yes, skip the PendSV logic LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address LDR r1, [r0] @ Pickup the current thread pointer @@ -267,5 +259,3 @@ __tx_timer_nothing_expired: BX lr @ Return to caller @ @} - - diff --git a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s index 4d7fdbea..061505ff 100644 --- a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s @@ -20,43 +20,33 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_initialize_unused_memory - EXTERN _tx_timer_interrupt - EXTERN __vector_table - EXTERN _tx_execution_isr_enter - EXTERN _tx_execution_isr_exit + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __vector_table + EXTERN _tx_execution_isr_enter + EXTERN _tx_execution_isr_exit ; ; SYSTEM_CLOCK EQU 50000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB - + SECTION `.text`:CODE:NOROOT(2) + THUMB + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -90,6 +80,10 @@ __tx_free_memory_start ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), and */ +;/* commented out code for */ +;/* enabling DWT, */ +;/* resulting in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -97,33 +91,33 @@ __tx_free_memory_start PUBLIC _tx_initialize_low_level _tx_initialize_low_level: -; +; ; /* Ensure that interrupts are disabled. */ ; CPSID i ; Disable interrupts ; ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer STR r0, [r2, #0] ; Save first free memory address ; ; /* Enable the cycle count register. */ -; - LDR r0, =0xE0001000 ; Build address of DWT register - LDR r1, [r0] ; Pickup the current value - MOVS r2, #1 - ORRS r1, r1, r2 ; Set the CYCCNTENA bit - STR r1, [r0] ; Enable the cycle count register +; /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */ +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; MOVS r2, #1 +; ORRS r1, r1, r2 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register ; ; /* Setup Vector Table Offset Register. */ -; +; LDR r0, =0xE000E000 ; Build address of NVIC registers LDR r2, =0xD08 ; Offset to vector base register ADD r0, r0, r2 ; Build vector base register LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0] ; Set vector table address + STR r1, [r0] ; Set vector table address ; ; /* Set system stack pointer from vector value. */ ; @@ -144,26 +138,26 @@ _tx_initialize_low_level: ; LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD18 ; - ADD r0, r0, r2 ; + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD1C ; - ADD r0, r0, r2 ; + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers ; Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD20 ; - ADD r0, r0, r2 ; + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; +; BX lr ;} ; diff --git a/ports/cortex_m0/iar/readme_threadx.txt b/ports/cortex_m0/iar/readme_threadx.txt index 4b6e3f6c..0d528857 100644 --- a/ports/cortex_m0/iar/readme_threadx.txt +++ b/ports/cortex_m0/iar/readme_threadx.txt @@ -148,6 +148,12 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M0/IAR port. The following files were + changed/added for port specific version 6.0.2: + + tx_initialize_low_level.s Comment out DWT code. + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M0 using IAR's ARM tools. diff --git a/ports/cortex_m0/iar/src/tx_thread_context_restore.s b/ports/cortex_m0/iar/src/tx_thread_context_restore.s index 9191562a..cae92740 100644 --- a/ports/cortex_m0/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m0/iar/src/tx_thread_context_restore.s @@ -21,40 +21,32 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_state - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_schedule - EXTERN _tx_thread_preempt_disable - EXTERN _tx_execution_isr_exit -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -81,6 +73,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -103,4 +98,3 @@ _tx_thread_context_restore: ; ;} END - diff --git a/ports/cortex_m0/iar/src/tx_thread_context_save.s b/ports/cortex_m0/iar/src/tx_thread_context_save.s index c598b3fe..1990adc9 100644 --- a/ports/cortex_m0/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m0/iar/src/tx_thread_context_save.s @@ -21,35 +21,27 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_state - EXTERN _tx_thread_current_ptr - EXTERN _tx_execution_isr_enter -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -84,11 +79,11 @@ _tx_thread_context_save: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the ISR enter function to indicate an ISR is starting. */ -; +; PUSH {r0, lr} ; Save return address BL _tx_execution_isr_enter ; Call the ISR enter function POP {r0, r1} ; Recover return address - MOV lr, r1 ; + MOV lr, r1 ; #endif ; ; /* Context is already saved - just return! */ diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s index 6f870e9b..c60541a2 100644 --- a/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -83,4 +78,3 @@ _tx_thread_interrupt_control: ; ;} END - diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s index 32f155cb..fe575c2d 100644 --- a/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s index cadf01e4..884f815e 100644 --- a/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m0/iar/src/tx_thread_schedule.s b/ports/cortex_m0/iar/src/tx_thread_schedule.s index 6b9830cf..26ee0f12 100644 --- a/ports/cortex_m0/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m0/iar/src/tx_thread_schedule.s @@ -21,32 +21,23 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_thread_preempt_disable - EXTERN _tx_execution_thread_enter - EXTERN _tx_execution_thread_exit -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,6 +71,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -92,7 +86,7 @@ _tx_thread_schedule: ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOVS r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -100,7 +94,7 @@ _tx_thread_schedule: ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; LDR r0, =0x10000000 ; Load PENDSVSET bit @@ -110,21 +104,21 @@ _tx_thread_schedule: ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here: B __tx_wait_here ; Wait for the PendSV to happen ;} ; ; /* Generic context switch-out switch-in handler... */ -; +; PUBLIC PendSV_Handler PUBLIC __tx_PendSVHandler PendSV_Handler: __tx_PendSVHandler: ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler: +; +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -134,7 +128,7 @@ __tx_ts_handler: PUSH {r0, lr} ; Save LR (and r0 just for alignment) BL _tx_execution_thread_exit ; Call the thread exit function POP {r0, r1} ; Recover LR - MOV lr, r1 ; + MOV lr, r1 ; CPSIE i ; Enable interrupts #endif LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address @@ -143,9 +137,9 @@ __tx_ts_handler: LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CMP r1,#0 ; If NULL, skip preservation - BEQ __tx_ts_new ; + BEQ __tx_ts_new ; ; ; /* Recover PSP and preserve current thread context. */ ; @@ -153,15 +147,15 @@ __tx_ts_handler: MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 ; Allocate stack space STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4,r8 ; - MOV r5,r9 ; - MOV r6,r10 ; - MOV r7,r11 ; + MOV r4,r8 ; + MOV r5,r9 ; + MOV r6,r10 ; + MOV r7,r11 ; SUBS r3, r3, #32 ; Allocate stack space - STM r3!, {r4-r7} ; + STM r3!, {r4-r7} ; SUBS r3, r3, #20 ; Allocate stack space - MOV r5, LR ; - STR r5, [r3] ; Save LR on the stack + MOV r5, LR ; + STR r5, [r3] ; Save LR on the stack STR r3, [r1, #8] ; Save its stack pointer ; ; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ @@ -169,7 +163,7 @@ __tx_ts_handler: LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable LDR r5, [r4] ; Pickup current time-slice CMP r5, #0 ; If not active, skip processing - BEQ __tx_ts_new ; + BEQ __tx_ts_new ; ; ; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ ; @@ -180,7 +174,7 @@ __tx_ts_handler: MOVS r5, #0 ; Build clear value STR r5, [r4] ; Clear time-slice ; -; +; ; /* Executing thread is now completely preserved!!! */ ; __tx_ts_new: @@ -189,7 +183,7 @@ __tx_ts_new: ; CPSID i ; Disable interrupts LDR r1, [r2] ; Is there another thread ready to execute? - CMP r1, #0 ; + CMP r1, #0 ; BEQ __tx_ts_wait ; No, skip to the wait processing ; ; /* Yes, another thread is ready for else, make the current thread the new thread. */ @@ -226,26 +220,26 @@ __tx_ts_restore: ADDS r3, r3, #4 ; Position past LR MOV lr, r5 ; Restore LR LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11) - MOV r11,r7 ; - MOV r10,r6 ; - MOV r9,r5 ; - MOV r8,r4 ; - LDM r3!,{r4-r7} ; + MOV r11,r7 ; + MOV r10,r6 ; + MOV r9,r5 ; + MOV r8,r4 ; + LDM r3!,{r4-r7} ; MSR PSP, r3 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: CPSID i ; Disable interrupts LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer - CMP r1, #0 ; If non-NULL, a new thread is ready! + CMP r1, #0 ; If non-NULL, a new thread is ready! BNE __tx_ts_ready ; #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions @@ -255,18 +249,17 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: LDR r7, =0x08000000 ; Build clear PendSV value LDR r5, =0xE000ED04 ; Build base NVIC address - STR r7, [r5] ; Clear any PendSV + STR r7, [r5] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread END - diff --git a/ports/cortex_m0/iar/src/tx_thread_stack_build.s b/ports/cortex_m0/iar/src/tx_thread_stack_build.s index f1073d54..c688c01c 100644 --- a/ports/cortex_m0/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m0/iar/src/tx_thread_stack_build.s @@ -21,23 +21,14 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -77,11 +71,11 @@ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M0 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r8 Initial value for r8 ; r9 Initial value for r9 @@ -103,7 +97,7 @@ _tx_thread_stack_build: ; Stack Bottom: (higher memory address) */ ; LDR r2, [r0, #16] ; Pickup end of stack area - MOVS r3, #0x7 ; + MOVS r3, #0x7 ; BICS r2, r2, r3 ; Align frame for 8-byte alignment SUBS r2, r2, #68 ; Subtract frame size LDR r3, =0xFFFFFFFD ; Build initial LR value @@ -142,4 +136,3 @@ _tx_thread_stack_build: BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m0/iar/src/tx_thread_system_return.s b/ports/cortex_m0/iar/src/tx_thread_system_return.s index 3035fd25..83bc5617 100644 --- a/ports/cortex_m0/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m0/iar/src/tx_thread_system_return.s @@ -20,25 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -79,9 +72,9 @@ _tx_thread_system_return??rA: _tx_thread_system_return: ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; LDR r0, =0x10000000 ; Load PENDSVSET bit LDR r1, =0xE000ED04 ; Load NVIC base STR r0, [r1] ; Set PENDSVBIT in ICSR @@ -92,7 +85,6 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports/cortex_m0/iar/src/tx_timer_interrupt.s b/ports/cortex_m0/iar/src/tx_timer_interrupt.s index a04ccf59..1452a7de 100644 --- a/ports/cortex_m0/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m0/iar/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock @@ -46,14 +35,14 @@ EXTERN _tx_thread_preempt_disable ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M0/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,6 +77,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -110,7 +102,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -228,18 +220,18 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag LDR r1, [r0] ; Is the preempt disable flag set? - CMP r1, #0 ; + CMP r1, #0 ; BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address LDR r1, [r0] ; Pickup the current thread pointer @@ -268,4 +260,3 @@ __tx_timer_nothing_expired: ; ;} END - diff --git a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s index 61c57b5f..992c196f 100644 --- a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s @@ -20,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; ; IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory @@ -87,7 +77,7 @@ __tx_vectors DCD __tx_IntHandler ; Int 0 DCD __tx_IntHandler ; Int 1 DCD __tx_IntHandler ; Int 2 - DCD __tx_IntHandler ; Int 3 + DCD __tx_IntHandler ; Int 3 ; ; AREA ||.text||, CODE, READONLY @@ -96,13 +86,13 @@ Reset_Handler CPSID i LDR R0, =__main BX R0 - + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -136,29 +126,32 @@ Reset_Handler ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ EXPORT _tx_initialize_low_level _tx_initialize_low_level -; +; ; /* Ensure that interrupts are disabled. */ ; CPSID i ; Disable interrupts ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| ; Build first free address - ADDS r1, r1, #4 ; + ADDS r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; LDR r0, =0xE000ED08 ; Build address of NVIC registers LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address + STR r1, [r0] ; Set vector table address ; ; /* Enable the cycle count register. */ ; @@ -166,15 +159,15 @@ _tx_initialize_low_level ; LDR r1, [r0] ; Pickup the current value ; MOVS r2, #1 ; ORRS r1, r1, r2 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Setup Vector Table Offset Register. */ -; +; LDR r0, =0xE000E000 ; Build address of NVIC registers LDR r2, =0xD08 ; Offset to vector base register ADD r0, r0, r2 ; Build vector base register LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address + STR r1, [r0] ; Set vector table address ; ; /* Set system stack pointer from vector value. */ ; @@ -195,30 +188,30 @@ _tx_initialize_low_level ; LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD18 ; - ADD r0, r0, r2 ; + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD1C ; - ADD r0, r0, r2 ; + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers ; Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD20 ; - ADD r0, r0, r2 ; + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; -; +; ;/* Define initial heap/stack routine for the ARM RVCT startup code. ; This routine will set the initial stack and heap locations */ ; @@ -239,14 +232,14 @@ __tx_BadHandler EXPORT __tx_SVCallHandler __tx_SVCallHandler - B __tx_SVCallHandler + B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {r0, lr} - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -269,7 +262,7 @@ SysTick_Handler BX lr ; } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler @@ -280,5 +273,4 @@ __tx_DBGHandler ALIGN LTORG END - diff --git a/ports/cortex_m0/keil/readme_threadx.txt b/ports/cortex_m0/keil/readme_threadx.txt index e34bd0e7..c1c26b3d 100644 --- a/ports/cortex_m0/keil/readme_threadx.txt +++ b/ports/cortex_m0/keil/readme_threadx.txt @@ -139,7 +139,12 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC5 tools. +08-14-2020 ThreadX update of Cortex-M0/Keil port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using Keil tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m0/keil/src/tx_thread_context_restore.s b/ports/cortex_m0/keil/src/tx_thread_context_restore.s index 4ef66308..2c61ab0d 100644 --- a/ports/cortex_m0/keil/src/tx_thread_context_restore.s +++ b/ports/cortex_m0/keil/src/tx_thread_context_restore.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_exit ENDIF @@ -42,13 +32,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -75,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -98,4 +93,4 @@ _tx_thread_context_restore ALIGN LTORG END - + diff --git a/ports/cortex_m0/keil/src/tx_thread_context_save.s b/ports/cortex_m0/keil/src/tx_thread_context_save.s index 52fd2828..834ab578 100644 --- a/ports/cortex_m0/keil/src/tx_thread_context_save.s +++ b/ports/cortex_m0/keil/src/tx_thread_context_save.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_enter ENDIF @@ -43,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -92,10 +87,10 @@ _tx_thread_context_save ENDIF ; ; /* Return to interrupt processing. */ -; +; BX lr ; Return to interrupt processing caller ;} ALIGN LTORG END - + diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s index 7b360417..8d8a6cac 100644 --- a/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -84,4 +79,4 @@ _tx_thread_interrupt_control ALIGN LTORG END - + diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s index b28496d6..60c8eb0d 100644 --- a/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s index 29d0f590..8357b420 100644 --- a/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m0/keil/src/tx_thread_schedule.s b/ports/cortex_m0/keil/src/tx_thread_schedule.s index abcb7c2c..6222286d 100644 --- a/ports/cortex_m0/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m0/keil/src/tx_thread_schedule.s @@ -21,15 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice @@ -37,7 +28,7 @@ IMPORT _tx_thread_preempt_disable IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_thread_enter - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; @@ -48,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,6 +73,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -94,7 +88,7 @@ _tx_thread_schedule ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOVS r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -102,7 +96,7 @@ _tx_thread_schedule ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; LDR r0, =0x10000000 ; Load PENDSVSET bit @@ -112,22 +106,22 @@ _tx_thread_schedule ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here B __tx_wait_here ; Wait for the PendSV to happen ;} ; -; /* Generic context switch-out switch-in handler... Note that this handler is +; /* Generic context switch-out switch-in handler... Note that this handler is ; common for both PendSV and SVCall. */ -; +; EXPORT PendSV_Handler EXPORT __tx_PendSVHandler PendSV_Handler __tx_PendSVHandler ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler +; +__tx_ts_handler IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -137,7 +131,7 @@ __tx_ts_handler PUSH {r0, lr} ; Save LR (and r0 just for alignment) BL _tx_execution_thread_exit ; Call the thread exit function POP {r0, r1} ; Recover LR - MOV lr, r1 ; + MOV lr, r1 ; CPSIE i ; Enable interrupts ENDIF LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address @@ -146,9 +140,9 @@ __tx_ts_handler LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CMP r1,#0 ; If NULL, skip preservation - BEQ __tx_ts_new ; + BEQ __tx_ts_new ; ; ; /* Recover PSP and preserve current thread context. */ ; @@ -156,15 +150,15 @@ __tx_ts_handler MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 ; Allocate stack space STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4,r8 ; - MOV r5,r9 ; - MOV r6,r10 ; - MOV r7,r11 ; + MOV r4,r8 ; + MOV r5,r9 ; + MOV r6,r10 ; + MOV r7,r11 ; SUBS r3, r3, #32 ; Allocate stack space - STM r3!, {r4-r7} ; + STM r3!, {r4-r7} ; SUBS r3, r3, #20 ; Allocate stack space - MOV r5, LR ; - STR r5, [r3] ; Save LR on the stack + MOV r5, LR ; + STR r5, [r3] ; Save LR on the stack STR r3, [r1, #8] ; Save its stack pointer ; ; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ @@ -172,7 +166,7 @@ __tx_ts_handler LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable LDR r5, [r4] ; Pickup current time-slice CMP r5, #0 ; If not active, skip processing - BEQ __tx_ts_new ; + BEQ __tx_ts_new ; ; ; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ ; @@ -183,7 +177,7 @@ __tx_ts_handler MOVS r5, #0 ; Build clear value STR r5, [r4] ; Clear time-slice ; -; +; ; /* Executing thread is now completely preserved!!! */ ; __tx_ts_new @@ -192,7 +186,7 @@ __tx_ts_new ; CPSID i ; Disable interrupts LDR r1, [r2] ; Is there another thread ready to execute? - CMP r1, #0 ; + CMP r1, #0 ; BEQ __tx_ts_wait ; No, skip to the wait processing ; ; /* Yes, another thread is ready for else, make the current thread the new thread. */ @@ -229,26 +223,26 @@ __tx_ts_restore ADDS r3, r3, #4 ; Position past LR MOV lr, r5 ; Restore LR LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11) - MOV r11,r7 ; - MOV r10,r6 ; - MOV r9,r5 ; - MOV r8,r4 ; - LDM r3!,{r4-r7} ; + MOV r11,r7 ; + MOV r10,r6 ; + MOV r9,r5 ; + MOV r8,r4 ; + LDM r3!,{r4-r7} ; MSR PSP, r3 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait CPSID i ; Disable interrupts LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer - CMP r1, #0 ; If non-NULL, a new thread is ready! + CMP r1, #0 ; If non-NULL, a new thread is ready! BNE __tx_ts_ready ; IF :DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions @@ -259,20 +253,19 @@ __tx_ts_ISB CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready LDR r7, =0x08000000 ; Build clear PendSV value LDR r5, =0xE000ED04 ; Build base NVIC address - STR r7, [r5] ; Clear any PendSV + STR r7, [r5] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ALIGN LTORG END - diff --git a/ports/cortex_m0/keil/src/tx_thread_stack_build.s b/ports/cortex_m0/keil/src/tx_thread_stack_build.s index 524eb9f5..142c48a4 100644 --- a/ports/cortex_m0/keil/src/tx_thread_stack_build.s +++ b/ports/cortex_m0/keil/src/tx_thread_stack_build.s @@ -21,22 +21,13 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -76,11 +70,11 @@ EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M0 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r8 Initial value for r8 ; r9 Initial value for r9 @@ -102,7 +96,7 @@ _tx_thread_stack_build ; Stack Bottom: (higher memory address) */ ; LDR r2, [r0, #16] ; Pickup end of stack area - MOVS r3, #0x7 ; + MOVS r3, #0x7 ; BICS r2, r2, r3 ; Align frame for 8-byte alignment SUBS r2, r2, #68 ; Subtract frame size LDR r3, =0xFFFFFFFD ; Build initial LR value @@ -143,4 +137,3 @@ _tx_thread_stack_build ALIGN LTORG END - diff --git a/ports/cortex_m0/keil/src/tx_thread_system_return.s b/ports/cortex_m0/keil/src/tx_thread_system_return.s index a1e11054..a896d2aa 100644 --- a/ports/cortex_m0/keil/src/tx_thread_system_return.s +++ b/ports/cortex_m0/keil/src/tx_thread_system_return.s @@ -20,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -37,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -77,9 +70,9 @@ EXPORT _tx_thread_system_return _tx_thread_system_return ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; LDR r0, =0x10000000 ; Load PENDSVSET bit LDR r1, =0xE000ED04 ; Load NVIC base STR r0, [r1] ; Set PENDSVBIT in ICSR @@ -90,8 +83,8 @@ _tx_thread_system_return CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context - BX lr ; Return to caller + BX lr ; Return to caller NOP ;} - END - + END + diff --git a/ports/cortex_m0/keil/src/tx_timer_interrupt.s b/ports/cortex_m0/keil/src/tx_timer_interrupt.s index d5844d9c..eff615bf 100644 --- a/ports/cortex_m0/keil/src/tx_timer_interrupt.s +++ b/ports/cortex_m0/keil/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; IMPORT _tx_timer_time_slice IMPORT _tx_timer_system_clock @@ -53,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M0/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,6 +77,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -111,7 +103,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -229,18 +221,18 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); ; BL _tx_thread_time_slice ; Call time-slice processing LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag LDR r1, [r0] ; Is the preempt disable flag set? - CMP r1, #0 ; + CMP r1, #0 ; BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address LDR r1, [r0] ; Pickup the current thread pointer @@ -271,4 +263,3 @@ __tx_timer_nothing_expired ALIGN LTORG END - diff --git a/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s index 3e92d7ca..04ddfc47 100644 --- a/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; ; IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory @@ -83,7 +78,7 @@ __tx_vectors DCD __tx_IntHandler ; Int 1 DCD __tx_IntHandler ; Int 2 DCD __tx_IntHandler ; Int 3 - + ; ; AREA ||.text||, CODE, READONLY @@ -99,7 +94,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -133,6 +128,9 @@ Reset_Handler ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -145,24 +143,24 @@ _tx_initialize_low_level CPSID i ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| ; Build first free address - ADD r1, r1, #4 ; + ADD r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register ; LDR r1, [r0] ; Pickup the current value ; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Set system stack pointer from vector value. */ ; @@ -193,11 +191,11 @@ _tx_initialize_low_level ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; -; +; ;/* Define initial heap/stack routine for the ARM RVCT startup code. ; This routine will set the initial stack and heap locations */ ; @@ -213,13 +211,13 @@ __user_initial_stackheap ;/* Define shells for each of the unused vectors. */ ; EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler EXPORT __tx_SVCallHandler __tx_SVCallHandler - B __tx_SVCallHandler + B __tx_SVCallHandler EXPORT __tx_IntHandler @@ -227,7 +225,7 @@ __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {r0, lr} - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -246,7 +244,7 @@ __tx_SysTickHandler BX LR ; } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler diff --git a/ports/cortex_m3/ac5/readme_threadx.txt b/ports/cortex_m3/ac5/readme_threadx.txt index 523279a3..f428a26f 100644 --- a/ports/cortex_m3/ac5/readme_threadx.txt +++ b/ports/cortex_m3/ac5/readme_threadx.txt @@ -135,6 +135,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M3/AC5 port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using AC5 tools. diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_restore.s b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s index eb6c205f..67731bce 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -16,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_exit ENDIF @@ -38,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -71,6 +68,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_save.s b/ports/cortex_m3/ac5/src/tx_thread_context_save.s index 4dfc3352..f11b9a70 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m3/ac5/src/tx_thread_context_save.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -16,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_enter ENDIF @@ -38,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -70,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -86,7 +86,7 @@ _tx_thread_context_save ENDIF ; ; /* Return to interrupt processing. */ -; +; BX lr ; Return to interrupt processing caller ;} ALIGN diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s index 8951fc9d..22ad0fb7 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -30,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -61,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -77,4 +77,3 @@ _tx_thread_interrupt_control ; ;} END - diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s index d7fd0951..6fe29368 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -30,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -61,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s index f5c6d3ba..e27d5cfc 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -30,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -61,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m3/ac5/src/tx_thread_schedule.s b/ports/cortex_m3/ac5/src/tx_thread_schedule.s index a0cbd6a7..c4e749b5 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m3/ac5/src/tx_thread_schedule.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -16,15 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice @@ -32,7 +28,7 @@ IMPORT _tx_thread_preempt_disable IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_thread_enter - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; @@ -43,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,6 +73,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -89,7 +88,7 @@ _tx_thread_schedule ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -97,7 +96,7 @@ _tx_thread_schedule ; /* Enable the interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit @@ -107,21 +106,21 @@ _tx_thread_schedule ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here B __tx_wait_here ; Wait for the PendSV to happen ;} ; ; /* Generic context switching PendSV handler. */ -; +; EXPORT __tx_PendSVHandler EXPORT PendSV_Handler -__tx_PendSVHandler +__tx_PendSVHandler PendSV_Handler ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler +; +__tx_ts_handler IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -139,7 +138,7 @@ __tx_ts_handler LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -163,10 +162,10 @@ __tx_ts_handler ; /* Clear the global time-slice. */ ; STR r3, [r4] ; Clear time-slice -; +; ; /* Executing thread is now completely preserved!!! */ ; -__tx_ts_new +__tx_ts_new ; ; /* Now we are looking for a new thread to execute! */ ; @@ -181,7 +180,7 @@ __tx_ts_new ; ; /* Increment the thread run count. */ ; -__tx_ts_restore +__tx_ts_restore LDR r7, [r1, #4] ; Pickup the current thread run count MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable LDR r5, [r1, #24] ; Pickup thread's current time-slice @@ -209,14 +208,14 @@ __tx_ts_restore MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; - BX lr ; Return to thread! +; + BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; -__tx_ts_wait +__tx_ts_wait CPSID i ; Disable interrupts LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer @@ -229,20 +228,19 @@ __tx_ts_wait CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; -__tx_ts_ready +__tx_ts_ready MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ALIGN LTORG END - diff --git a/ports/cortex_m3/ac5/src/tx_thread_stack_build.s b/ports/cortex_m3/ac5/src/tx_thread_stack_build.s index 023e14c4..8c3d7d17 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m3/ac5/src/tx_thread_stack_build.s @@ -31,7 +31,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,6 +64,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -71,11 +74,11 @@ EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M3 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -135,4 +138,3 @@ _tx_thread_stack_build BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m3/ac5/src/tx_thread_system_return.s b/ports/cortex_m3/ac5/src/tx_thread_system_return.s index 0e88b617..b097896c 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m3/ac5/src/tx_thread_system_return.s @@ -15,16 +15,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -32,7 +22,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,6 +55,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -72,9 +65,9 @@ EXPORT _tx_thread_system_return _tx_thread_system_return ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -85,7 +78,6 @@ _tx_thread_system_return CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports/cortex_m3/ac5/src/tx_timer_interrupt.s b/ports/cortex_m3/ac5/src/tx_timer_interrupt.s index e9a43031..ef7a55f4 100644 --- a/ports/cortex_m3/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m3/ac5/src/tx_timer_interrupt.s @@ -15,17 +15,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; IMPORT _tx_timer_time_slice IMPORT _tx_timer_system_clock @@ -48,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,6 +72,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -106,7 +98,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -223,13 +215,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -263,4 +255,3 @@ __tx_timer_nothing_expired ALIGN LTORG END - diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 058d4981..c04e3f81 100644 --- a/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -20,16 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_initialize.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ @ .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory @@ -57,7 +47,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M3/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,6 +81,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -104,17 +97,17 @@ _tx_initialize_low_level: CPSID i @ @ /* Set base of available memory to end of non-initialised RAM area. */ -@ +@ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address - ADD r1, r1, #4 @ + ADD r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer @ @ /* Setup Vector Table Offset Register. */ -@ +@ MOV r0, #0xE000E000 @ Build address of NVIC registers LDR r1, =vector_table @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address + STR r1, [r0, #0xD08] @ Set vector table address @ @ /* Set system stack pointer from vector value. */ @ @@ -128,7 +121,7 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 @ Build address of DWT register LDR r1, [r0] @ Pickup the current value ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register + STR r1, [r0] @ Enable the cycle count register @ @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ @@ -150,11 +143,11 @@ _tx_initialize_low_level: LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers @ Note: PnSV must be lowest priority, which is 0xFF - + @ @ /* Return to caller. */ -@ - BX lr +@ + BX lr @} @ @@ -190,7 +183,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter @ Call the ISR enter function -#endif +#endif @ /* Do interrupt handler work here */ @ /* BL <your C Function>.... */ @@ -226,7 +219,7 @@ SysTick_Handler: @ /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler @@ -235,8 +228,3 @@ __tx_NMIHandler: .thumb_func __tx_DBGHandler: B __tx_DBGHandler - - - - - diff --git a/ports/cortex_m3/ac6/readme_threadx.txt b/ports/cortex_m3/ac6/readme_threadx.txt index d248b45f..828e24da 100644 --- a/ports/cortex_m3/ac6/readme_threadx.txt +++ b/ports/cortex_m3/ac6/readme_threadx.txt @@ -146,6 +146,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M3/AC6 port. The following files were + changed/added for port specific version 6.0.2: + + *.S Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using AC6 tools. diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S index a4e0b8e2..90afa28c 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_system_stack_ptr @@ -48,13 +38,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M3/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function restores the interrupt context if it is processing a */ @/* nested interrupt. If not, it returns to the interrupt thread if no */ @/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -81,6 +73,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -92,4 +87,3 @@ _tx_thread_context_restore: @ /* Not needed for this port - just return! */ BX lr @} - diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_save.S b/ports/cortex_m3/ac6/src/tx_thread_context_save.S index 24e73026..35ebcdd3 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_save.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr @ @@ -43,13 +33,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M3/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function saves the context of an executing thread in the */ @/* beginning of interrupt processing. The function also ensures that */ @/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S index e24e3200..0ab24fa8 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -37,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M3/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,6 +60,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) @@ -87,6 +82,3 @@ _tx_thread_interrupt_control: BX lr @ Return to caller @/* } */ - - - diff --git a/ports/cortex_m3/ac6/src/tx_thread_schedule.S b/ports/cortex_m3/ac6/src/tx_thread_schedule.S index 71f2a673..bf30619e 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m3/ac6/src/tx_thread_schedule.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -44,7 +35,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M3/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,6 +69,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -91,7 +85,7 @@ _tx_thread_schedule: @ from the PendSV handling routines below. */ @ @ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -@ +@ MOV r0, #0 @ Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag STR r0, [r2, #0] @ Clear preempt disable flag @@ -99,7 +93,7 @@ _tx_thread_schedule: @ /* Enable interrupts */ @ CPSIE i -@ +@ @ /* Enter the scheduler for the first time. */ @ MOV r0, #0x10000000 @ Load PENDSVSET bit @@ -109,14 +103,14 @@ _tx_thread_schedule: ISB @ Flush pipeline @ @ /* Wait here for the PendSV to take place. */ -@ +@ __tx_wait_here: B __tx_wait_here @ Wait for the PendSV to happen @} @ -@ /* Generic context switch-out switch-in handler... Note that this handler is +@ /* Generic context switch-out switch-in handler... Note that this handler is @ common for both PendSV and SVCall. */ -@ +@ .global PendSV_Handler .global __tx_PendSVHandler .thumb_func @@ -125,8 +119,8 @@ PendSV_Handler: __tx_PendSVHandler: @ @ /* Get current thread value and new thread pointer. */ -@ -__tx_ts_handler: +@ +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @@ -144,7 +138,7 @@ __tx_ts_handler: LDR r1, [r0] @ Pickup current thread pointer @ @ /* Determine if there is a current thread to finish preserving. */ -@ +@ CBZ r1, __tx_ts_new @ If NULL, skip preservation @ @ /* Recover PSP and preserve current thread context. */ @@ -169,7 +163,7 @@ __tx_ts_handler: @ STR r3, [r4] @ Clear time-slice @ -@ +@ @ /* Executing thread is now completely preserved!!! */ @ __tx_ts_new: @@ -215,11 +209,11 @@ __tx_ts_restore: MSR PSP, r12 @ Setup the thread's stack pointer @ @ /* Return to thread. */ -@ +@ BX lr @ Return to thread! @ @ /* The following is the idle wait processing... in this case, no threads are ready for execution and the -@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts @ are disabled to allow use of WFI for waiting for a thread to arrive. */ @ __tx_ts_wait: @@ -235,16 +229,16 @@ __tx_ts_wait: CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ -@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are @ already in the handler! */ @ __tx_ts_ready: MOV r7, #0x08000000 @ Build clear PendSV value MOV r8, #0xE000E000 @ Build base NVIC address - STR r7, [r8, #0xD04] @ Clear any PendSV + STR r7, [r8, #0xD04] @ Clear any PendSV @ @ /* Re-enable interrupts and restore new thread. */ -@ +@ CPSIE i @ Enable interrupts B __tx_ts_restore @ Restore the thread - + diff --git a/ports/cortex_m3/ac6/src/tx_thread_stack_build.S b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S index c863e873..a6740472 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ .text .align 4 .syntax unified @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M3/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -79,11 +73,11 @@ .thumb_func _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-M3 should look like the following after it is built: -@ -@ Stack Top: +@ +@ Stack Top: @ LR Interrupted LR (LR at time of PENDSV) @ r4 Initial value for r4 @ r5 Initial value for r5 @@ -142,5 +136,3 @@ _tx_thread_stack_build: @ control block BX lr @ Return to caller @} - - diff --git a/ports/cortex_m3/ac6/src/tx_thread_system_return.S b/ports/cortex_m3/ac6/src/tx_thread_system_return.S index 3fc5f646..bb24456d 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m3/ac6/src/tx_thread_system_return.S @@ -19,15 +19,6 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@/* #define TX_SOURCE_CODE */ -@ -@ -@/* Include necessary system files. */ -@ -@/* #include "tx_api.h" -@ #include "tx_thread.h" -@ #include "tx_timer.h" */ .text 32 @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M3/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @@ -79,9 +73,9 @@ .global _tx_thread_system_return _tx_thread_system_return: @ -@ /* Return to real scheduler via PendSV. Note that this routine is often +@ /* Return to real scheduler via PendSV. Note that this routine is often @ replaced with in-line assembly in tx_port.h to improved performance. */ -@ +@ MOV r0, #0x10000000 @ Load PENDSVSET bit MOV r1, #0xE000E000 @ Load NVIC base STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR @@ -92,7 +86,6 @@ _tx_thread_system_return: CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture _isr_context: - BX lr @ Return to caller + BX lr @ Return to caller @/* } */ - diff --git a/ports/cortex_m3/ac6/src/tx_timer_interrupt.S b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S index e703f54d..060b7f9e 100644 --- a/ports/cortex_m3/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S @@ -20,17 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ -@Define Assembly language external references... @ .global _tx_timer_time_slice .global _tx_timer_system_clock @@ -51,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M3/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +75,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -110,7 +102,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3, #0] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -228,13 +220,13 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired LDR r2, [r3, #0] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing @ @ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); @ BL _tx_thread_time_slice @ Call time-slice processing LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag @@ -266,5 +258,3 @@ __tx_timer_nothing_expired: BX lr @ Return to caller @ @} - - diff --git a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S index 3eaf5731..dd788e9d 100644 --- a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S @@ -20,16 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_initialize.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ @ .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory @@ -59,7 +49,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M3/GNU */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,6 +86,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */ @/* GNU assembly comment, */ @/* resulting in version 6.0.1 */ +@/* 08-14-2020 William E. Lamie Modified Comment(s), clean */ +@/* up whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -109,17 +102,17 @@ _tx_initialize_low_level: CPSID i @ @ /* Set base of available memory to end of non-initialised RAM area. */ -@ +@ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer @ @ /* Setup Vector Table Offset Register. */ -@ +@ MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address + LDR r1, =_vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address @ @ /* Set system stack pointer from vector value. */ @ @@ -133,7 +126,7 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 @ Build address of DWT register LDR r1, [r0] @ Pickup the current value ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register + STR r1, [r0] @ Enable the cycle count register @ @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ @@ -155,11 +148,10 @@ _tx_initialize_low_level: LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers @ Note: PnSV must be lowest priority, which is 0xFF - @ @ /* Return to caller. */ -@ - BX lr +@ + BX lr @} @ @@ -195,7 +187,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter @ Call the ISR enter function -#endif +#endif @ /* Do interrupt handler work here */ @ /* BL <your C Function>.... */ @@ -231,7 +223,7 @@ SysTick_Handler: @ /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler @@ -240,8 +232,3 @@ __tx_NMIHandler: .thumb_func __tx_DBGHandler: B __tx_DBGHandler - - - - - diff --git a/ports/cortex_m3/gnu/readme_threadx.txt b/ports/cortex_m3/gnu/readme_threadx.txt index 92c2045d..d1ccef31 100644 --- a/ports/cortex_m3/gnu/readme_threadx.txt +++ b/ports/cortex_m3/gnu/readme_threadx.txt @@ -143,6 +143,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M3/GNU port. The following files were + changed/added for port specific version 6.0.2: + + *.S Modified comments and whitespace. + 05/19/2020 Initial ThreadX 6.0 version for Cortex-M3 using GNU tools. diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S index 91937893..eef563f8 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_system_stack_ptr @@ -49,13 +39,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M3/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function restores the interrupt context if it is processing a */ @/* nested interrupt. If not, it returns to the interrupt thread if no */ @/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -82,6 +74,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -93,4 +88,3 @@ _tx_thread_context_restore: @ /* Not needed for this port - just return! */ BX lr @} - diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_save.S b/ports/cortex_m3/gnu/src/tx_thread_context_save.S index 29a7631a..fb7a3845 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_save.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_execution_isr_enter @@ -44,13 +34,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M3/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function saves the context of an executing thread in the */ @/* beginning of interrupt processing. The function also ensures that */ @/* the system stack is used upon return to the calling ISR. */ @@ -76,6 +68,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S index 5890a93d..731d4bc1 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -37,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M3/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,6 +60,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) @@ -87,6 +82,3 @@ _tx_thread_interrupt_control: BX lr @ Return to caller @/* } */ - - - diff --git a/ports/cortex_m3/gnu/src/tx_thread_schedule.S b/ports/cortex_m3/gnu/src/tx_thread_schedule.S index 6cf8ab54..f244081e 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m3/gnu/src/tx_thread_schedule.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -46,7 +37,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M3/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -80,6 +71,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -93,7 +87,7 @@ _tx_thread_schedule: @ from the PendSV handling routines below. */ @ @ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -@ +@ MOV r0, #0 @ Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag STR r0, [r2, #0] @ Clear preempt disable flag @@ -101,7 +95,7 @@ _tx_thread_schedule: @ /* Enable interrupts */ @ CPSIE i -@ +@ @ /* Enter the scheduler for the first time. */ @ MOV r0, #0x10000000 @ Load PENDSVSET bit @@ -111,14 +105,14 @@ _tx_thread_schedule: ISB @ Flush pipeline @ @ /* Wait here for the PendSV to take place. */ -@ +@ __tx_wait_here: B __tx_wait_here @ Wait for the PendSV to happen @} @ -@ /* Generic context switch-out switch-in handler... Note that this handler is +@ /* Generic context switch-out switch-in handler... Note that this handler is @ common for both PendSV and SVCall. */ -@ +@ .global PendSV_Handler .global __tx_PendSVHandler .thumb_func @@ -127,8 +121,8 @@ PendSV_Handler: __tx_PendSVHandler: @ @ /* Get current thread value and new thread pointer. */ -@ -__tx_ts_handler: +@ +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @@ -146,7 +140,7 @@ __tx_ts_handler: LDR r1, [r0] @ Pickup current thread pointer @ @ /* Determine if there is a current thread to finish preserving. */ -@ +@ CBZ r1, __tx_ts_new @ If NULL, skip preservation @ @ /* Recover PSP and preserve current thread context. */ @@ -171,7 +165,7 @@ __tx_ts_handler: @ STR r3, [r4] @ Clear time-slice @ -@ +@ @ /* Executing thread is now completely preserved!!! */ @ __tx_ts_new: @@ -217,11 +211,11 @@ __tx_ts_restore: MSR PSP, r12 @ Setup the thread's stack pointer @ @ /* Return to thread. */ -@ +@ BX lr @ Return to thread! @ @ /* The following is the idle wait processing... in this case, no threads are ready for execution and the -@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts @ are disabled to allow use of WFI for waiting for a thread to arrive. */ @ __tx_ts_wait: @@ -237,16 +231,15 @@ __tx_ts_wait: CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ -@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are @ already in the handler! */ @ __tx_ts_ready: MOV r7, #0x08000000 @ Build clear PendSV value MOV r8, #0xE000E000 @ Build base NVIC address - STR r7, [r8, #0xD04] @ Clear any PendSV + STR r7, [r8, #0xD04] @ Clear any PendSV @ @ /* Re-enable interrupts and restore new thread. */ -@ +@ CPSIE i @ Enable interrupts B __tx_ts_restore @ Restore the thread - diff --git a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S index 35d6e2ca..cf8dbb50 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ .text .align 4 .syntax unified @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M3/GNU */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -76,6 +67,9 @@ @/* needed. Removed references */ @/* to stack frame, resulting */ @/* in version 6.0.1 */ +@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -84,11 +78,11 @@ .thumb_func _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-M3 should look like the following after it is built: -@ -@ Stack Top: +@ +@ Stack Top: @ LR Interrupted LR (LR at time of PENDSV) @ r4 Initial value for r4 @ r5 Initial value for r5 @@ -147,5 +141,3 @@ _tx_thread_stack_build: @ control block BX lr @ Return to caller @} - - diff --git a/ports/cortex_m3/gnu/src/tx_thread_system_return.S b/ports/cortex_m3/gnu/src/tx_thread_system_return.S index 0ac8ce08..f16b757f 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m3/gnu/src/tx_thread_system_return.S @@ -19,15 +19,6 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@/* #define TX_SOURCE_CODE */ -@ -@ -@/* Include necessary system files. */ -@ -@/* #include "tx_api.h" -@ #include "tx_thread.h" -@ #include "tx_timer.h" */ .text 32 @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M3/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @@ -79,9 +73,9 @@ .global _tx_thread_system_return _tx_thread_system_return: @ -@ /* Return to real scheduler via PendSV. Note that this routine is often +@ /* Return to real scheduler via PendSV. Note that this routine is often @ replaced with in-line assembly in tx_port.h to improved performance. */ -@ +@ MOV r0, #0x10000000 @ Load PENDSVSET bit MOV r1, #0xE000E000 @ Load NVIC base STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR @@ -92,7 +86,6 @@ _tx_thread_system_return: CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture _isr_context: - BX lr @ Return to caller + BX lr @ Return to caller @/* } */ - diff --git a/ports/cortex_m3/gnu/src/tx_timer_interrupt.S b/ports/cortex_m3/gnu/src/tx_timer_interrupt.S index 340d70e9..26b52acb 100644 --- a/ports/cortex_m3/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m3/gnu/src/tx_timer_interrupt.S @@ -20,17 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ -@Define Assembly language external references... @ .global _tx_timer_time_slice .global _tx_timer_system_clock @@ -51,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M3/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +75,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -110,7 +102,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3, #0] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -228,13 +220,13 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired LDR r2, [r3, #0] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing @ @ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); @ BL _tx_thread_time_slice @ Call time-slice processing LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag @@ -266,5 +258,3 @@ __tx_timer_nothing_expired: BX lr @ Return to caller @ @} - - diff --git a/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s index ab6a346c..1e867c41 100644 --- a/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s @@ -20,42 +20,32 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_initialize_unused_memory - EXTERN _tx_timer_interrupt - EXTERN __vector_table - EXTERN _tx_execution_isr_enter - EXTERN _tx_execution_isr_exit + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __vector_table + EXTERN _tx_execution_isr_enter + EXTERN _tx_execution_isr_exit ; ; SYSTEM_CLOCK EQU 7200000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -89,6 +79,9 @@ __tx_free_memory_start ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -102,7 +95,7 @@ _tx_initialize_low_level: ; ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer STR r0, [r2, #0] ; Save first free memory address @@ -112,13 +105,13 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 ; Build address of DWT register LDR r1, [r0] ; Pickup the current value ORR r1, r1, #1 ; Set the CYCCNTENA bit - STR r1, [r0] ; Enable the cycle count register + STR r1, [r0] ; Enable the cycle count register ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Set system stack pointer from vector value. */ ; @@ -149,8 +142,8 @@ _tx_initialize_low_level: ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; ; @@ -175,7 +168,5 @@ __tx_SysTickHandler: POP {r0, lr} BX LR ; } - - END - + END diff --git a/ports/cortex_m3/iar/readme_threadx.txt b/ports/cortex_m3/iar/readme_threadx.txt index 22a46139..427cc94e 100644 --- a/ports/cortex_m3/iar/readme_threadx.txt +++ b/ports/cortex_m3/iar/readme_threadx.txt @@ -148,6 +148,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M3/IAR port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M3 using IAR's ARM tools. diff --git a/ports/cortex_m3/iar/src/tx_thread_context_restore.s b/ports/cortex_m3/iar/src/tx_thread_context_restore.s index e3e42286..977ac88d 100644 --- a/ports/cortex_m3/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/iar/src/tx_thread_context_restore.s @@ -21,33 +21,25 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_execution_isr_exit ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_execution_isr_exit -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -74,6 +66,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -94,4 +89,4 @@ _tx_thread_context_restore: BX lr ; ;} - END + END diff --git a/ports/cortex_m3/iar/src/tx_thread_context_save.s b/ports/cortex_m3/iar/src/tx_thread_context_save.s index 49e11d68..977c2208 100644 --- a/ports/cortex_m3/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m3/iar/src/tx_thread_context_save.s @@ -21,33 +21,25 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_execution_isr_enter ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_execution_isr_enter -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -73,6 +65,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -82,7 +77,7 @@ _tx_thread_context_save: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the ISR enter function to indicate an ISR is starting. */ -; +; PUSH {r0, lr} ; Save return address BL _tx_execution_isr_enter ; Call the ISR enter function POP {r0, lr} ; Recover return address @@ -93,4 +88,3 @@ _tx_thread_context_save: BX lr ;} END - diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s index d956fd6d..b9685cbd 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -83,4 +78,3 @@ _tx_thread_interrupt_control: ; ;} END - diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s index 38a2083d..cad6eb3c 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s index 356c8aac..1b895380 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m3/iar/src/tx_thread_schedule.s b/ports/cortex_m3/iar/src/tx_thread_schedule.s index aa5f7764..d4f30b62 100644 --- a/ports/cortex_m3/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m3/iar/src/tx_thread_schedule.s @@ -21,32 +21,23 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_execution_thread_enter - EXTERN _tx_execution_thread_exit - EXTERN _tx_thread_preempt_disable -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,6 +71,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -92,7 +86,7 @@ _tx_thread_schedule: ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -100,7 +94,7 @@ _tx_thread_schedule: ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit @@ -110,21 +104,21 @@ _tx_thread_schedule: ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here: B __tx_wait_here ; Wait for the PendSV to happen ;} ; ; /* Generic context PendSV handler. */ -; +; PUBLIC PendSV_Handler PUBLIC __tx_PendSVHandler PendSV_Handler: __tx_PendSVHandler: ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler: +; +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -142,7 +136,7 @@ __tx_ts_handler: LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -167,7 +161,7 @@ __tx_ts_handler: ; STR r3, [r4] ; Clear time-slice ; -; +; ; /* Executing thread is now completely preserved!!! */ ; __tx_ts_new: @@ -213,11 +207,11 @@ __tx_ts_restore: MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: @@ -233,18 +227,17 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ;} END - diff --git a/ports/cortex_m3/iar/src/tx_thread_stack_build.s b/ports/cortex_m3/iar/src/tx_thread_stack_build.s index 96526cc1..92a5c821 100644 --- a/ports/cortex_m3/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m3/iar/src/tx_thread_stack_build.s @@ -21,23 +21,14 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -77,11 +71,11 @@ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -141,4 +135,3 @@ _tx_thread_stack_build: BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m3/iar/src/tx_thread_system_return.s b/ports/cortex_m3/iar/src/tx_thread_system_return.s index fa0ef7a3..1f440cc4 100644 --- a/ports/cortex_m3/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m3/iar/src/tx_thread_system_return.s @@ -20,25 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -79,9 +72,9 @@ _tx_thread_system_return??rA: _tx_thread_system_return: ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -92,7 +85,6 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports/cortex_m3/iar/src/tx_timer_interrupt.s b/ports/cortex_m3/iar/src/tx_timer_interrupt.s index 94af5d87..1d1dc79a 100644 --- a/ports/cortex_m3/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m3/iar/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock @@ -46,14 +35,14 @@ EXTERN _tx_thread_preempt_disable ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -87,6 +76,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -109,7 +101,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -226,13 +218,13 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -265,4 +257,3 @@ __tx_timer_nothing_expired: ; ;} END - diff --git a/ports/cortex_m3/keil/example_build/sample_threadx.c b/ports/cortex_m3/keil/example_build/sample_threadx.c index 9b94bcd4..96c4eb5a 100644 --- a/ports/cortex_m3/keil/example_build/sample_threadx.c +++ b/ports/cortex_m3/keil/example_build/sample_threadx.c @@ -43,7 +43,7 @@ UCHAR thread_5_stack[DEMO_STACK_SIZE]; /* Define the queue area. */ -UCHAR queue_0_area[DEMO_QUEUE_SIZE*sizeof(ULONG)]; +UCHAR queue_0_area[DEMO_QUEUE_SIZE*sizeof(ULONG)]; /* Define thread prototypes. */ diff --git a/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s index 4b55621a..a82c22c2 100644 --- a/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s @@ -20,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; ; IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory @@ -88,7 +78,6 @@ __tx_vectors DCD __tx_IntHandler ; Int 1 DCD __tx_IntHandler ; Int 2 DCD __tx_IntHandler ; Int 3 - ; ; AREA ||.text||, CODE, READONLY @@ -104,7 +93,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M3/RVDS */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -138,6 +127,9 @@ Reset_Handler ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -150,24 +142,24 @@ _tx_initialize_low_level CPSID i ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| ; Build first free address - ADD r1, r1, #4 ; + ADD r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register ; LDR r1, [r0] ; Pickup the current value ; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Set system stack pointer from vector value. */ ; @@ -198,11 +190,11 @@ _tx_initialize_low_level ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; -; +; ;/* Define initial heap/stack routine for the ARM RVCT startup code. ; This routine will set the initial stack and heap locations */ ; @@ -218,13 +210,13 @@ __user_initial_stackheap ;/* Define shells for each of the unused vectors. */ ; EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler EXPORT __tx_SVCallHandler __tx_SVCallHandler - B __tx_SVCallHandler + B __tx_SVCallHandler EXPORT __tx_IntHandler @@ -232,7 +224,7 @@ __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {r0, lr} - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -251,7 +243,7 @@ __tx_SysTickHandler BX LR ; } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler @@ -262,5 +254,3 @@ __tx_DBGHandler ALIGN LTORG END - - diff --git a/ports/cortex_m3/keil/readme_threadx.txt b/ports/cortex_m3/keil/readme_threadx.txt index e0c99485..a88ac72e 100644 --- a/ports/cortex_m3/keil/readme_threadx.txt +++ b/ports/cortex_m3/keil/readme_threadx.txt @@ -142,6 +142,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M3/Keil port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using Keil tools. diff --git a/ports/cortex_m3/keil/src/tx_thread_context_restore.s b/ports/cortex_m3/keil/src/tx_thread_context_restore.s index d78da55e..67731bce 100644 --- a/ports/cortex_m3/keil/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/keil/src/tx_thread_context_restore.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_exit ENDIF @@ -43,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -76,6 +68,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m3/keil/src/tx_thread_context_save.s b/ports/cortex_m3/keil/src/tx_thread_context_save.s index 5645d361..f11b9a70 100644 --- a/ports/cortex_m3/keil/src/tx_thread_context_save.s +++ b/ports/cortex_m3/keil/src/tx_thread_context_save.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_enter ENDIF @@ -43,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -91,7 +86,7 @@ _tx_thread_context_save ENDIF ; ; /* Return to interrupt processing. */ -; +; BX lr ; Return to interrupt processing caller ;} ALIGN diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s index de8f1029..22ad0fb7 100644 --- a/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -82,4 +77,3 @@ _tx_thread_interrupt_control ; ;} END - diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s index 2ff46cad..6fe29368 100644 --- a/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s index 43c20a0f..8123da28 100644 --- a/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m3/keil/src/tx_thread_schedule.s b/ports/cortex_m3/keil/src/tx_thread_schedule.s index 3b9f2cda..c002e1f3 100644 --- a/ports/cortex_m3/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m3/keil/src/tx_thread_schedule.s @@ -21,15 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice @@ -37,7 +28,7 @@ IMPORT _tx_thread_preempt_disable IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_thread_enter - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; @@ -48,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,6 +73,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -94,7 +88,7 @@ _tx_thread_schedule ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -102,7 +96,7 @@ _tx_thread_schedule ; /* Enable the interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit @@ -112,21 +106,21 @@ _tx_thread_schedule ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here B __tx_wait_here ; Wait for the PendSV to happen ;} ; ; /* Generic context switching PendSV handler. */ -; +; EXPORT __tx_PendSVHandler EXPORT PendSV_Handler -__tx_PendSVHandler +__tx_PendSVHandler PendSV_Handler ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler +; +__tx_ts_handler IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -144,7 +138,7 @@ __tx_ts_handler LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -168,10 +162,10 @@ __tx_ts_handler ; /* Clear the global time-slice. */ ; STR r3, [r4] ; Clear time-slice -; +; ; /* Executing thread is now completely preserved!!! */ ; -__tx_ts_new +__tx_ts_new ; ; /* Now we are looking for a new thread to execute! */ ; @@ -186,7 +180,7 @@ __tx_ts_new ; ; /* Increment the thread run count. */ ; -__tx_ts_restore +__tx_ts_restore LDR r7, [r1, #4] ; Pickup the current thread run count MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable LDR r5, [r1, #24] ; Pickup thread's current time-slice @@ -214,14 +208,14 @@ __tx_ts_restore MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; -__tx_ts_wait +__tx_ts_wait CPSID i ; Disable interrupts LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer @@ -234,20 +228,19 @@ __tx_ts_wait CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; -__tx_ts_ready +__tx_ts_ready MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ALIGN LTORG END - diff --git a/ports/cortex_m3/keil/src/tx_thread_stack_build.s b/ports/cortex_m3/keil/src/tx_thread_stack_build.s index bfc38038..9dbcd8aa 100644 --- a/ports/cortex_m3/keil/src/tx_thread_stack_build.s +++ b/ports/cortex_m3/keil/src/tx_thread_stack_build.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -76,11 +79,11 @@ EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M3 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -140,4 +143,3 @@ _tx_thread_stack_build BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m3/keil/src/tx_thread_system_return.s b/ports/cortex_m3/keil/src/tx_thread_system_return.s index 59d59bc6..8443a09a 100644 --- a/ports/cortex_m3/keil/src/tx_thread_system_return.s +++ b/ports/cortex_m3/keil/src/tx_thread_system_return.s @@ -20,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -37,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -77,9 +70,9 @@ EXPORT _tx_thread_system_return _tx_thread_system_return ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -90,7 +83,6 @@ _tx_thread_system_return CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports/cortex_m3/keil/src/tx_timer_interrupt.s b/ports/cortex_m3/keil/src/tx_timer_interrupt.s index e8c34551..6e877312 100644 --- a/ports/cortex_m3/keil/src/tx_timer_interrupt.s +++ b/ports/cortex_m3/keil/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; IMPORT _tx_timer_time_slice IMPORT _tx_timer_system_clock @@ -53,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M3/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,6 +77,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -111,7 +103,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -228,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -268,4 +260,3 @@ __tx_timer_nothing_expired ALIGN LTORG END - diff --git a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S index bc2c31cf..094a575d 100644 --- a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -34,7 +34,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,6 +68,9 @@ HEAP_SIZE = 0x00000000 /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) @@ -87,7 +90,7 @@ _tx_initialize_low_level: /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address - ADD r1, r1, #4 // + ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ @@ -99,7 +102,7 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 // Build address of DWT register LDR r1, [r0] // Pickup the current value ORR r1, r1, #1 // Set the CYCCNTENA bit - STR r1, [r0] // Enable the cycle count register + STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -154,7 +157,7 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - + /* Do interrupt handler work here */ /* .... */ @@ -206,23 +209,23 @@ UsageFault_Handler: TST r1, #0x00100000 // Check for Stack Overflow _unhandled_usage_loop: BEQ _unhandled_usage_loop // If not stack overflow then loop - + // Handle stack overflow STR r1, [r0] // Clear CFSR flag(s) - + #ifdef __ARM_PCS_VFP LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address LDR r1, [r0] // Load FPCCR BIC r1, r1, #1 // Clear the lazy preservation active bit STR r1, [r0] // Store the value #endif - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r0,[r0] // Pick up current thread pointer PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment) BL _tx_thread_stack_error_handler // Call ThreadX/user handler POP {r0,lr} // Restore LR and dummy reg - + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY // Call the thread exit function to indicate the thread is no longer executing. PUSH {r0, lr} // Save LR (and r0 just for alignment) diff --git a/ports/cortex_m33/ac6/readme_threadx.txt b/ports/cortex_m33/ac6/readme_threadx.txt index 767c22c6..cdbbb7a5 100644 --- a/ports/cortex_m33/ac6/readme_threadx.txt +++ b/ports/cortex_m33/ac6/readme_threadx.txt @@ -204,6 +204,14 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M33/AC6 port. The following files were + changed/added for port specific version 6.0.2: + + tx_thread_context_restore.S Remove execution profile kit call. + tx_thread_context_save.S Remove execution profile kit call. + tx_timer_interrupt.S Add DSB instruction before returning. + *.S Modified comments and whitespace. + 06-30-2020 Initial ThreadX 6.0.1 version for Cortex-M33 using AC6 tools. diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S index c35e441e..951d526a 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S @@ -26,17 +26,14 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ +/* This function is not needed for Cortex-M. */ /* */ /* INPUT */ /* */ @@ -59,6 +56,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), remove */ +/* EPK, clean up whitespace */ +/* resulting in version 6.0.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -71,14 +71,6 @@ .thumb_func .type _tx_thread_context_restore, function _tx_thread_context_restore: - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the ISR exit function to indicate an ISR is complete. */ - PUSH {r0,lr} // Save ISR lr (and r0 for 8-byte stack alignment) - BL _tx_execution_isr_exit - POP {r0,lr} -#endif - /* Just return! */ BX lr // } diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_save.S b/ports/cortex_m33/ac6/src/tx_thread_context_save.S index 3519e2ed..36e115f9 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_save.S @@ -26,16 +26,14 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ +/* This function is not needed for Cortex-M. */ /* */ /* INPUT */ /* */ @@ -58,6 +56,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), remove */ +/* EPK, clean up whitespace */ +/* resulting in version 6.0.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -70,14 +71,6 @@ .thumb_func .type _tx_thread_context_save, function _tx_thread_context_save: - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the ISR enter function to indicate an ISR is executing. */ - PUSH {r0,lr} // Save ISR lr (and r0 for 8-byte stack alignment) - BL _tx_execution_isr_enter // Call the ISR enter function - POP {r0,lr} // Recover ISR lr (and r0) -#endif - /* Return to interrupt processing. */ BX lr // } diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S index 716c06a4..bf00b31e 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,6 +57,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S index f8f4eab2..b603c19e 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,6 +57,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S index 90f886f7..7da57ee0 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,6 +57,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m33/ac6/src/tx_thread_schedule.S b/ports/cortex_m33/ac6/src/tx_thread_schedule.S index 8e9f3a0f..4171213a 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m33/ac6/src/tx_thread_schedule.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -84,7 +87,7 @@ _tx_thread_schedule: #ifdef __ARM_PCS_VFP MRS r0, CONTROL // Pickup current CONTROL register - BIC r0, r0, #4 // Clear the FPCA bit + BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register #endif @@ -106,7 +109,7 @@ __tx_wait_here: // } /* Generic context switching PendSV handler. */ - + .section .text .balign 4 .syntax unified @@ -151,7 +154,7 @@ _skip_vfp_save: LDR r4, =_tx_timer_time_slice // Build address of time-slice variable STMDB r12!, {LR} // Save LR on the stack STR r12, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, [r1,#0x90] // Load secure stack index @@ -229,7 +232,7 @@ _skip_secure_restore: LDMIA r12!, {LR} // Pickup LR #ifdef __ARM_PCS_VFP TST LR, #0x10 // Determine if the VFP extended frame is present - BNE _skip_vfp_restore // If not, skip VFP restore + BNE _skip_vfp_restore // If not, skip VFP restore VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -240,7 +243,7 @@ _skip_vfp_restore: BX lr // Return to thread! /* The following is the idle wait processing... in this case, no threads are ready for execution and the - system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts are disabled to allow use of WFI for waiting for a thread to arrive. */ __tx_ts_wait: @@ -256,12 +259,12 @@ __tx_ts_wait: CPSIE i // Enable interrupts B __tx_ts_wait // Loop to continue waiting - /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are already in the handler! */ __tx_ts_ready: MOV r7, #0x08000000 // Build clear PendSV value MOV r8, #0xE000E000 // Build base NVIC address - STR r7, [r8, #0xD04] // Clear any PendSV + STR r7, [r8, #0xD04] // Clear any PendSV /* Re-enable interrupts and restore new thread. */ CPSIE i // Enable interrupts @@ -291,10 +294,10 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + // Unknown SVC argument - just return BX lr - + _tx_svc_secure_alloc: PUSH {r0,lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S index c6a1fa53..6e4ec1b6 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,6 +58,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S index 24d830bd..53aada3b 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,6 +56,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S index c232f89e..f31d35c7 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S index eb3183c0..7651e708 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m33/ac6/src/tx_thread_system_return.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -71,7 +74,7 @@ .thumb_func .type _tx_thread_system_return, function _tx_thread_system_return: - /* Return to real scheduler via PendSV. Note that this routine is often + /* Return to real scheduler via PendSV. Note that this routine is often replaced with in-line assembly in tx_port.h to improved performance. */ MOV r0, #0x10000000 // Load PENDSVSET bit @@ -84,6 +87,6 @@ _tx_thread_system_return: CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture _isr_context: - BX lr // Return to caller + BX lr // Return to caller // } .end diff --git a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S index 9aedaad9..6e49112e 100644 --- a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.0.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +61,10 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +/* whitespace, add DSB before */ +/* returning, resulting */ +/* in version 6.0.2 */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) @@ -90,7 +94,7 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing @@ -206,13 +210,13 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR r2, [r3, #0] // Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag @@ -239,6 +243,7 @@ __tx_timer_not_ts_expiration: __tx_timer_nothing_expired: + DSB // Complete all memory access BX lr // Return to caller // } diff --git a/ports/cortex_m33/iar/readme_threadx.txt b/ports/cortex_m33/iar/readme_threadx.txt index 888a0a71..b804225c 100644 --- a/ports/cortex_m33/iar/readme_threadx.txt +++ b/ports/cortex_m33/iar/readme_threadx.txt @@ -198,6 +198,13 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M33/IAR port. The following files were + changed/added for port specific version 6.0.2: + + tx_thread_context_restore.s Remove execution profile kit call. + tx_thread_context_save.s Remove execution profile kit call. + *.s Modified comments and whitespace. + 06-30-2020 Initial ThreadX 6.0.1 version for Cortex-M33 using IAR's ARM tools. diff --git a/ports/cortex_m33/iar/src/tx_initialize_low_level.s b/ports/cortex_m33/iar/src/tx_initialize_low_level.s index e58c20a1..96ddc643 100644 --- a/ports/cortex_m33/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m33/iar/src/tx_initialize_low_level.s @@ -48,7 +48,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -82,6 +82,9 @@ __tx_free_memory_start ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -94,13 +97,13 @@ _tx_initialize_low_level: CPSID i ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =__tx_free_memory_start ; Build first free address STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__vector_table ; Pickup address of vector table STR r1, [r0, #0xD08] ; Set vector table address @@ -110,7 +113,7 @@ _tx_initialize_low_level: ; LDR r0, =0xE0001000 ; Build address of DWT register ; LDR r1, [r0] ; Pickup the current value ; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Set system stack pointer from vector value. */ ; @@ -141,7 +144,7 @@ _tx_initialize_low_level: ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; +; BX lr ;} ; @@ -158,7 +161,7 @@ __tx_IntHandler: ; VOID InterruptHandler (VOID) ; { PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment) - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -194,34 +197,34 @@ UsageFault_Handler: TST r1, #0x00100000 ; Check for Stack Overflow _unhandled_usage_loop BEQ _unhandled_usage_loop ; If not stack overflow then loop - + ; Handle stack overflow STR r1, [r0] ; Clear CFSR flag(s) - + #ifdef __ARMVFP__ LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address LDR r1, [r0] ; Load FPCCR BIC r1, r1, #1 ; Clear the lazy preservation active bit STR r1, [r0] ; Store the value #endif - + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address LDR r0,[r0] ; Pick up current thread pointer PUSH {r0,lr} ; Save LR (and r0 to maintain stack alignment) BL _tx_thread_stack_error_handler ; Call ThreadX/user handler POP {r0,lr} ; Restore LR and dummy reg - + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; Call the thread exit function to indicate the thread is no longer executing. PUSH {r0, lr} ; Save LR (and r0 just for alignment) BL _tx_execution_thread_exit ; Call the thread exit function POP {r0, lr} ; Recover LR #endif - + MOV r1, #0 ; Build NULL value LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer STR r1, [r0] ; Clear current thread pointer - + ; Return from UsageFault_Handler exception LDR r0, =0xE000ED04 ; Load ICSR LDR r1, =0x10000000 ; Set PENDSVSET bit @@ -234,8 +237,8 @@ _unhandled_usage_loop PUBLIC __tx_NMIHandler __tx_NMIHandler: B __tx_NMIHandler - - + + PUBLIC __tx_DBGHandler __tx_DBGHandler: B __tx_DBGHandler diff --git a/ports/cortex_m33/iar/src/tx_thread_context_restore.s b/ports/cortex_m33/iar/src/tx_thread_context_restore.s index 0fee5f51..690652d9 100644 --- a/ports/cortex_m33/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m33/iar/src/tx_thread_context_restore.s @@ -21,9 +21,6 @@ ;/**************************************************************************/ ; ; - EXTERN _tx_execution_isr_exit -; -; SECTION `.text`:CODE:NOROOT(2) THUMB ;/**************************************************************************/ @@ -31,17 +28,14 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ +;/* This function is not needed for Cortex-M. */ ;/* */ ;/* INPUT */ ;/* */ @@ -64,25 +58,18 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), remove */ +;/* EPK, clean up whitespace */ +;/* resulting in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ PUBLIC _tx_thread_context_restore _tx_thread_context_restore: - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the ISR exit function to indicate an ISR is complete. */ -; - PUSH {r0, lr} ; Save return address - BL _tx_execution_isr_exit ; Call the ISR exit function - POP {r0, lr} ; Recover Save return address -#endif ; ; /* Return to interrupt processing. */ ; BX lr ;} - END - + END diff --git a/ports/cortex_m33/iar/src/tx_thread_context_save.s b/ports/cortex_m33/iar/src/tx_thread_context_save.s index 6774dd3d..df77906f 100644 --- a/ports/cortex_m33/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m33/iar/src/tx_thread_context_save.s @@ -21,9 +21,6 @@ ;/**************************************************************************/ ; ; - EXTERN _tx_execution_isr_enter -; -; SECTION `.text`:CODE:NOROOT(2) THUMB ;/**************************************************************************/ @@ -31,16 +28,14 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ +;/* This function is not needed for Cortex-M. */ ;/* */ ;/* INPUT */ ;/* */ @@ -63,24 +58,19 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), remove */ +;/* EPK, clean up whitespace */ +;/* resulting in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ PUBLIC _tx_thread_context_save _tx_thread_context_save: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the ISR enter function to indicate an ISR is executing. */ -; - PUSH {r0, lr} ; Save return address - BL _tx_execution_isr_enter ; Call the ISR enter function - POP {r0, lr} ; Recover return address -#endif ; ; /* Return to interrupt processing. */ ; BX lr ;} - END - + END + diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s index 0fe770f4..d1308939 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -74,4 +77,4 @@ _tx_thread_interrupt_control: BX lr ; ;} - END + END diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s index 82a8d239..f1148371 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s @@ -21,14 +21,14 @@ ;/**************************************************************************/ ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s index b90c86c0..e5cbbaf8 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m33/iar/src/tx_thread_schedule.s b/ports/cortex_m33/iar/src/tx_thread_schedule.s index 161766f2..37c0397a 100644 --- a/ports/cortex_m33/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m33/iar/src/tx_thread_schedule.s @@ -41,7 +41,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -74,6 +74,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -86,7 +89,7 @@ _tx_thread_schedule: ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -95,7 +98,7 @@ _tx_thread_schedule: ; #ifdef __ARMVFP__ MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register #endif ; @@ -118,12 +121,12 @@ __tx_wait_here: ;} ; ; /* Generic context switching PendSV handler. */ -; +; PUBLIC PendSV_Handler PendSV_Handler: ; ; /* Get current thread value and new thread pointer. */ -; +; __tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -159,7 +162,7 @@ _skip_vfp_save: MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable STMDB r12!, {LR} ; Save LR on the stack STR r12, [r1, #8] ; Save the thread stack pointer - + #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) ; Save secure context LDR r5, [r1,#0x90] ; Load secure stack index @@ -183,7 +186,7 @@ _skip_secure_save: ; /* Clear the global time-slice. */ ; STR r3, [r4] ; Clear time-slice -; +; ; /* Executing thread is now completely preserved!!! */ ; __tx_ts_new: @@ -241,7 +244,7 @@ _skip_secure_restore: LDMIA r12!, {LR} ; Pickup LR #ifdef __ARMVFP__ TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -253,7 +256,7 @@ _skip_vfp_restore: BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: @@ -269,16 +272,16 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread @@ -301,10 +304,10 @@ SVC_Handler: CMP r1, #2 ; Is it a secure stack free request? BEQ _tx_svc_secure_free ; Yes, go there - + ; Unknown SVC argument - just return BX lr - + _tx_svc_secure_alloc: PUSH {r0,lr} ; Save SP and EXC_RETURN LDM r0, {r0-r3} ; Load function parameters from stack diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s index dc414183..650c25db 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_secure_stack_allocate Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -60,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -78,5 +81,5 @@ _tx_thread_secure_stack_allocate: #endif _alloc_return_interrupt_enabled BX lr - + END diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s index 3fb3c795..5b939bb5 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_secure_stack_free Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -58,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -77,4 +80,3 @@ _tx_thread_secure_stack_free: _free_return_interrupt_enabled BX lr END -
\ No newline at end of file diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_build.s b/ports/cortex_m33/iar/src/tx_thread_stack_build.s index 8d63dbf0..25c38cfd 100644 --- a/ports/cortex_m33/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m33/iar/src/tx_thread_stack_build.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -61,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -135,4 +138,3 @@ _tx_thread_stack_build: BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m33/iar/src/tx_thread_system_return.s b/ports/cortex_m33/iar/src/tx_thread_system_return.s index 9d55121e..083dfefe 100644 --- a/ports/cortex_m33/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m33/iar/src/tx_thread_system_return.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -61,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -69,9 +72,9 @@ _tx_thread_system_return??rA: _tx_thread_system_return: ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -82,6 +85,6 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} - END + END diff --git a/ports/cortex_m33/iar/src/tx_timer_interrupt.s b/ports/cortex_m33/iar/src/tx_timer_interrupt.s index cbda08bd..202bc4aa 100644 --- a/ports/cortex_m33/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m33/iar/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M33/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -76,6 +76,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -98,7 +101,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -215,13 +218,13 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -254,4 +257,3 @@ __tx_timer_nothing_expired: ; ;} END - diff --git a/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s index dc0fdd8b..3ca267be 100644 --- a/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s @@ -15,16 +15,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; ; IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory @@ -85,7 +75,6 @@ __tx_vectors DCD __tx_IntHandler ; Int 1 DCD __tx_IntHandler ; Int 2 DCD __tx_IntHandler ; Int 3 - ; ; AREA ||.text||, CODE, READONLY @@ -108,7 +97,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation. */ @@ -142,6 +131,9 @@ Reset_Handler ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -154,24 +146,24 @@ _tx_initialize_low_level CPSID i ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| ; Build first free address - ADD r1, r1, #4 ; + ADD r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register ; LDR r1, [r0] ; Pickup the current value ; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Set system stack pointer from vector value. */ ; @@ -202,11 +194,11 @@ _tx_initialize_low_level ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; -; +; ;/* Define initial heap/stack routine for the ARM RVCT startup code. ; This routine will set the initial stack and heap locations */ ; @@ -222,19 +214,19 @@ __user_initial_stackheap ;/* Define shells for each of the unused vectors. */ ; EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler EXPORT __tx_SVCallHandler __tx_SVCallHandler - B __tx_SVCallHandler + B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {r0, lr} - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -253,7 +245,7 @@ __tx_SysTickHandler BX LR ; } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler @@ -264,4 +256,3 @@ __tx_DBGHandler ALIGN LTORG END - diff --git a/ports/cortex_m4/ac5/readme_threadx.txt b/ports/cortex_m4/ac5/readme_threadx.txt index cfd9ae0b..6664f394 100644 --- a/ports/cortex_m4/ac5/readme_threadx.txt +++ b/ports/cortex_m4/ac5/readme_threadx.txt @@ -112,22 +112,22 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 0x78 s30 0x7C s31 0x80 fpscr - 0x84 r4 - 0x88 r5 - 0x8C r6 - 0x90 r7 - 0x94 r8 - 0x98 r9 - 0x9C r10 (sl) - 0xA0 r11 + 0x84 r4 + 0x88 r5 + 0x8C r6 + 0x90 r7 + 0x94 r8 + 0x98 r9 + 0x9C r10 + 0xA0 r11 0xA4 r0 (Hardware stack starts here!!) - 0xA8 r1 - 0xAC r2 - 0xB0 r3 - 0xB4 r12 - 0xB8 lr - 0xBC pc - 0xC0 xPSR + 0xA8 r1 + 0xAC r2 + 0xB0 r3 + 0xB4 r12 + 0xB8 lr + 0xBC pc + 0xC0 xPSR 5. Improving Performance @@ -197,6 +197,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M4/AC5 port. The following files were + changed/added for port specific version 6.0.2: + tx_thread_context_save.s Fixed register names. + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using AC5 tools. diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_restore.s b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s index 6d310a17..9f65cc8c 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -16,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_exit ENDIF @@ -38,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -71,6 +68,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_save.s b/ports/cortex_m4/ac5/src/tx_thread_context_save.s index 052c3e5a..aa86e10d 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m4/ac5/src/tx_thread_context_save.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -16,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_enter ENDIF @@ -38,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -70,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -82,11 +82,11 @@ _tx_thread_context_save ; PUSH {r0, lr} ; Save ISR lr BL _tx_execution_isr_enter ; Call the ISR enter function - POP {lr0, r} ; Recover ISR lr + POP {r0, lr} ; Recover ISR lr ENDIF ; ; /* Return to interrupt processing. */ -; +; BX lr ; Return to interrupt processing caller ;} ALIGN diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s index e97c7a47..9ca90dd7 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -30,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -61,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -77,4 +77,3 @@ _tx_thread_interrupt_control ; ;} END - diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s index e366e44b..861fbbe8 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -30,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation. */ @@ -61,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s index 1d0bffb6..1ef06c78 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -30,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation. */ @@ -61,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m4/ac5/src/tx_thread_schedule.s b/ports/cortex_m4/ac5/src/tx_thread_schedule.s index e78a040d..158783fa 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m4/ac5/src/tx_thread_schedule.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -16,15 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice @@ -32,7 +28,7 @@ IMPORT _tx_thread_preempt_disable IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_thread_enter - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; @@ -43,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,6 +73,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -89,7 +88,7 @@ _tx_thread_schedule ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -98,14 +97,14 @@ _tx_thread_schedule ; IF {TARGET_FPU_VFP} = {TRUE} MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register ENDIF ; ; /* Enable the interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit @@ -115,21 +114,21 @@ _tx_thread_schedule ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here B __tx_wait_here ; Wait for the PendSV to happen ;} ; ; /* Generic context switching PendSV handler. */ -; +; EXPORT __tx_PendSVHandler EXPORT PendSV_Handler -__tx_PendSVHandler +__tx_PendSVHandler PendSV_Handler ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler +; +__tx_ts_handler IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -147,7 +146,7 @@ __tx_ts_handler LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -177,10 +176,10 @@ _skip_vfp_save ; /* Clear the global time-slice. */ ; STR r3, [r4] ; Clear time-slice -; +; ; /* Executing thread is now completely preserved!!! */ ; -__tx_ts_new +__tx_ts_new ; ; /* Now we are looking for a new thread to execute! */ ; @@ -195,7 +194,7 @@ __tx_ts_new ; ; /* Increment the thread run count. */ ; -__tx_ts_restore +__tx_ts_restore LDR r7, [r1, #4] ; Pickup the current thread run count MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable LDR r5, [r1, #24] ; Pickup thread's current time-slice @@ -221,7 +220,7 @@ __tx_ts_restore LDMIA r12!, {LR} ; Pickup LR IF {TARGET_FPU_VFP} = {TRUE} TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore ENDIF @@ -229,14 +228,14 @@ _skip_vfp_restore MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; -__tx_ts_wait +__tx_ts_wait CPSID i ; Disable interrupts LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer @@ -249,16 +248,16 @@ __tx_ts_wait CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; -__tx_ts_ready +__tx_ts_ready MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread @@ -266,7 +265,7 @@ __tx_ts_ready EXPORT tx_thread_fpu_enable tx_thread_fpu_enable ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -274,7 +273,7 @@ tx_thread_fpu_enable EXPORT tx_thread_fpu_disable tx_thread_fpu_disable ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -290,4 +289,3 @@ _tx_vfp_access ALIGN LTORG END - diff --git a/ports/cortex_m4/ac5/src/tx_thread_stack_build.s b/ports/cortex_m4/ac5/src/tx_thread_stack_build.s index d9cf2a1f..2b3b76f8 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m4/ac5/src/tx_thread_stack_build.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -31,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,6 +69,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -71,11 +79,11 @@ EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M4 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -135,4 +143,3 @@ _tx_thread_stack_build BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m4/ac5/src/tx_thread_system_return.s b/ports/cortex_m4/ac5/src/tx_thread_system_return.s index c61d0e53..ece0b1cf 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m4/ac5/src/tx_thread_system_return.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -32,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -72,9 +70,9 @@ EXPORT _tx_thread_system_return _tx_thread_system_return ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -85,7 +83,6 @@ _tx_thread_system_return CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports/cortex_m4/ac5/src/tx_timer_interrupt.s b/ports/cortex_m4/ac5/src/tx_timer_interrupt.s index af94c70c..33793ad0 100644 --- a/ports/cortex_m4/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m4/ac5/src/tx_timer_interrupt.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; IMPORT _tx_timer_time_slice IMPORT _tx_timer_system_clock @@ -48,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,6 +77,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -106,7 +103,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -223,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -263,4 +260,3 @@ __tx_timer_nothing_expired ALIGN LTORG END - diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 5c721be1..272484cc 100644 --- a/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -20,16 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_initialize.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ @ .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory @@ -57,7 +47,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M4/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,6 +81,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -104,17 +97,17 @@ _tx_initialize_low_level: CPSID i @ @ /* Set base of available memory to end of non-initialised RAM area. */ -@ +@ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address - ADD r1, r1, #4 @ + ADD r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer @ @ /* Setup Vector Table Offset Register. */ -@ +@ MOV r0, #0xE000E000 @ Build address of NVIC registers LDR r1, =vector_table @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address + STR r1, [r0, #0xD08] @ Set vector table address @ @ /* Set system stack pointer from vector value. */ @ @@ -128,7 +121,7 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 @ Build address of DWT register LDR r1, [r0] @ Pickup the current value ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register + STR r1, [r0] @ Enable the cycle count register @ @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ @@ -150,11 +143,11 @@ _tx_initialize_low_level: LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers @ Note: PnSV must be lowest priority, which is 0xFF - + @ @ /* Return to caller. */ -@ - BX lr +@ + BX lr @} @ @@ -190,7 +183,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter @ Call the ISR enter function -#endif +#endif @ /* Do interrupt handler work here */ @ /* BL <your C Function>.... */ @@ -226,7 +219,7 @@ SysTick_Handler: @ /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler @@ -235,4 +228,3 @@ __tx_NMIHandler: .thumb_func __tx_DBGHandler: B __tx_DBGHandler - diff --git a/ports/cortex_m4/ac6/readme_threadx.txt b/ports/cortex_m4/ac6/readme_threadx.txt index 4df37323..928be3df 100644 --- a/ports/cortex_m4/ac6/readme_threadx.txt +++ b/ports/cortex_m4/ac6/readme_threadx.txt @@ -211,6 +211,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M4/AC6 port. The following files were + changed/added for port specific version 6.0.2: + + *.S Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using AC6 tools. diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S index abcda29c..49baa253 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_system_stack_ptr @@ -48,13 +38,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M4/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function restores the interrupt context if it is processing a */ @/* nested interrupt. If not, it returns to the interrupt thread if no */ @/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -81,6 +73,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -92,4 +87,3 @@ _tx_thread_context_restore: @ /* Not needed for this port - just return! */ BX lr @} - diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_save.S b/ports/cortex_m4/ac6/src/tx_thread_context_save.S index c198f6d3..ed1831f2 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_save.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr @ @@ -43,13 +33,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M4/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function saves the context of an executing thread in the */ @/* beginning of interrupt processing. The function also ensures that */ @/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S index cc317cf3..c6facbc6 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -37,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M4/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,6 +60,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) @@ -87,6 +82,3 @@ _tx_thread_interrupt_control: BX lr @ Return to caller @/* } */ - - - diff --git a/ports/cortex_m4/ac6/src/tx_thread_schedule.S b/ports/cortex_m4/ac6/src/tx_thread_schedule.S index b3b78246..614bf3c1 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m4/ac6/src/tx_thread_schedule.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -44,7 +35,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M4/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,6 +69,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -91,7 +85,7 @@ _tx_thread_schedule: @ from the PendSV handling routines below. */ @ @ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -@ +@ MOV r0, #0 @ Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag STR r0, [r2, #0] @ Clear preempt disable flag @@ -100,14 +94,14 @@ _tx_thread_schedule: @ #ifdef TX_ENABLE_FPU_SUPPORT MRS r0, CONTROL @ Pickup current CONTROL register - BIC r0, r0, #4 @ Clear the FPCA bit + BIC r0, r0, #4 @ Clear the FPCA bit MSR CONTROL, r0 @ Setup new CONTROL register #endif @ @ /* Enable interrupts */ @ CPSIE i -@ +@ @ /* Enter the scheduler for the first time. */ @ MOV r0, #0x10000000 @ Load PENDSVSET bit @@ -117,14 +111,14 @@ _tx_thread_schedule: ISB @ Flush pipeline @ @ /* Wait here for the PendSV to take place. */ -@ +@ __tx_wait_here: B __tx_wait_here @ Wait for the PendSV to happen @} @ -@ /* Generic context switch-out switch-in handler... Note that this handler is +@ /* Generic context switch-out switch-in handler... Note that this handler is @ common for both PendSV and SVCall. */ -@ +@ .global PendSV_Handler .global __tx_PendSVHandler .thumb_func @@ -133,8 +127,8 @@ PendSV_Handler: __tx_PendSVHandler: @ @ /* Get current thread value and new thread pointer. */ -@ -__tx_ts_handler: +@ +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @@ -152,7 +146,7 @@ __tx_ts_handler: LDR r1, [r0] @ Pickup current thread pointer @ @ /* Determine if there is a current thread to finish preserving. */ -@ +@ CBZ r1, __tx_ts_new @ If NULL, skip preservation @ @ /* Recover PSP and preserve current thread context. */ @@ -183,7 +177,7 @@ _skip_vfp_save: @ STR r3, [r4] @ Clear time-slice @ -@ +@ @ /* Executing thread is now completely preserved!!! */ @ __tx_ts_new: @@ -227,7 +221,7 @@ __tx_ts_restore: LDMIA r12!, {LR} @ Pickup LR #ifdef TX_ENABLE_FPU_SUPPORT TST LR, #0x10 @ Determine if the VFP extended frame is present - BNE _skip_vfp_restore @ If not, skip VFP restore + BNE _skip_vfp_restore @ If not, skip VFP restore VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -235,11 +229,11 @@ _skip_vfp_restore: MSR PSP, r12 @ Setup the thread's stack pointer @ @ /* Return to thread. */ -@ +@ BX lr @ Return to thread! @ @ /* The following is the idle wait processing... in this case, no threads are ready for execution and the -@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts @ are disabled to allow use of WFI for waiting for a thread to arrive. */ @ __tx_ts_wait: @@ -255,19 +249,18 @@ __tx_ts_wait: CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ -@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are @ already in the handler! */ @ __tx_ts_ready: MOV r7, #0x08000000 @ Build clear PendSV value MOV r8, #0xE000E000 @ Build base NVIC address - STR r7, [r8, #0xD04] @ Clear any PendSV + STR r7, [r8, #0xD04] @ Clear any PendSV @ @ /* Re-enable interrupts and restore new thread. */ -@ +@ CPSIE i @ Enable interrupts B __tx_ts_restore @ Restore the thread - #ifdef TX_ENABLE_FPU_SUPPORT @@ -275,7 +268,7 @@ __tx_ts_ready: .thumb_func tx_thread_fpu_enable: @ -@ /* Automatic VPF logic is supported, this function is present only for +@ /* Automatic VPF logic is supported, this function is present only for @ backward compatibility purposes and therefore simply returns. */ @ BX LR @ Return to caller @@ -284,11 +277,9 @@ tx_thread_fpu_enable: .thumb_func tx_thread_fpu_disable: @ -@ /* Automatic VPF logic is supported, this function is present only for +@ /* Automatic VPF logic is supported, this function is present only for @ backward compatibility purposes and therefore simply returns. */ @ BX LR @ Return to caller - #endif - diff --git a/ports/cortex_m4/ac6/src/tx_thread_stack_build.S b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S index 1f17511c..2dd6acd2 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ .text .align 4 .syntax unified @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M4/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -79,11 +73,11 @@ .thumb_func _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-M4 should look like the following after it is built: -@ -@ Stack Top: +@ +@ Stack Top: @ LR Interrupted LR (LR at time of PENDSV) @ r4 Initial value for r4 @ r5 Initial value for r5 @@ -142,5 +136,3 @@ _tx_thread_stack_build: @ control block BX lr @ Return to caller @} - - diff --git a/ports/cortex_m4/ac6/src/tx_thread_system_return.S b/ports/cortex_m4/ac6/src/tx_thread_system_return.S index d7e24361..e163c9dd 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m4/ac6/src/tx_thread_system_return.S @@ -19,15 +19,6 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@/* #define TX_SOURCE_CODE */ -@ -@ -@/* Include necessary system files. */ -@ -@/* #include "tx_api.h" -@ #include "tx_thread.h" -@ #include "tx_timer.h" */ .text 32 @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M4/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @@ -79,9 +73,9 @@ .global _tx_thread_system_return _tx_thread_system_return: @ -@ /* Return to real scheduler via PendSV. Note that this routine is often +@ /* Return to real scheduler via PendSV. Note that this routine is often @ replaced with in-line assembly in tx_port.h to improved performance. */ -@ +@ MOV r0, #0x10000000 @ Load PENDSVSET bit MOV r1, #0xE000E000 @ Load NVIC base STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR @@ -92,7 +86,6 @@ _tx_thread_system_return: CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture _isr_context: - BX lr @ Return to caller + BX lr @ Return to caller @/* } */ - diff --git a/ports/cortex_m4/ac6/src/tx_timer_interrupt.S b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S index 2fbf230b..72085640 100644 --- a/ports/cortex_m4/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S @@ -20,17 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ -@Define Assembly language external references... @ .global _tx_timer_time_slice .global _tx_timer_system_clock @@ -51,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M4/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +75,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -110,7 +102,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3, #0] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -228,13 +220,13 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired LDR r2, [r3, #0] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing @ @ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); @ BL _tx_thread_time_slice @ Call time-slice processing LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag @@ -266,5 +258,3 @@ __tx_timer_nothing_expired: BX lr @ Return to caller @ @} - - diff --git a/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S index 00db7ac2..16d055d3 100644 --- a/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S @@ -20,16 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_initialize.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ @ .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory @@ -59,7 +49,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M4/GNU */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +85,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ @/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */ @/* GNU assembly comment, */ -@/* resulting in version 6.0.1 */ +@/* resulting in version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -109,17 +102,17 @@ _tx_initialize_low_level: CPSID i @ @ /* Set base of available memory to end of non-initialised RAM area. */ -@ +@ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer @ @ /* Setup Vector Table Offset Register. */ -@ +@ MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address + LDR r1, =_vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address @ @ /* Set system stack pointer from vector value. */ @ @@ -133,7 +126,7 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 @ Build address of DWT register LDR r1, [r0] @ Pickup the current value ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register + STR r1, [r0] @ Enable the cycle count register @ @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ @@ -155,11 +148,11 @@ _tx_initialize_low_level: LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers @ Note: PnSV must be lowest priority, which is 0xFF - + @ @ /* Return to caller. */ -@ - BX lr +@ + BX lr @} @ @@ -195,7 +188,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter @ Call the ISR enter function -#endif +#endif @ /* Do interrupt handler work here */ @ /* BL <your C Function>.... */ @@ -231,7 +224,7 @@ SysTick_Handler: @ /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler @@ -240,4 +233,3 @@ __tx_NMIHandler: .thumb_func __tx_DBGHandler: B __tx_DBGHandler - diff --git a/ports/cortex_m4/gnu/readme_threadx.txt b/ports/cortex_m4/gnu/readme_threadx.txt index a8c7c684..ebc6f2af 100644 --- a/ports/cortex_m4/gnu/readme_threadx.txt +++ b/ports/cortex_m4/gnu/readme_threadx.txt @@ -208,6 +208,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M4/GNU port. The following files were + changed/added for port specific version 6.0.2: + + *.S Modified comments and whitespace. + 05/19/2020 Initial ThreadX 6.0 version for Cortex-M4 using GNU tools. diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S index 37e37c28..29a1c0ce 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_system_stack_ptr @@ -49,13 +39,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M4/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function restores the interrupt context if it is processing a */ @/* nested interrupt. If not, it returns to the interrupt thread if no */ @/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -82,6 +74,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -93,4 +88,3 @@ _tx_thread_context_restore: @ /* Not needed for this port - just return! */ BX lr @} - diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_save.S b/ports/cortex_m4/gnu/src/tx_thread_context_save.S index b2196ac4..8cef0b96 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_save.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_execution_isr_enter @@ -44,13 +34,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M4/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function saves the context of an executing thread in the */ @/* beginning of interrupt processing. The function also ensures that */ @/* the system stack is used upon return to the calling ISR. */ @@ -76,6 +68,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S index 31e83f46..9c990ca0 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S @@ -20,14 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - .text 32 .align 4 @@ -37,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M4/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,6 +60,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) @@ -87,6 +82,3 @@ _tx_thread_interrupt_control: BX lr @ Return to caller @/* } */ - - - diff --git a/ports/cortex_m4/gnu/src/tx_thread_schedule.S b/ports/cortex_m4/gnu/src/tx_thread_schedule.S index 11bdbe09..8b0ecb16 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m4/gnu/src/tx_thread_schedule.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -46,7 +37,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M4/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -80,6 +71,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -93,7 +87,7 @@ _tx_thread_schedule: @ from the PendSV handling routines below. */ @ @ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -@ +@ MOV r0, #0 @ Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag STR r0, [r2, #0] @ Clear preempt disable flag @@ -102,14 +96,14 @@ _tx_thread_schedule: @ #ifdef TX_ENABLE_FPU_SUPPORT MRS r0, CONTROL @ Pickup current CONTROL register - BIC r0, r0, #4 @ Clear the FPCA bit + BIC r0, r0, #4 @ Clear the FPCA bit MSR CONTROL, r0 @ Setup new CONTROL register #endif @ @ /* Enable interrupts */ @ CPSIE i -@ +@ @ /* Enter the scheduler for the first time. */ @ MOV r0, #0x10000000 @ Load PENDSVSET bit @@ -119,14 +113,14 @@ _tx_thread_schedule: ISB @ Flush pipeline @ @ /* Wait here for the PendSV to take place. */ -@ +@ __tx_wait_here: B __tx_wait_here @ Wait for the PendSV to happen @} @ -@ /* Generic context switch-out switch-in handler... Note that this handler is +@ /* Generic context switch-out switch-in handler... Note that this handler is @ common for both PendSV and SVCall. */ -@ +@ .global PendSV_Handler .global __tx_PendSVHandler .thumb_func @@ -135,8 +129,8 @@ PendSV_Handler: __tx_PendSVHandler: @ @ /* Get current thread value and new thread pointer. */ -@ -__tx_ts_handler: +@ +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @@ -154,7 +148,7 @@ __tx_ts_handler: LDR r1, [r0] @ Pickup current thread pointer @ @ /* Determine if there is a current thread to finish preserving. */ -@ +@ CBZ r1, __tx_ts_new @ If NULL, skip preservation @ @ /* Recover PSP and preserve current thread context. */ @@ -185,7 +179,7 @@ _skip_vfp_save: @ STR r3, [r4] @ Clear time-slice @ -@ +@ @ /* Executing thread is now completely preserved!!! */ @ __tx_ts_new: @@ -229,7 +223,7 @@ __tx_ts_restore: LDMIA r12!, {LR} @ Pickup LR #ifdef TX_ENABLE_FPU_SUPPORT TST LR, #0x10 @ Determine if the VFP extended frame is present - BNE _skip_vfp_restore @ If not, skip VFP restore + BNE _skip_vfp_restore @ If not, skip VFP restore VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -237,11 +231,11 @@ _skip_vfp_restore: MSR PSP, r12 @ Setup the thread's stack pointer @ @ /* Return to thread. */ -@ +@ BX lr @ Return to thread! @ @ /* The following is the idle wait processing... in this case, no threads are ready for execution and the -@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts @ are disabled to allow use of WFI for waiting for a thread to arrive. */ @ __tx_ts_wait: @@ -257,19 +251,18 @@ __tx_ts_wait: CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ -@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are @ already in the handler! */ @ __tx_ts_ready: MOV r7, #0x08000000 @ Build clear PendSV value MOV r8, #0xE000E000 @ Build base NVIC address - STR r7, [r8, #0xD04] @ Clear any PendSV + STR r7, [r8, #0xD04] @ Clear any PendSV @ @ /* Re-enable interrupts and restore new thread. */ -@ +@ CPSIE i @ Enable interrupts B __tx_ts_restore @ Restore the thread - #ifdef TX_ENABLE_FPU_SUPPORT @@ -277,7 +270,7 @@ __tx_ts_ready: .thumb_func tx_thread_fpu_enable: @ -@ /* Automatic VPF logic is supported, this function is present only for +@ /* Automatic VPF logic is supported, this function is present only for @ backward compatibility purposes and therefore simply returns. */ @ BX LR @ Return to caller @@ -286,11 +279,9 @@ tx_thread_fpu_enable: .thumb_func tx_thread_fpu_disable: @ -@ /* Automatic VPF logic is supported, this function is present only for +@ /* Automatic VPF logic is supported, this function is present only for @ backward compatibility purposes and therefore simply returns. */ @ BX LR @ Return to caller - #endif - diff --git a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S index 9307686e..5c0e0377 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ .text .align 4 .syntax unified @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M4/GNU */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -76,6 +67,9 @@ @/* needed. Removed references */ @/* to stack frame, resulting */ @/* in version 6.0.1 */ +@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -84,11 +78,11 @@ .thumb_func _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-M4 should look like the following after it is built: -@ -@ Stack Top: +@ +@ Stack Top: @ LR Interrupted LR (LR at time of PENDSV) @ r4 Initial value for r4 @ r5 Initial value for r5 @@ -147,5 +141,3 @@ _tx_thread_stack_build: @ control block BX lr @ Return to caller @} - - diff --git a/ports/cortex_m4/gnu/src/tx_thread_system_return.S b/ports/cortex_m4/gnu/src/tx_thread_system_return.S index d570bb73..65907ae7 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m4/gnu/src/tx_thread_system_return.S @@ -19,15 +19,6 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@/* #define TX_SOURCE_CODE */ -@ -@ -@/* Include necessary system files. */ -@ -@/* #include "tx_api.h" -@ #include "tx_thread.h" -@ #include "tx_timer.h" */ .text 32 @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M4/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @@ -79,9 +73,9 @@ .global _tx_thread_system_return _tx_thread_system_return: @ -@ /* Return to real scheduler via PendSV. Note that this routine is often +@ /* Return to real scheduler via PendSV. Note that this routine is often @ replaced with in-line assembly in tx_port.h to improved performance. */ -@ +@ MOV r0, #0x10000000 @ Load PENDSVSET bit MOV r1, #0xE000E000 @ Load NVIC base STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR @@ -92,7 +86,6 @@ _tx_thread_system_return: CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture _isr_context: - BX lr @ Return to caller + BX lr @ Return to caller @/* } */ - diff --git a/ports/cortex_m4/gnu/src/tx_timer_interrupt.S b/ports/cortex_m4/gnu/src/tx_timer_interrupt.S index 6d96eaf9..bbb5c08b 100644 --- a/ports/cortex_m4/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m4/gnu/src/tx_timer_interrupt.S @@ -20,17 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ -@Define Assembly language external references... @ .global _tx_timer_time_slice .global _tx_timer_system_clock @@ -51,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M4/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +75,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -110,7 +102,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3, #0] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -228,13 +220,13 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired LDR r2, [r3, #0] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing @ @ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); @ BL _tx_thread_time_slice @ Call time-slice processing LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag @@ -266,5 +258,3 @@ __tx_timer_nothing_expired: BX lr @ Return to caller @ @} - - diff --git a/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s index c252a33f..50eb54dc 100644 --- a/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s @@ -20,42 +20,32 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_initialize_unused_memory - EXTERN _tx_timer_interrupt - EXTERN __vector_table - EXTERN _tx_execution_isr_enter - EXTERN _tx_execution_isr_exit + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __vector_table + EXTERN _tx_execution_isr_enter + EXTERN _tx_execution_isr_exit ; ; SYSTEM_CLOCK EQU 25000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -89,20 +79,23 @@ __tx_free_memory_start ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ PUBLIC _tx_initialize_low_level _tx_initialize_low_level: -; +; ; /* Ensure that interrupts are disabled. */ ; CPSID i ; Disable interrupts ; ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer STR r0, [r2, #0] ; Save first free memory address @@ -112,13 +105,13 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 ; Build address of DWT register LDR r1, [r0] ; Pickup the current value ORR r1, r1, #1 ; Set the CYCCNTENA bit - STR r1, [r0] ; Enable the cycle count register + STR r1, [r0] ; Enable the cycle count register ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Set system stack pointer from vector value. */ ; @@ -149,8 +142,8 @@ _tx_initialize_low_level: ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; PUBLIC SysTick_Handler @@ -173,4 +166,3 @@ SysTick_Handler: BX LR ; } END - diff --git a/ports/cortex_m4/iar/readme_threadx.txt b/ports/cortex_m4/iar/readme_threadx.txt index c6e7bb1f..22a5dc7f 100644 --- a/ports/cortex_m4/iar/readme_threadx.txt +++ b/ports/cortex_m4/iar/readme_threadx.txt @@ -214,6 +214,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M4/IAR port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using IAR's ARM tools. diff --git a/ports/cortex_m4/iar/src/tx_thread_context_restore.s b/ports/cortex_m4/iar/src/tx_thread_context_restore.s index 1930c870..a3d4d7a3 100644 --- a/ports/cortex_m4/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/iar/src/tx_thread_context_restore.s @@ -21,33 +21,25 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_execution_isr_exit ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_execution_isr_exit -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -74,6 +66,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -94,5 +89,4 @@ _tx_thread_context_restore: BX lr ; ;} - END - + END diff --git a/ports/cortex_m4/iar/src/tx_thread_context_save.s b/ports/cortex_m4/iar/src/tx_thread_context_save.s index ab563506..5ce75e63 100644 --- a/ports/cortex_m4/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m4/iar/src/tx_thread_context_save.s @@ -21,33 +21,25 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_execution_isr_enter ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_execution_isr_enter -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -73,6 +65,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -82,7 +77,7 @@ _tx_thread_context_save: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the ISR enter function to indicate an ISR is starting. */ -; +; PUSH {r0, lr} ; Save return address BL _tx_execution_isr_enter ; Call the ISR enter function POP {r0, lr} ; Recover return address diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s index e04f8ceb..c036b06f 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -83,4 +78,3 @@ _tx_thread_interrupt_control: ; ;} END - diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s index 7807d5c8..3a6557bc 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s index 2159ae40..d57b60d9 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m4/iar/src/tx_thread_schedule.s b/ports/cortex_m4/iar/src/tx_thread_schedule.s index df0e74b2..62785071 100644 --- a/ports/cortex_m4/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m4/iar/src/tx_thread_schedule.s @@ -21,32 +21,23 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_execution_thread_enter - EXTERN _tx_execution_thread_exit - EXTERN _tx_thread_preempt_disable -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,6 +71,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -92,7 +86,7 @@ _tx_thread_schedule: ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -101,14 +95,14 @@ _tx_thread_schedule: ; #ifdef __ARMVFP__ MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register #endif ; ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit @@ -118,21 +112,21 @@ _tx_thread_schedule: ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here: B __tx_wait_here ; Wait for the PendSV to happen ;} ; ; /* Generic context PendSV handler. */ -; +; PUBLIC PendSV_Handler PUBLIC __tx_PendSVHandler PendSV_Handler: __tx_PendSVHandler: ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler: +; +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -150,7 +144,7 @@ __tx_ts_handler: LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -181,7 +175,7 @@ _skip_vfp_save: ; STR r3, [r4] ; Clear time-slice ; -; +; ; /* Executing thread is now completely preserved!!! */ ; __tx_ts_new: @@ -225,7 +219,7 @@ __tx_ts_restore: LDMIA r12!, {LR} ; Pickup LR #ifdef __ARMVFP__ TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -233,11 +227,11 @@ _skip_vfp_restore: MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: @@ -253,16 +247,16 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ;} @@ -272,7 +266,7 @@ __tx_ts_ready: PUBLIC tx_thread_fpu_enable tx_thread_fpu_enable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -280,7 +274,7 @@ tx_thread_fpu_enable: PUBLIC tx_thread_fpu_disable tx_thread_fpu_disable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -288,4 +282,3 @@ tx_thread_fpu_disable: #endif END - diff --git a/ports/cortex_m4/iar/src/tx_thread_stack_build.s b/ports/cortex_m4/iar/src/tx_thread_stack_build.s index 61b86ab9..5f28b814 100644 --- a/ports/cortex_m4/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m4/iar/src/tx_thread_stack_build.s @@ -21,23 +21,14 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -77,11 +71,11 @@ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -141,4 +135,3 @@ _tx_thread_stack_build: BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m4/iar/src/tx_thread_system_return.s b/ports/cortex_m4/iar/src/tx_thread_system_return.s index 9820752e..72b588dd 100644 --- a/ports/cortex_m4/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m4/iar/src/tx_thread_system_return.s @@ -20,25 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -79,9 +72,9 @@ _tx_thread_system_return??rA: _tx_thread_system_return: ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -92,7 +85,6 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports/cortex_m4/iar/src/tx_timer_interrupt.s b/ports/cortex_m4/iar/src/tx_timer_interrupt.s index 0a3c3e52..5921443e 100644 --- a/ports/cortex_m4/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m4/iar/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock @@ -46,14 +35,14 @@ EXTERN _tx_thread_preempt_disable ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -87,6 +76,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -109,7 +101,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -226,13 +218,13 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -265,4 +257,3 @@ __tx_timer_nothing_expired: ; ;} END - diff --git a/ports/cortex_m4/keil/example_build/demo_threadx.c b/ports/cortex_m4/keil/example_build/demo_threadx.c index 9b94bcd4..96c4eb5a 100644 --- a/ports/cortex_m4/keil/example_build/demo_threadx.c +++ b/ports/cortex_m4/keil/example_build/demo_threadx.c @@ -43,7 +43,7 @@ UCHAR thread_5_stack[DEMO_STACK_SIZE]; /* Define the queue area. */ -UCHAR queue_0_area[DEMO_QUEUE_SIZE*sizeof(ULONG)]; +UCHAR queue_0_area[DEMO_QUEUE_SIZE*sizeof(ULONG)]; /* Define thread prototypes. */ diff --git a/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s index de11bafb..64b690c4 100644 --- a/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s @@ -90,7 +90,7 @@ __tx_vectors DCD __tx_IntHandler ; Int 1 DCD __tx_IntHandler ; Int 2 DCD __tx_IntHandler ; Int 3 - + ; ; AREA ||.text||, CODE, READONLY @@ -99,10 +99,10 @@ Reset_Handler CPSID i IF {TARGET_FPU_VFP} = {TRUE} LDR r0, =0xE000ED88 ; Pickup address of CPACR - LDR r1, [r0] ; Pickup CPACR - MOV32 r2, 0x00F00000 ; Build enable value - ORR r1, r1, r2 ; Or in enable value - STR r1, [r0] ; Setup CPACR + LDR r1, [r0] ; Pickup CPACR + MOV32 r2, 0x00F00000 ; Build enable value + ORR r1, r1, r2 ; Or in enable value + STR r1, [r0] ; Setup CPACR ENDIF LDR r0, =__main BX r0 @@ -113,7 +113,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M4/RVDS */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -147,6 +147,9 @@ Reset_Handler ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -159,24 +162,24 @@ _tx_initialize_low_level CPSID i ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| ; Build first free address - ADD r1, r1, #4 ; + ADD r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register ; LDR r1, [r0] ; Pickup the current value ; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Set system stack pointer from vector value. */ ; @@ -207,11 +210,11 @@ _tx_initialize_low_level ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; -; +; ;/* Define initial heap/stack routine for the ARM RVCT startup code. ; This routine will set the initial stack and heap locations */ ; @@ -227,19 +230,19 @@ __user_initial_stackheap ;/* Define shells for each of the unused vectors. */ ; EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler EXPORT __tx_SVCallHandler __tx_SVCallHandler - B __tx_SVCallHandler + B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {r0, lr} - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -258,7 +261,7 @@ __tx_SysTickHandler BX LR ; } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler diff --git a/ports/cortex_m4/keil/readme_threadx.txt b/ports/cortex_m4/keil/readme_threadx.txt index 188eb21d..a265efd9 100644 --- a/ports/cortex_m4/keil/readme_threadx.txt +++ b/ports/cortex_m4/keil/readme_threadx.txt @@ -198,6 +198,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M4/Keil port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using Keil tools. diff --git a/ports/cortex_m4/keil/src/tx_thread_context_restore.s b/ports/cortex_m4/keil/src/tx_thread_context_restore.s index 7c54ab4e..603a73e3 100644 --- a/ports/cortex_m4/keil/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/keil/src/tx_thread_context_restore.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_exit ENDIF @@ -43,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -76,6 +68,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m4/keil/src/tx_thread_context_save.s b/ports/cortex_m4/keil/src/tx_thread_context_save.s index 268b05a9..fbadbcb3 100644 --- a/ports/cortex_m4/keil/src/tx_thread_context_save.s +++ b/ports/cortex_m4/keil/src/tx_thread_context_save.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_enter ENDIF @@ -43,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -91,7 +86,7 @@ _tx_thread_context_save ENDIF ; ; /* Return to interrupt processing. */ -; +; BX lr ; Return to interrupt processing caller ;} ALIGN diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s index a5889c6e..910322d9 100644 --- a/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -82,4 +77,3 @@ _tx_thread_interrupt_control ; ;} END - diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s index 3cf2a68c..2504a54d 100644 --- a/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s index 20447958..8cb20abc 100644 --- a/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m4/keil/src/tx_thread_schedule.s b/ports/cortex_m4/keil/src/tx_thread_schedule.s index fd29b203..56159f35 100644 --- a/ports/cortex_m4/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m4/keil/src/tx_thread_schedule.s @@ -21,15 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice @@ -37,7 +28,7 @@ IMPORT _tx_thread_preempt_disable IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_thread_enter - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; @@ -48,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,11 +73,14 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ - EXPORT _tx_thread_schedule + EXPORT _tx_thread_schedule _tx_thread_schedule ; ; /* This function should only ever be called on Cortex-M @@ -94,7 +88,7 @@ _tx_thread_schedule ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -103,14 +97,14 @@ _tx_thread_schedule ; IF {TARGET_FPU_VFP} = {TRUE} MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register ENDIF ; ; /* Enable the interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit @@ -120,21 +114,21 @@ _tx_thread_schedule ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here B __tx_wait_here ; Wait for the PendSV to happen ;} ; ; /* Generic context switching PendSV handler. */ -; +; EXPORT __tx_PendSVHandler EXPORT PendSV_Handler -__tx_PendSVHandler +__tx_PendSVHandler PendSV_Handler ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler +; +__tx_ts_handler IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -152,7 +146,7 @@ __tx_ts_handler LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -182,10 +176,10 @@ _skip_vfp_save ; /* Clear the global time-slice. */ ; STR r3, [r4] ; Clear time-slice -; +; ; /* Executing thread is now completely preserved!!! */ ; -__tx_ts_new +__tx_ts_new ; ; /* Now we are looking for a new thread to execute! */ ; @@ -200,7 +194,7 @@ __tx_ts_new ; ; /* Increment the thread run count. */ ; -__tx_ts_restore +__tx_ts_restore LDR r7, [r1, #4] ; Pickup the current thread run count MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable LDR r5, [r1, #24] ; Pickup thread's current time-slice @@ -226,7 +220,7 @@ __tx_ts_restore LDMIA r12!, {LR} ; Pickup LR IF {TARGET_FPU_VFP} = {TRUE} TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore ENDIF @@ -234,14 +228,14 @@ _skip_vfp_restore MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; -__tx_ts_wait +__tx_ts_wait CPSID i ; Disable interrupts LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer @@ -254,16 +248,16 @@ __tx_ts_wait CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; -__tx_ts_ready +__tx_ts_ready MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread @@ -271,7 +265,7 @@ __tx_ts_ready EXPORT tx_thread_fpu_enable tx_thread_fpu_enable ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -279,7 +273,7 @@ tx_thread_fpu_enable EXPORT tx_thread_fpu_disable tx_thread_fpu_disable ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -289,10 +283,8 @@ _tx_vfp_access VMOV.F32 s0, s0 ; Simply access the VFP BX lr ; Return to caller - ENDIF ALIGN LTORG END - diff --git a/ports/cortex_m4/keil/src/tx_thread_stack_build.s b/ports/cortex_m4/keil/src/tx_thread_stack_build.s index aa2f9d4d..2b3b76f8 100644 --- a/ports/cortex_m4/keil/src/tx_thread_stack_build.s +++ b/ports/cortex_m4/keil/src/tx_thread_stack_build.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -76,11 +79,11 @@ EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M4 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -140,4 +143,3 @@ _tx_thread_stack_build BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m4/keil/src/tx_thread_system_return.s b/ports/cortex_m4/keil/src/tx_thread_system_return.s index 1e9c99a8..1918450c 100644 --- a/ports/cortex_m4/keil/src/tx_thread_system_return.s +++ b/ports/cortex_m4/keil/src/tx_thread_system_return.s @@ -20,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -37,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -77,9 +70,9 @@ EXPORT _tx_thread_system_return _tx_thread_system_return ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -90,7 +83,6 @@ _tx_thread_system_return CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports/cortex_m4/keil/src/tx_timer_interrupt.s b/ports/cortex_m4/keil/src/tx_timer_interrupt.s index 3a53a2ee..3e23d43a 100644 --- a/ports/cortex_m4/keil/src/tx_timer_interrupt.s +++ b/ports/cortex_m4/keil/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; IMPORT _tx_timer_time_slice IMPORT _tx_timer_system_clock @@ -53,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,6 +77,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -111,7 +103,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -228,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -268,4 +260,3 @@ __tx_timer_nothing_expired ALIGN LTORG END - diff --git a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s index 439b0d8b..0b7db8c2 100644 --- a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s @@ -20,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; ; IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory @@ -90,7 +80,7 @@ __tx_vectors DCD __tx_IntHandler ; Int 1 DCD __tx_IntHandler ; Int 2 DCD __tx_IntHandler ; Int 3 - + ; ; AREA ||.text||, CODE, READONLY @@ -99,10 +89,10 @@ Reset_Handler CPSID i IF {TARGET_FPU_VFP} = {TRUE} LDR r0, =0xE000ED88 ; Pickup address of CPACR - LDR r1, [r0] ; Pickup CPACR - MOV32 r2, 0x00F00000 ; Build enable value - ORR r1, r1, r2 ; Or in enable value - STR r1, [r0] ; Setup CPACR + LDR r1, [r0] ; Pickup CPACR + MOV32 r2, 0x00F00000 ; Build enable value + ORR r1, r1, r2 ; Or in enable value + STR r1, [r0] ; Setup CPACR ENDIF LDR r0, =__main BX r0 @@ -113,7 +103,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -147,6 +137,9 @@ Reset_Handler ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -159,24 +152,24 @@ _tx_initialize_low_level CPSID i ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| ; Build first free address - ADD r1, r1, #4 ; + ADD r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register ; LDR r1, [r0] ; Pickup the current value ; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Set system stack pointer from vector value. */ ; @@ -207,11 +200,11 @@ _tx_initialize_low_level ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; -; +; ;/* Define initial heap/stack routine for the ARM RVCT startup code. ; This routine will set the initial stack and heap locations */ ; @@ -227,19 +220,19 @@ __user_initial_stackheap ;/* Define shells for each of the unused vectors. */ ; EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler EXPORT __tx_SVCallHandler __tx_SVCallHandler - B __tx_SVCallHandler + B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {r0, lr} - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -247,7 +240,7 @@ __tx_IntHandler BX LR ; } - EXPORT __tx_SysTickHandler + EXPORT __tx_SysTickHandler __tx_SysTickHandler ; VOID TimerInterruptHandler (VOID) ; { @@ -258,7 +251,7 @@ __tx_SysTickHandler BX LR ; } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler @@ -269,4 +262,3 @@ __tx_DBGHandler ALIGN LTORG END - diff --git a/ports/cortex_m7/ac5/readme_threadx.txt b/ports/cortex_m7/ac5/readme_threadx.txt index 4cf8c2da..57e21b28 100644 --- a/ports/cortex_m7/ac5/readme_threadx.txt +++ b/ports/cortex_m7/ac5/readme_threadx.txt @@ -197,6 +197,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M7/AC5 port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M7 using AC5 tools. diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_restore.s b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s index b58508d3..92f481f9 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_exit ENDIF @@ -43,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -76,6 +68,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_save.s b/ports/cortex_m7/ac5/src/tx_thread_context_save.s index 5e789200..4626a8ee 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m7/ac5/src/tx_thread_context_save.s @@ -21,16 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_enter ENDIF @@ -43,13 +33,15 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -91,7 +86,7 @@ _tx_thread_context_save ENDIF ; ; /* Return to interrupt processing. */ -; +; BX lr ; Return to interrupt processing caller ;} ALIGN diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s index 17e4a59a..090cc3c1 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -82,4 +77,3 @@ _tx_thread_interrupt_control ; ;} END - diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s index 894f969a..79ca1e67 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s index 364f5414..7fc8fb4b 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s @@ -20,14 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -35,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +58,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m7/ac5/src/tx_thread_schedule.s b/ports/cortex_m7/ac5/src/tx_thread_schedule.s index 34bc8cd0..fbdd7a2b 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m7/ac5/src/tx_thread_schedule.s @@ -21,15 +21,6 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice @@ -37,7 +28,7 @@ IMPORT _tx_thread_preempt_disable IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_thread_enter - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; @@ -48,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,6 +73,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -94,7 +88,7 @@ _tx_thread_schedule ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -103,14 +97,14 @@ _tx_thread_schedule ; IF {TARGET_FPU_VFP} = {TRUE} MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register ENDIF ; ; /* Enable the interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit @@ -120,21 +114,21 @@ _tx_thread_schedule ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here B __tx_wait_here ; Wait for the PendSV to happen ;} ; ; /* Generic context switching PendSV handler. */ -; +; EXPORT __tx_PendSVHandler EXPORT PendSV_Handler -__tx_PendSVHandler +__tx_PendSVHandler PendSV_Handler ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler +; +__tx_ts_handler IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -152,7 +146,7 @@ __tx_ts_handler LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -182,10 +176,10 @@ _skip_vfp_save ; /* Clear the global time-slice. */ ; STR r3, [r4] ; Clear time-slice -; +; ; /* Executing thread is now completely preserved!!! */ ; -__tx_ts_new +__tx_ts_new ; ; /* Now we are looking for a new thread to execute! */ ; @@ -200,7 +194,7 @@ __tx_ts_new ; ; /* Increment the thread run count. */ ; -__tx_ts_restore +__tx_ts_restore LDR r7, [r1, #4] ; Pickup the current thread run count MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable LDR r5, [r1, #24] ; Pickup thread's current time-slice @@ -226,7 +220,7 @@ __tx_ts_restore LDMIA r12!, {LR} ; Pickup LR IF {TARGET_FPU_VFP} = {TRUE} TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore ENDIF @@ -234,14 +228,14 @@ _skip_vfp_restore MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; -__tx_ts_wait +__tx_ts_wait CPSID i ; Disable interrupts LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer @@ -254,16 +248,16 @@ __tx_ts_wait CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; -__tx_ts_ready +__tx_ts_ready MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread @@ -271,7 +265,7 @@ __tx_ts_ready EXPORT tx_thread_fpu_enable tx_thread_fpu_enable ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -279,7 +273,7 @@ tx_thread_fpu_enable EXPORT tx_thread_fpu_disable tx_thread_fpu_disable ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -289,10 +283,8 @@ _tx_vfp_access VMOV.F32 s0, s0 ; Simply access the VFP BX lr ; Return to caller - ENDIF ALIGN LTORG END - diff --git a/ports/cortex_m7/ac5/src/tx_thread_stack_build.s b/ports/cortex_m7/ac5/src/tx_thread_stack_build.s index d02c3df3..ce4b928d 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m7/ac5/src/tx_thread_stack_build.s @@ -21,22 +21,13 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -76,11 +70,11 @@ EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M7 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -119,7 +113,7 @@ _tx_thread_stack_build STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r3, [r2, #36] ; Store initial r0 STR r3, [r2, #40] ; Store initial r1 @@ -140,4 +134,3 @@ _tx_thread_stack_build BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m7/ac5/src/tx_thread_system_return.s b/ports/cortex_m7/ac5/src/tx_thread_system_return.s index 82daa084..12b14b7e 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m7/ac5/src/tx_thread_system_return.s @@ -20,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -37,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -77,9 +70,9 @@ EXPORT _tx_thread_system_return _tx_thread_system_return ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -90,7 +83,6 @@ _tx_thread_system_return CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports/cortex_m7/ac5/src/tx_timer_interrupt.s b/ports/cortex_m7/ac5/src/tx_timer_interrupt.s index 661e01e6..491f99b0 100644 --- a/ports/cortex_m7/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m7/ac5/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; IMPORT _tx_timer_time_slice IMPORT _tx_timer_system_clock @@ -53,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M7/AC5 */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,6 +77,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -111,7 +103,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -228,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -268,4 +260,3 @@ __tx_timer_nothing_expired ALIGN LTORG END - diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 12bed311..e3a08654 100644 --- a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -20,16 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_initialize.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ @ .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory @@ -57,7 +47,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M7/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,6 +81,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -104,17 +97,17 @@ _tx_initialize_low_level: CPSID i @ @ /* Set base of available memory to end of non-initialised RAM area. */ -@ +@ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address - ADD r1, r1, #4 @ + ADD r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer @ @ /* Setup Vector Table Offset Register. */ -@ +@ MOV r0, #0xE000E000 @ Build address of NVIC registers LDR r1, =vector_table @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address + STR r1, [r0, #0xD08] @ Set vector table address @ @ /* Set system stack pointer from vector value. */ @ @@ -128,7 +121,7 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 @ Build address of DWT register LDR r1, [r0] @ Pickup the current value ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register + STR r1, [r0] @ Enable the cycle count register @ @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ @@ -150,11 +143,10 @@ _tx_initialize_low_level: LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers @ Note: PnSV must be lowest priority, which is 0xFF - @ @ /* Return to caller. */ -@ - BX lr +@ + BX lr @} @ @@ -190,7 +182,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter @ Call the ISR enter function -#endif +#endif @ /* Do interrupt handler work here */ @ /* BL <your C Function>.... */ @@ -226,7 +218,7 @@ SysTick_Handler: @ /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler diff --git a/ports/cortex_m7/ac6/readme_threadx.txt b/ports/cortex_m7/ac6/readme_threadx.txt index 262b51e9..fd7a1025 100644 --- a/ports/cortex_m7/ac6/readme_threadx.txt +++ b/ports/cortex_m7/ac6/readme_threadx.txt @@ -144,6 +144,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M7/AC6 port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M7 using AC6 tools. diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S index e50e4d1e..529c47f8 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_system_stack_ptr @@ -48,13 +38,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M7/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function restores the interrupt context if it is processing a */ @/* nested interrupt. If not, it returns to the interrupt thread if no */ @/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -81,6 +73,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -92,4 +87,3 @@ _tx_thread_context_restore: @ /* Not needed for this port - just return! */ BX lr @} - diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_save.S b/ports/cortex_m7/ac6/src/tx_thread_context_save.S index 3f25a5eb..90ba4b8b 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_save.S @@ -21,16 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ .global _tx_thread_system_state .global _tx_thread_current_ptr @ @@ -43,13 +33,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M7/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function saves the context of an executing thread in the */ @/* beginning of interrupt processing. The function also ensures that */ @/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S index fc7d8741..5c463ac1 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S @@ -20,15 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - - .text 32 .align 4 .syntax unified @@ -37,7 +28,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M7/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,6 +59,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) @@ -87,6 +81,3 @@ _tx_thread_interrupt_control: BX lr @ Return to caller @/* } */ - - - diff --git a/ports/cortex_m7/ac6/src/tx_thread_schedule.S b/ports/cortex_m7/ac6/src/tx_thread_schedule.S index c905067b..2fc270f7 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m7/ac6/src/tx_thread_schedule.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -44,7 +35,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M7/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,6 +69,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -91,7 +85,7 @@ _tx_thread_schedule: @ from the PendSV handling routines below. */ @ @ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -@ +@ MOV r0, #0 @ Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag STR r0, [r2, #0] @ Clear preempt disable flag @@ -100,14 +94,14 @@ _tx_thread_schedule: @ #ifdef TX_ENABLE_FPU_SUPPORT MRS r0, CONTROL @ Pickup current CONTROL register - BIC r0, r0, #4 @ Clear the FPCA bit + BIC r0, r0, #4 @ Clear the FPCA bit MSR CONTROL, r0 @ Setup new CONTROL register #endif @ @ /* Enable interrupts */ @ CPSIE i -@ +@ @ /* Enter the scheduler for the first time. */ @ MOV r0, #0x10000000 @ Load PENDSVSET bit @@ -117,14 +111,14 @@ _tx_thread_schedule: ISB @ Flush pipeline @ @ /* Wait here for the PendSV to take place. */ -@ +@ __tx_wait_here: B __tx_wait_here @ Wait for the PendSV to happen @} @ -@ /* Generic context switch-out switch-in handler... Note that this handler is +@ /* Generic context switch-out switch-in handler... Note that this handler is @ common for both PendSV and SVCall. */ -@ +@ .global PendSV_Handler .global __tx_PendSVHandler .thumb_func @@ -133,8 +127,8 @@ PendSV_Handler: __tx_PendSVHandler: @ @ /* Get current thread value and new thread pointer. */ -@ -__tx_ts_handler: +@ +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @@ -152,7 +146,7 @@ __tx_ts_handler: LDR r1, [r0] @ Pickup current thread pointer @ @ /* Determine if there is a current thread to finish preserving. */ -@ +@ CBZ r1, __tx_ts_new @ If NULL, skip preservation @ @ /* Recover PSP and preserve current thread context. */ @@ -183,7 +177,6 @@ _skip_vfp_save: @ STR r3, [r4] @ Clear time-slice @ -@ @ /* Executing thread is now completely preserved!!! */ @ __tx_ts_new: @@ -227,7 +220,7 @@ __tx_ts_restore: LDMIA r12!, {LR} @ Pickup LR #ifdef TX_ENABLE_FPU_SUPPORT TST LR, #0x10 @ Determine if the VFP extended frame is present - BNE _skip_vfp_restore @ If not, skip VFP restore + BNE _skip_vfp_restore @ If not, skip VFP restore VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -235,11 +228,11 @@ _skip_vfp_restore: MSR PSP, r12 @ Setup the thread's stack pointer @ @ /* Return to thread. */ -@ +@ BX lr @ Return to thread! @ @ /* The following is the idle wait processing... in this case, no threads are ready for execution and the -@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts @ are disabled to allow use of WFI for waiting for a thread to arrive. */ @ __tx_ts_wait: @@ -255,40 +248,37 @@ __tx_ts_wait: CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ -@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are @ already in the handler! */ @ __tx_ts_ready: MOV r7, #0x08000000 @ Build clear PendSV value MOV r8, #0xE000E000 @ Build base NVIC address - STR r7, [r8, #0xD04] @ Clear any PendSV + STR r7, [r8, #0xD04] @ Clear any PendSV @ @ /* Re-enable interrupts and restore new thread. */ -@ +@ CPSIE i @ Enable interrupts B __tx_ts_restore @ Restore the thread - #ifdef TX_ENABLE_FPU_SUPPORT - .global tx_thread_fpu_enable - .thumb_func + .global tx_thread_fpu_enable + .thumb_func tx_thread_fpu_enable: @ -@ /* Automatic VPF logic is supported, this function is present only for +@ /* Automatic VPF logic is supported, this function is present only for @ backward compatibility purposes and therefore simply returns. */ @ BX LR @ Return to caller - .global tx_thread_fpu_disable - .thumb_func + .global tx_thread_fpu_disable + .thumb_func tx_thread_fpu_disable: @ -@ /* Automatic VPF logic is supported, this function is present only for +@ /* Automatic VPF logic is supported, this function is present only for @ backward compatibility purposes and therefore simply returns. */ @ BX LR @ Return to caller - #endif - diff --git a/ports/cortex_m7/ac6/src/tx_thread_stack_build.S b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S index f7a7ec21..6adc81ac 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ .text .align 4 .syntax unified @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M7/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -79,11 +73,11 @@ .thumb_func _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-M7 should look like the following after it is built: -@ -@ Stack Top: +@ +@ Stack Top: @ LR Interrupted LR (LR at time of PENDSV) @ r4 Initial value for r4 @ r5 Initial value for r5 @@ -142,5 +136,3 @@ _tx_thread_stack_build: @ control block BX lr @ Return to caller @} - - diff --git a/ports/cortex_m7/ac6/src/tx_thread_system_return.S b/ports/cortex_m7/ac6/src/tx_thread_system_return.S index f9ba40fb..6ba17aab 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m7/ac6/src/tx_thread_system_return.S @@ -19,15 +19,6 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@/* #define TX_SOURCE_CODE */ -@ -@ -@/* Include necessary system files. */ -@ -@/* #include "tx_api.h" -@ #include "tx_thread.h" -@ #include "tx_timer.h" */ .text 32 @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M7/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @@ -79,9 +73,9 @@ .global _tx_thread_system_return _tx_thread_system_return: @ -@ /* Return to real scheduler via PendSV. Note that this routine is often +@ /* Return to real scheduler via PendSV. Note that this routine is often @ replaced with in-line assembly in tx_port.h to improved performance. */ -@ +@ MOV r0, #0x10000000 @ Load PENDSVSET bit MOV r1, #0xE000E000 @ Load NVIC base STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR @@ -92,7 +86,6 @@ _tx_thread_system_return: CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture _isr_context: - BX lr @ Return to caller + BX lr @ Return to caller @/* } */ - diff --git a/ports/cortex_m7/ac6/src/tx_timer_interrupt.S b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S index e58e27d2..597fbfa5 100644 --- a/ports/cortex_m7/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S @@ -20,17 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ -@Define Assembly language external references... @ .global _tx_timer_time_slice .global _tx_timer_system_clock @@ -51,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M7/AC6 */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +75,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -110,7 +102,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3, #0] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -228,13 +220,13 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired LDR r2, [r3, #0] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing @ @ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); @ BL _tx_thread_time_slice @ Call time-slice processing LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag @@ -266,5 +258,3 @@ __tx_timer_nothing_expired: BX lr @ Return to caller @ @} - - diff --git a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S index 7b0e2100..710590f5 100644 --- a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S @@ -20,16 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_initialize.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ @ .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory @@ -59,7 +49,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M7/GNU */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,6 +86,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */ @/* GNU assembly comment, */ @/* resulting in version 6.0.1 */ +@/* 08-14-2020 William E. Lamie Modified Comment(s), clean */ +@/* up whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -109,17 +102,17 @@ _tx_initialize_low_level: CPSID i @ @ /* Set base of available memory to end of non-initialised RAM area. */ -@ +@ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer @ @ /* Setup Vector Table Offset Register. */ -@ +@ MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address + LDR r1, =_vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address @ @ /* Set system stack pointer from vector value. */ @ @@ -133,7 +126,7 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 @ Build address of DWT register LDR r1, [r0] @ Pickup the current value ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register + STR r1, [r0] @ Enable the cycle count register @ @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ @@ -155,11 +148,10 @@ _tx_initialize_low_level: LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers @ Note: PnSV must be lowest priority, which is 0xFF - @ @ /* Return to caller. */ -@ - BX lr +@ + BX lr @} @ @@ -195,7 +187,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter @ Call the ISR enter function -#endif +#endif @ /* Do interrupt handler work here */ @ /* BL <your C Function>.... */ @@ -231,7 +223,7 @@ SysTick_Handler: @ /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler diff --git a/ports/cortex_m7/gnu/readme_threadx.txt b/ports/cortex_m7/gnu/readme_threadx.txt index 287d3481..c5975f3a 100644 --- a/ports/cortex_m7/gnu/readme_threadx.txt +++ b/ports/cortex_m7/gnu/readme_threadx.txt @@ -141,6 +141,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M7/GNU port. The following files were + changed/added for port specific version 6.0.2: + + *.S Modified comments and whitespace. + 05/19/2020 Initial ThreadX 6.0 version for Cortex-M7 using GNU tools. diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S index 53a7a18f..dfddb849 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S @@ -21,26 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ - .global _tx_thread_system_state - .global _tx_thread_current_ptr - .global _tx_thread_system_stack_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_thread_schedule - .global _tx_thread_preempt_disable - .global _tx_execution_isr_exit -@ -@ .text .align 4 .syntax unified @@ -49,13 +29,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M7/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function restores the interrupt context if it is processing a */ @/* nested interrupt. If not, it returns to the interrupt thread if no */ @/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -82,6 +64,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -93,4 +78,3 @@ _tx_thread_context_restore: @ /* Not needed for this port - just return! */ BX lr @} - diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_save.S b/ports/cortex_m7/gnu/src/tx_thread_context_save.S index 1c7eff9e..201cccdd 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_save.S @@ -21,21 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ - .global _tx_thread_system_state - .global _tx_thread_current_ptr - .global _tx_execution_isr_enter -@ -@ .text .align 4 .syntax unified @@ -44,13 +29,15 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M7/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ @/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ @/* This function saves the context of an executing thread in the */ @/* beginning of interrupt processing. The function also ensures that */ @/* the system stack is used upon return to the calling ISR. */ @@ -76,6 +63,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S index f4e3f61c..c43b8cc9 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S @@ -20,15 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ -@/* #define TX_SOURCE_CODE */ - - -@/* Include necessary system files. */ - -@/* #include "tx_api.h" - #include "tx_thread.h" */ - - .text 32 .align 4 .syntax unified @@ -37,7 +28,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M7/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,6 +59,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) @@ -87,6 +81,3 @@ _tx_thread_interrupt_control: BX lr @ Return to caller @/* } */ - - - diff --git a/ports/cortex_m7/gnu/src/tx_thread_schedule.S b/ports/cortex_m7/gnu/src/tx_thread_schedule.S index 99af8be2..0f0c18b7 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m7/gnu/src/tx_thread_schedule.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -46,7 +37,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M7/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -80,6 +71,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -93,7 +87,7 @@ _tx_thread_schedule: @ from the PendSV handling routines below. */ @ @ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -@ +@ MOV r0, #0 @ Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag STR r0, [r2, #0] @ Clear preempt disable flag @@ -102,14 +96,14 @@ _tx_thread_schedule: @ #ifdef TX_ENABLE_FPU_SUPPORT MRS r0, CONTROL @ Pickup current CONTROL register - BIC r0, r0, #4 @ Clear the FPCA bit + BIC r0, r0, #4 @ Clear the FPCA bit MSR CONTROL, r0 @ Setup new CONTROL register #endif @ @ /* Enable interrupts */ @ CPSIE i -@ +@ @ /* Enter the scheduler for the first time. */ @ MOV r0, #0x10000000 @ Load PENDSVSET bit @@ -119,14 +113,14 @@ _tx_thread_schedule: ISB @ Flush pipeline @ @ /* Wait here for the PendSV to take place. */ -@ +@ __tx_wait_here: B __tx_wait_here @ Wait for the PendSV to happen @} @ -@ /* Generic context switch-out switch-in handler... Note that this handler is +@ /* Generic context switch-out switch-in handler... Note that this handler is @ common for both PendSV and SVCall. */ -@ +@ .global PendSV_Handler .global __tx_PendSVHandler .thumb_func @@ -135,8 +129,8 @@ PendSV_Handler: __tx_PendSVHandler: @ @ /* Get current thread value and new thread pointer. */ -@ -__tx_ts_handler: +@ +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @@ -154,7 +148,7 @@ __tx_ts_handler: LDR r1, [r0] @ Pickup current thread pointer @ @ /* Determine if there is a current thread to finish preserving. */ -@ +@ CBZ r1, __tx_ts_new @ If NULL, skip preservation @ @ /* Recover PSP and preserve current thread context. */ @@ -185,7 +179,6 @@ _skip_vfp_save: @ STR r3, [r4] @ Clear time-slice @ -@ @ /* Executing thread is now completely preserved!!! */ @ __tx_ts_new: @@ -229,7 +222,7 @@ __tx_ts_restore: LDMIA r12!, {LR} @ Pickup LR #ifdef TX_ENABLE_FPU_SUPPORT TST LR, #0x10 @ Determine if the VFP extended frame is present - BNE _skip_vfp_restore @ If not, skip VFP restore + BNE _skip_vfp_restore @ If not, skip VFP restore VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -237,11 +230,11 @@ _skip_vfp_restore: MSR PSP, r12 @ Setup the thread's stack pointer @ @ /* Return to thread. */ -@ +@ BX lr @ Return to thread! @ @ /* The following is the idle wait processing... in this case, no threads are ready for execution and the -@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts @ are disabled to allow use of WFI for waiting for a thread to arrive. */ @ __tx_ts_wait: @@ -257,40 +250,37 @@ __tx_ts_wait: CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ -@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are @ already in the handler! */ @ __tx_ts_ready: MOV r7, #0x08000000 @ Build clear PendSV value MOV r8, #0xE000E000 @ Build base NVIC address - STR r7, [r8, #0xD04] @ Clear any PendSV + STR r7, [r8, #0xD04] @ Clear any PendSV @ @ /* Re-enable interrupts and restore new thread. */ -@ +@ CPSIE i @ Enable interrupts B __tx_ts_restore @ Restore the thread - #ifdef TX_ENABLE_FPU_SUPPORT - .global tx_thread_fpu_enable - .thumb_func + .global tx_thread_fpu_enable + .thumb_func tx_thread_fpu_enable: @ -@ /* Automatic VPF logic is supported, this function is present only for +@ /* Automatic VPF logic is supported, this function is present only for @ backward compatibility purposes and therefore simply returns. */ @ BX LR @ Return to caller - .global tx_thread_fpu_disable - .thumb_func + .global tx_thread_fpu_disable + .thumb_func tx_thread_fpu_disable: @ -@ /* Automatic VPF logic is supported, this function is present only for +@ /* Automatic VPF logic is supported, this function is present only for @ backward compatibility purposes and therefore simply returns. */ @ BX LR @ Return to caller - #endif - diff --git a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S index 8c4a6b7d..c8723d1d 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S @@ -21,15 +21,6 @@ @/**************************************************************************/ @ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ .text .align 4 .syntax unified @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M7/GNU */ -@/* 6.0.1 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -76,6 +67,9 @@ @/* needed. Removed references */ @/* to stack frame, resulting */ @/* in version 6.0.1 */ +@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -84,11 +78,11 @@ .thumb_func _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-M7 should look like the following after it is built: -@ -@ Stack Top: +@ +@ Stack Top: @ LR Interrupted LR (LR at time of PENDSV) @ r4 Initial value for r4 @ r5 Initial value for r5 @@ -147,5 +141,3 @@ _tx_thread_stack_build: @ control block BX lr @ Return to caller @} - - diff --git a/ports/cortex_m7/gnu/src/tx_thread_system_return.S b/ports/cortex_m7/gnu/src/tx_thread_system_return.S index 3c609279..9ed23b63 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m7/gnu/src/tx_thread_system_return.S @@ -19,15 +19,6 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@/* #define TX_SOURCE_CODE */ -@ -@ -@/* Include necessary system files. */ -@ -@/* #include "tx_api.h" -@ #include "tx_thread.h" -@ #include "tx_timer.h" */ .text 32 @@ -38,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M7/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +62,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @@ -79,9 +73,9 @@ .global _tx_thread_system_return _tx_thread_system_return: @ -@ /* Return to real scheduler via PendSV. Note that this routine is often +@ /* Return to real scheduler via PendSV. Note that this routine is often @ replaced with in-line assembly in tx_port.h to improved performance. */ -@ +@ MOV r0, #0x10000000 @ Load PENDSVSET bit MOV r1, #0xE000E000 @ Load NVIC base STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR @@ -92,7 +86,6 @@ _tx_thread_system_return: CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture _isr_context: - BX lr @ Return to caller + BX lr @ Return to caller @/* } */ - diff --git a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S index b58b60b7..7bf85439 100755 --- a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S @@ -20,17 +20,6 @@ @/**************************************************************************/ @/**************************************************************************/ @ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ -@Define Assembly language external references... @ .global _tx_timer_time_slice .global _tx_timer_system_clock @@ -51,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M7/GNU */ -@/* 6.0 */ +@/* 6.0.2 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +75,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +@/* whitespace, resulting */ +@/* in version 6.0.2 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -110,7 +102,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3, #0] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -228,13 +220,13 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired LDR r2, [r3, #0] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing @ @ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); @ BL _tx_thread_time_slice @ Call time-slice processing LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag @@ -266,5 +258,3 @@ __tx_timer_nothing_expired: BX lr @ Return to caller @ @} - - diff --git a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s index bcf8d4b1..bb349b95 100644 --- a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s @@ -20,42 +20,32 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_initialize_unused_memory - EXTERN _tx_timer_interrupt - EXTERN __vector_table - EXTERN _tx_execution_isr_enter - EXTERN _tx_execution_isr_exit + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __vector_table + EXTERN _tx_execution_isr_enter + EXTERN _tx_execution_isr_exit ; ; SYSTEM_CLOCK EQU 25000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -89,20 +79,23 @@ __tx_free_memory_start ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ PUBLIC _tx_initialize_low_level _tx_initialize_low_level: -; +; ; /* Ensure that interrupts are disabled. */ ; CPSID i ; Disable interrupts ; ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer STR r0, [r2, #0] ; Save first free memory address @@ -112,13 +105,13 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 ; Build address of DWT register LDR r1, [r0] ; Pickup the current value ORR r1, r1, #1 ; Set the CYCCNTENA bit - STR r1, [r0] ; Enable the cycle count register + STR r1, [r0] ; Enable the cycle count register ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Set system stack pointer from vector value. */ ; @@ -149,8 +142,8 @@ _tx_initialize_low_level: ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; ; @@ -174,4 +167,3 @@ SysTick_Handler: BX LR ; } END - diff --git a/ports/cortex_m7/iar/readme_threadx.txt b/ports/cortex_m7/iar/readme_threadx.txt index 42c8d901..41ff1b5a 100644 --- a/ports/cortex_m7/iar/readme_threadx.txt +++ b/ports/cortex_m7/iar/readme_threadx.txt @@ -206,6 +206,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +08-14-2020 ThreadX update of Cortex-M7/IAR port. The following files were + changed/added for port specific version 6.0.2: + + *.s Modified comments and whitespace. + 06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M7 using IAR's ARM tools. diff --git a/ports/cortex_m7/iar/src/tx_thread_context_restore.s b/ports/cortex_m7/iar/src/tx_thread_context_restore.s index f671f2d4..fc27deeb 100644 --- a/ports/cortex_m7/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m7/iar/src/tx_thread_context_restore.s @@ -21,40 +21,32 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_state - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_schedule - EXTERN _tx_thread_preempt_disable - EXTERN _tx_execution_isr_exit -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -81,6 +73,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -101,5 +96,4 @@ _tx_thread_context_restore: BX lr ; ;} - END - + END diff --git a/ports/cortex_m7/iar/src/tx_thread_context_save.s b/ports/cortex_m7/iar/src/tx_thread_context_save.s index 1febcc18..d1a7f71d 100644 --- a/ports/cortex_m7/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m7/iar/src/tx_thread_context_save.s @@ -21,35 +21,27 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_state - EXTERN _tx_thread_current_ptr - EXTERN _tx_execution_isr_enter -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -75,6 +67,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -84,7 +79,7 @@ _tx_thread_context_save: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the ISR enter function to indicate an ISR is starting. */ -; +; PUSH {r0, lr} ; Save return address BL _tx_execution_isr_enter ; Call the ISR enter function POP {r0, lr} ; Recover return address diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s index 2e95e0f7..207ffed8 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -82,5 +77,4 @@ _tx_thread_interrupt_control: BX lr ; ;} - END - + END diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s index e435b0b8..d706ed79 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s index cfdb140d..addd8816 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +59,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m7/iar/src/tx_thread_schedule.s b/ports/cortex_m7/iar/src/tx_thread_schedule.s index 4e97613c..0e26586d 100644 --- a/ports/cortex_m7/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m7/iar/src/tx_thread_schedule.s @@ -21,32 +21,23 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_execution_thread_enter - EXTERN _tx_execution_thread_exit - EXTERN _tx_thread_preempt_disable -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,6 +71,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -92,7 +86,7 @@ _tx_thread_schedule: ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -101,14 +95,14 @@ _tx_thread_schedule: ; #ifdef __ARMVFP__ MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register #endif ; ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit @@ -118,21 +112,21 @@ _tx_thread_schedule: ISB ; Flush pipeline ; ; /* Wait here for the PendSV to take place. */ -; +; __tx_wait_here: B __tx_wait_here ; Wait for the PendSV to happen ;} ; ; /* Generic context PendSV handler. */ -; +; PUBLIC PendSV_Handler PUBLIC __tx_PendSVHandler PendSV_Handler: __tx_PendSVHandler: ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler: +; +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -150,7 +144,7 @@ __tx_ts_handler: LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -181,7 +175,7 @@ _skip_vfp_save: ; STR r3, [r4] ; Clear time-slice ; -; +; ; /* Executing thread is now completely preserved!!! */ ; __tx_ts_new: @@ -225,7 +219,7 @@ __tx_ts_restore: LDMIA r12!, {LR} ; Pickup LR #ifdef __ARMVFP__ TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -233,11 +227,11 @@ _skip_vfp_restore: MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: @@ -253,16 +247,16 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ;} @@ -272,7 +266,7 @@ __tx_ts_ready: PUBLIC tx_thread_fpu_enable tx_thread_fpu_enable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -280,7 +274,7 @@ tx_thread_fpu_enable: PUBLIC tx_thread_fpu_disable tx_thread_fpu_disable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -288,4 +282,3 @@ tx_thread_fpu_disable: #endif END - diff --git a/ports/cortex_m7/iar/src/tx_thread_stack_build.s b/ports/cortex_m7/iar/src/tx_thread_stack_build.s index 36518e5e..9a94461b 100644 --- a/ports/cortex_m7/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m7/iar/src/tx_thread_stack_build.s @@ -21,23 +21,14 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -77,11 +71,11 @@ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M7 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -120,7 +114,7 @@ _tx_thread_stack_build: STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r3, [r2, #36] ; Store initial r0 STR r3, [r2, #40] ; Store initial r1 @@ -141,4 +135,3 @@ _tx_thread_stack_build: BX lr ; Return to caller ;} END - diff --git a/ports/cortex_m7/iar/src/tx_thread_system_return.s b/ports/cortex_m7/iar/src/tx_thread_system_return.s index 126a9c78..52322551 100644 --- a/ports/cortex_m7/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m7/iar/src/tx_thread_system_return.s @@ -20,25 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +61,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -79,9 +72,9 @@ _tx_thread_system_return??rA: _tx_thread_system_return: ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -92,6 +85,6 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} - END + END diff --git a/ports/cortex_m7/iar/src/tx_timer_interrupt.s b/ports/cortex_m7/iar/src/tx_timer_interrupt.s index c900f267..33f13a42 100644 --- a/ports/cortex_m7/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m7/iar/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock @@ -46,14 +35,14 @@ EXTERN _tx_thread_preempt_disable ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.0.2 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -87,6 +76,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ +;/* whitespace, resulting */ +;/* in version 6.0.2 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -109,7 +101,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -226,13 +218,13 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -265,4 +257,3 @@ __tx_timer_nothing_expired: ; ;} END - |