diff options
| author | Alex Kiselev <[email protected]> | 2023-06-21 09:08:45 +0200 |
|---|---|---|
| committer | Alex Kiselev <[email protected]> | 2023-06-21 09:08:45 +0200 |
| commit | 5d619e5c4ba36fdf4fe5bc6ffb34f18dc7076ac5 (patch) | |
| tree | 2098a0844e78cf60e29f3eb678c01491c9ea3401 | |
| parent | 1b2995cea8aecd46c8bc012f2605dea6142bec01 (diff) | |
SysTick initialization problem fixed in tx_initialize_low_level.s
Problem with first system tick was detected, it needs much more time for the first tick as it's defined. The reason for this behavior is incorrect initialization of the SysTick timer in the port file for the Cortex-M0. It doesn't reset the SysTick Current Value Register despite the fact that its value is not initialized at startup (see https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/system-timer--systick). So if we have 0xFFFFFF (this register has 24-bit), it means we will get about 256*256*256 / 48000000 for the tact frequency of 48MHz to reach the zero, that makes 350ms delay at startup.
4 files changed, 12 insertions, 0 deletions
diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s index 4a4f20db..0c19cc2f 100644 --- a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -176,6 +176,9 @@ _tx_initialize_low_level ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOVS r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S index aaf3ece2..fd08b282 100644 --- a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S @@ -134,6 +134,9 @@ _tx_initialize_low_level: @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ LDR r0, =0xE000E000 @ Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value LDR r1, =0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s index 3de316e5..09742ecc 100644 --- a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s @@ -125,6 +125,9 @@ _tx_initialize_low_level: ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOVS r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s index 4a4f20db..0c19cc2f 100644 --- a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s @@ -176,6 +176,9 @@ _tx_initialize_low_level ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOVS r1, #0x7 ; Build SysTick Control Enable Value |