diff options
| author | TiejunZhou <[email protected]> | 2023-06-26 09:21:06 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-06-26 09:21:06 +0800 |
| commit | 8ff9910ddc089e7af91e4089b26f225aba5d7eb7 (patch) | |
| tree | 5106838e06f53fefd2bc79c0de07e1c304d0673f | |
| parent | 08380caa7792f917d2e24cfae22df8796487ac5b (diff) | |
Added memory barrier before thread scheduling for ARMv8-A ThreadX SMP. (#280)
50 files changed, 150 insertions, 50 deletions
diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_restore.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_restore.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_system_return.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_system_return.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_restore.S index 8ab57b5e..19f80685 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_restore.S @@ -70,7 +70,8 @@ /* FIFO queueing, */ /* resulting in version 6.1.11 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -294,6 +295,7 @@ __tx_thread_dont_save_ts: /* Set bit indicating this thread is ready for execution. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x2, #1 // Build ready flag STR w2, [x0, #260] // Set thread's ready flag DMB ISH // Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_system_return.S index 0142f0e6..9628b32c 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_system_return.S @@ -67,7 +67,8 @@ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ /* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ +/* #include tx_user.h, added */ +/* memory barrier, */ /* resulting in version 6.x */ /* */ /**************************************************************************/ @@ -173,6 +174,7 @@ __tx_thread_dont_save_ts: /* Set ready bit in thread control block. */ + DMB ISH // Ensure that accesses to shared resource have completed MOV x3, #1 // Build ready value STR w3, [x6, #260] // Make the thread ready DMB ISH // |