removed dead code in riscv64/gnu port

Signed-off-by: Akif Ejaz <[email protected]>

2 files changed, 11 insertions, 78 deletions

diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h
index d2385358..ed985072 100644
--- a/ports/risc-v64/gnu/inc/tx_port.h
+++ b/ports/risc-v64/gnu/inc/tx_port.h
@@ -53,6 +53,8 @@
 #ifndef TX_PORT_H
 #define TX_PORT_H
 
+#ifndef __ASSEMBLER__
+
 /* Include for memset.  */
 #include <string.h>
 
@@ -68,10 +70,14 @@
 #include "tx_user.h"
 #endif /* TX_INCLUDE_USER_DEFINE_FILE */
 
+#endif /* __ASSEMBLER__ */
+
 
 /* Define ThreadX basic types for this port.  */
 
 #define VOID                                    void
+
+#ifndef __ASSEMBLER__
 typedef char                                    CHAR;
 typedef unsigned char                           UCHAR;
 typedef int                                     INT;
@@ -82,6 +88,7 @@ typedef unsigned long long                      ULONG64;
 typedef short                                   SHORT;
 typedef unsigned short                          USHORT;
 #define ULONG64_DEFINED
+#endif /* __ASSEMBLER__ */
 
 
 
@@ -230,7 +237,9 @@ typedef unsigned short                          USHORT;
 
 /* Expose helper used to perform an atomic read/modify/write of mstatus.
    The helper composes and returns the posture per ThreadX contract. */
+#ifndef __ASSEMBLER__
 UINT                                            _tx_thread_interrupt_control(UINT new_posture);
+#endif
 
 #ifdef TX_DISABLE_INLINE
 
@@ -270,11 +279,13 @@ UINT                                            _tx_thread_interrupt_control(UIN
 
 /* Define the version ID of ThreadX.  This may be utilized by the application.  */
 
+#ifndef __ASSEMBLER__
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
                                     "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V64/GNU Version 6.4.2 *";
 #else
 extern  CHAR                    _tx_version_id[];
 #endif /* TX_THREAD_INIT */
+#endif /* __ASSEMBLER__ */
 
 #endif /* TX_PORT_H */
diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S
index 641c7793..b9aa13c9 100644
--- a/ports/risc-v64/gnu/src/tx_thread_context_save.S
+++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S
@@ -260,84 +260,6 @@ _tx_thread_not_nested_save:
     ld      sp, 0(t0)                                   // Switch to system stack
     ret                                                 // Return to calling ISR
 
-    sd      x17, 20*8(sp)                               // Store a7
-    sd      x28, 16*8(sp)                               // Store t3
-    sd      x29, 15*8(sp)                               // Store t4
-    sd      x30, 14*8(sp)                               // Store t5
-    sd      x31, 13*8(sp)                               // Store t6
-
-    csrr    t0, mepc                                    // Load exception program counter
-    sd      t0, 30*8(sp)                                // Save it on the stack
-
-    /* Save floating point scratch registers.  */
-#if defined(__riscv_float_abi_single)
-    fsw     f0, 31*8(sp)                                // Store ft0
-    fsw     f1, 32*8(sp)                                // Store ft1
-    fsw     f2, 33*8(sp)                                // Store ft2
-    fsw     f3, 34*8(sp)                                // Store ft3
-    fsw     f4, 35*8(sp)                                // Store ft4
-    fsw     f5, 36*8(sp)                                // Store ft5
-    fsw     f6, 37*8(sp)                                // Store ft6
-    fsw     f7, 38*8(sp)                                // Store ft7
-    fsw     f10,41*8(sp)                                // Store fa0
-    fsw     f11,42*8(sp)                                // Store fa1
-    fsw     f12,43*8(sp)                                // Store fa2
-    fsw     f13,44*8(sp)                                // Store fa3
-    fsw     f14,45*8(sp)                                // Store fa4
-    fsw     f15,46*8(sp)                                // Store fa5
-    fsw     f16,47*8(sp)                                // Store fa6
-    fsw     f17,48*8(sp)                                // Store fa7
-    fsw     f28,59*8(sp)                                // Store ft8
-    fsw     f29,60*8(sp)                                // Store ft9
-    fsw     f30,61*8(sp)                                // Store ft10
-    fsw     f31,62*8(sp)                                // Store ft11
-    csrr    t0, fcsr
-    sd      t0, 63*8(sp)                                // Store fcsr
-#elif defined(__riscv_float_abi_double)
-    fsd     f0, 31*8(sp)                                // Store ft0
-    fsd     f1, 32*8(sp)                                // Store ft1
-    fsd     f2, 33*8(sp)                                // Store ft2
-    fsd     f3, 34*8(sp)                                // Store ft3
-    fsd     f4, 35*8(sp)                                // Store ft4
-    fsd     f5, 36*8(sp)                                // Store ft5
-    fsd     f6, 37*8(sp)                                // Store ft6
-    fsd     f7, 38*8(sp)                                // Store ft7
-    fsd     f10,41*8(sp)                                // Store fa0
-    fsd     f11,42*8(sp)                                // Store fa1
-    fsd     f12,43*8(sp)                                // Store fa2
-    fsd     f13,44*8(sp)                                // Store fa3
-    fsd     f14,45*8(sp)                                // Store fa4
-    fsd     f15,46*8(sp)                                // Store fa5
-    fsd     f16,47*8(sp)                                // Store fa6
-    fsd     f17,48*8(sp)                                // Store fa7
-    fsd     f28,59*8(sp)                                // Store ft8
-    fsd     f29,60*8(sp)                                // Store ft9
-    fsd     f30,61*8(sp)                                // Store ft10
-    fsd     f31,62*8(sp)                                // Store ft11
-    csrr    t0, fcsr
-    sd      t0, 63*8(sp)                                // Store fcsr
-#endif
-
-    /* Save the current stack pointer in the thread's control block.  */
-    /* _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;  */
-
-    /* Switch to the system stack.  */
-    /* sp =  _tx_thread_system_stack_ptr;  */
-
-    la      x5, _tx_thread_current_ptr                  // Pickup current thread pointer address
-    ld      t1, 0(x5)                                   // Pickup current thread pointer
-    sd      sp, 16(t1)                                  // Save stack pointer
-
-#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
-    /* _tx_execution_isr_enter is called with thread stack pointer */
-    call    _tx_execution_isr_enter                     // Call the ISR execution enter function
-#endif
-
-
-    la      x5, _tx_thread_system_stack_ptr             // Pickup system stack pointer address
-    ld      sp, 0(x5)                                   // Switch to system stack
-    ret                                                 // Return to calling ISR
-
     /* }
     else
     {  */