diff options
| author | Akif Ejaz <[email protected]> | 2026-03-01 15:13:28 +0500 |
|---|---|---|
| committer | Akif Ejaz <[email protected]> | 2026-03-01 15:13:28 +0500 |
| commit | cd101d9ab4d4581d978a4bf8befe9af8de173335 (patch) | |
| tree | 3413939761cbcffa5812f85b867bffade6afc3d1 | |
| parent | ff287cce979e23aa4866edb6ab17e69e3de30a9c (diff) | |
update comments
Signed-off-by: Akif Ejaz <[email protected]>
| -rw-r--r-- | ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S index f4f4a750..d7108c27 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S +++ b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S @@ -66,9 +66,9 @@ .extern _tx_thread_context_restore trap_entry: #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, -260 // Allocate space for all registers - with floating point enabled + addi sp, sp, -260 // Allocate space for all registers - with floating point enabled (65*4) #else - addi sp, sp, -128 // Allocate space for all registers - without floating point enabled + addi sp, sp, -128 // Allocate space for all registers - without floating point enabled (32*4) #endif sw x1, 112(sp) // Store RA (28*4 = 112, because call will override ra [ra is a callee register in riscv]) |