diff options
| author | Yajun Xia <[email protected]> | 2023-12-28 09:37:39 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-12-28 09:37:39 +0800 |
| commit | e73843f6d4ec7d17cb91c6391405f94e7672f4e8 (patch) | |
| tree | 9890bddf9eeac411fc3aa2375e34372cfd39ad5f | |
| parent | dbfad5d126cbc640507b1e5ec88d8e62902f0b49 (diff) | |
Added thumb mode support for threadX GNU ports on armv7a platforms. (#333)
* Added thumb mode support for threadX GNU ports on armv7a platforms.
https://msazure.visualstudio.com/One/_workitems/edit/26105175/
* move the swi interrupt to tx_initialize_low_level.S.
* update the test log.
208 files changed, 4938 insertions, 4541 deletions
diff --git a/ports/cortex_a12/ac6/src/tx_thread_context_restore.S b/ports/cortex_a12/ac6/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a12/ac6/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a12/ac6/src/tx_thread_context_save.S b/ports/cortex_a12/ac6/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a12/ac6/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a12/ac6/src/tx_thread_schedule.S b/ports/cortex_a12/ac6/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a12/ac6/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a12/ac6/src/tx_thread_stack_build.S b/ports/cortex_a12/ac6/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a12/ac6/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a12/ac6/src/tx_thread_system_return.S b/ports/cortex_a12/ac6/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a12/ac6/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a12/ac6/src/tx_timer_interrupt.S b/ports/cortex_a12/ac6/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a12/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a12/ac6/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a12/gnu/example_build/crt0.S b/ports/cortex_a12/gnu/example_build/crt0.S index d25196ef..abc817d5 100644 --- a/ports/cortex_a12/gnu/example_build/crt0.S +++ b/ports/cortex_a12/gnu/example_build/crt0.S @@ -1,15 +1,30 @@ + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + /* .text is used instead of .section .text so it works with arm-aout too. */ .text - .code 32 .align 0 +#if defined(THUMB_MODE) + .thumb_func +#endif .global _mainCRTStartup +_mainCRTStartup: +#if defined(THUMB_MODE) + .thumb_func +#endif .global _start +_start: +#if defined(THUMB_MODE) + .thumb_func +#endif .global start start: -_start: -_mainCRTStartup: /* Start by setting up a stack */ /* Set up the stack pointer to a fixed value */ @@ -69,24 +84,12 @@ _mainCRTStartup: .word _fini #endif */ /* Return ... */ -#ifdef __APCS_26__ - movs pc, lr -#else -#ifdef __THUMB_INTERWORK bx lr -#else - mov pc, lr -#endif -#endif .global _fini .type _fini,function _fini: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif /* Workspace for Angel calls. */ .data diff --git a/ports/cortex_a12/gnu/src/tx_thread_context_restore.S b/ports/cortex_a12/gnu/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a12/gnu/src/tx_thread_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_schedule.S b/ports/cortex_a12/gnu/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a12/gnu/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_stack_build.S b/ports/cortex_a12/gnu/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a12/gnu/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_system_return.S b/ports/cortex_a12/gnu/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a12/gnu/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a12/gnu/src/tx_timer_interrupt.S b/ports/cortex_a12/gnu/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a12/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a12/gnu/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_restore.S b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a15/ac6/src/tx_thread_schedule.S b/ports/cortex_a15/ac6/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a15/ac6/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a15/ac6/src/tx_thread_stack_build.S b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a15/ac6/src/tx_thread_system_return.S b/ports/cortex_a15/ac6/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a15/ac6/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a15/ac6/src/tx_timer_interrupt.S b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a15/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a15/gnu/example_build/crt0.S b/ports/cortex_a15/gnu/example_build/crt0.S index d25196ef..abc817d5 100644 --- a/ports/cortex_a15/gnu/example_build/crt0.S +++ b/ports/cortex_a15/gnu/example_build/crt0.S @@ -1,15 +1,30 @@ + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + /* .text is used instead of .section .text so it works with arm-aout too. */ .text - .code 32 .align 0 +#if defined(THUMB_MODE) + .thumb_func +#endif .global _mainCRTStartup +_mainCRTStartup: +#if defined(THUMB_MODE) + .thumb_func +#endif .global _start +_start: +#if defined(THUMB_MODE) + .thumb_func +#endif .global start start: -_start: -_mainCRTStartup: /* Start by setting up a stack */ /* Set up the stack pointer to a fixed value */ @@ -69,24 +84,12 @@ _mainCRTStartup: .word _fini #endif */ /* Return ... */ -#ifdef __APCS_26__ - movs pc, lr -#else -#ifdef __THUMB_INTERWORK bx lr -#else - mov pc, lr -#endif -#endif .global _fini .type _fini,function _fini: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif /* Workspace for Angel calls. */ .data diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a15/gnu/src/tx_thread_schedule.S b/ports/cortex_a15/gnu/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a15/gnu/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a15/gnu/src/tx_thread_system_return.S b/ports/cortex_a15/gnu/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a15/gnu/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_context_restore.S b/ports/cortex_a17/ac6/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a17/ac6/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a17/ac6/src/tx_thread_context_save.S b/ports/cortex_a17/ac6/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a17/ac6/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_schedule.S b/ports/cortex_a17/ac6/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a17/ac6/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_stack_build.S b/ports/cortex_a17/ac6/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a17/ac6/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_system_return.S b/ports/cortex_a17/ac6/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a17/ac6/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a17/ac6/src/tx_timer_interrupt.S b/ports/cortex_a17/ac6/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a17/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a17/ac6/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a17/gnu/example_build/crt0.S b/ports/cortex_a17/gnu/example_build/crt0.S index d25196ef..abc817d5 100644 --- a/ports/cortex_a17/gnu/example_build/crt0.S +++ b/ports/cortex_a17/gnu/example_build/crt0.S @@ -1,15 +1,30 @@ + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + /* .text is used instead of .section .text so it works with arm-aout too. */ .text - .code 32 .align 0 +#if defined(THUMB_MODE) + .thumb_func +#endif .global _mainCRTStartup +_mainCRTStartup: +#if defined(THUMB_MODE) + .thumb_func +#endif .global _start +_start: +#if defined(THUMB_MODE) + .thumb_func +#endif .global start start: -_start: -_mainCRTStartup: /* Start by setting up a stack */ /* Set up the stack pointer to a fixed value */ @@ -69,24 +84,12 @@ _mainCRTStartup: .word _fini #endif */ /* Return ... */ -#ifdef __APCS_26__ - movs pc, lr -#else -#ifdef __THUMB_INTERWORK bx lr -#else - mov pc, lr -#endif -#endif .global _fini .type _fini,function _fini: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif /* Workspace for Angel calls. */ .data diff --git a/ports/cortex_a17/gnu/src/tx_thread_context_restore.S b/ports/cortex_a17/gnu/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a17/gnu/src/tx_thread_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_schedule.S b/ports/cortex_a17/gnu/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a17/gnu/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_stack_build.S b/ports/cortex_a17/gnu/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a17/gnu/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_system_return.S b/ports/cortex_a17/gnu/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a17/gnu/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a17/gnu/src/tx_timer_interrupt.S b/ports/cortex_a17/gnu/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a17/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a17/gnu/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_context_restore.S b/ports/cortex_a5/ac6/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a5/ac6/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a5/ac6/src/tx_thread_context_save.S b/ports/cortex_a5/ac6/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a5/ac6/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a5/ac6/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a5/ac6/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a5/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a5/ac6/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a5/ac6/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a5/ac6/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a5/ac6/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_schedule.S b/ports/cortex_a5/ac6/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a5/ac6/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_stack_build.S b/ports/cortex_a5/ac6/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a5/ac6/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_system_return.S b/ports/cortex_a5/ac6/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a5/ac6/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a5/ac6/src/tx_timer_interrupt.S b/ports/cortex_a5/ac6/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a5/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a5/ac6/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a5/gnu/example_build/crt0.S b/ports/cortex_a5/gnu/example_build/crt0.S index d25196ef..abc817d5 100644 --- a/ports/cortex_a5/gnu/example_build/crt0.S +++ b/ports/cortex_a5/gnu/example_build/crt0.S @@ -1,15 +1,30 @@ + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + /* .text is used instead of .section .text so it works with arm-aout too. */ .text - .code 32 .align 0 +#if defined(THUMB_MODE) + .thumb_func +#endif .global _mainCRTStartup +_mainCRTStartup: +#if defined(THUMB_MODE) + .thumb_func +#endif .global _start +_start: +#if defined(THUMB_MODE) + .thumb_func +#endif .global start start: -_start: -_mainCRTStartup: /* Start by setting up a stack */ /* Set up the stack pointer to a fixed value */ @@ -69,24 +84,12 @@ _mainCRTStartup: .word _fini #endif */ /* Return ... */ -#ifdef __APCS_26__ - movs pc, lr -#else -#ifdef __THUMB_INTERWORK bx lr -#else - mov pc, lr -#endif -#endif .global _fini .type _fini,function _fini: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif /* Workspace for Angel calls. */ .data diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_restore.S b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a5/gnu/src/tx_thread_schedule.S b/ports/cortex_a5/gnu/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a5/gnu/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a5/gnu/src/tx_thread_stack_build.S b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a5/gnu/src/tx_thread_system_return.S b/ports/cortex_a5/gnu/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a5/gnu/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a5/gnu/src/tx_timer_interrupt.S b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a5/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a7/ac6/src/tx_thread_context_restore.S b/ports/cortex_a7/ac6/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a7/ac6/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a7/ac6/src/tx_thread_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a7/ac6/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a7/ac6/src/tx_thread_schedule.S b/ports/cortex_a7/ac6/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a7/ac6/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a7/ac6/src/tx_thread_stack_build.S b/ports/cortex_a7/ac6/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a7/ac6/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a7/ac6/src/tx_thread_system_return.S b/ports/cortex_a7/ac6/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a7/ac6/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a7/ac6/src/tx_timer_interrupt.S b/ports/cortex_a7/ac6/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a7/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a7/ac6/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a7/gnu/example_build/crt0.S b/ports/cortex_a7/gnu/example_build/crt0.S index d25196ef..abc817d5 100644 --- a/ports/cortex_a7/gnu/example_build/crt0.S +++ b/ports/cortex_a7/gnu/example_build/crt0.S @@ -1,15 +1,30 @@ + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + /* .text is used instead of .section .text so it works with arm-aout too. */ .text - .code 32 .align 0 +#if defined(THUMB_MODE) + .thumb_func +#endif .global _mainCRTStartup +_mainCRTStartup: +#if defined(THUMB_MODE) + .thumb_func +#endif .global _start +_start: +#if defined(THUMB_MODE) + .thumb_func +#endif .global start start: -_start: -_mainCRTStartup: /* Start by setting up a stack */ /* Set up the stack pointer to a fixed value */ @@ -69,24 +84,12 @@ _mainCRTStartup: .word _fini #endif */ /* Return ... */ -#ifdef __APCS_26__ - movs pc, lr -#else -#ifdef __THUMB_INTERWORK bx lr -#else - mov pc, lr -#endif -#endif .global _fini .type _fini,function _fini: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif /* Workspace for Angel calls. */ .data diff --git a/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S index 22e3eaf8..a48deaed 100644 --- a/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S @@ -23,7 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0xD3 // Disable IRQ/FIQ SVC mode IRQ_MODE = 0xD2 // Disable IRQ/FIQ IRQ mode @@ -48,22 +53,6 @@ SYS_STACK_SIZE = 1024 // System stack size .global enableCaches .global init_private_timer .global start_private_timer -/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_initialize_low_level - .type $_tx_initialize_low_level,function -$_tx_initialize_low_level: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_initialize_low_level // Call _tx_initialize_low_level function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller .text .align 2 @@ -113,6 +102,9 @@ $_tx_initialize_low_level: /* resulting in version 6.3.0 */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_initialize_low_level .type _tx_initialize_low_level,function _tx_initialize_low_level: @@ -201,34 +193,49 @@ _stack_error_loop: BL start_private_timer POP {lr} -#ifdef __THUMB_INTERWORK + BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif /* Define shells for each of the interrupt vectors. */ +#if defined(THUMB_MODE) + .thumb_func +#endif .global __tx_undefined __tx_undefined: B __tx_undefined // Undefined handler +#if defined(THUMB_MODE) + .thumb_func +#endif .global __tx_swi_interrupt __tx_swi_interrupt: B __tx_swi_interrupt // Software interrupt handler +#if defined(THUMB_MODE) + .thumb_func +#endif .global __tx_prefetch_handler __tx_prefetch_handler: B __tx_prefetch_handler // Prefetch exception handler +#if defined(THUMB_MODE) + .thumb_func +#endif .global __tx_abort_handler __tx_abort_handler: B __tx_abort_handler // Abort exception handler +#if defined(THUMB_MODE) + .thumb_func +#endif .global __tx_reserved_handler __tx_reserved_handler: B __tx_reserved_handler // Reserved exception handler +#if defined(THUMB_MODE) + .thumb_func +#endif .global __tx_irq_handler .global __tx_irq_processing_return __tx_irq_handler: @@ -302,6 +309,9 @@ by_pass_timer_interrupt: #ifdef TX_ENABLE_FIQ_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global __tx_fiq_handler .global __tx_fiq_processing_return __tx_fiq_handler: @@ -336,6 +346,9 @@ __tx_fiq_processing_return: #else +#if defined(THUMB_MODE) + .thumb_func +#endif .global __tx_fiq_handler __tx_fiq_handler: B __tx_fiq_handler // FIQ interrupt handler diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_restore.S b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a7/gnu/src/tx_thread_schedule.S b/ports/cortex_a7/gnu/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a7/gnu/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a7/gnu/src/tx_thread_stack_build.S b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a7/gnu/src/tx_thread_system_return.S b/ports/cortex_a7/gnu/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a7/gnu/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a7/gnu/src/tx_timer_interrupt.S b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a7/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a8/ac6/src/tx_thread_context_restore.S b/ports/cortex_a8/ac6/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a8/ac6/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a8/ac6/src/tx_thread_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a8/ac6/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a8/ac6/src/tx_thread_schedule.S b/ports/cortex_a8/ac6/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a8/ac6/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a8/ac6/src/tx_thread_stack_build.S b/ports/cortex_a8/ac6/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a8/ac6/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a8/ac6/src/tx_thread_system_return.S b/ports/cortex_a8/ac6/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a8/ac6/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a8/ac6/src/tx_timer_interrupt.S b/ports/cortex_a8/ac6/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a8/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a8/ac6/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a8/gnu/example_build/crt0.S b/ports/cortex_a8/gnu/example_build/crt0.S index d25196ef..abc817d5 100644 --- a/ports/cortex_a8/gnu/example_build/crt0.S +++ b/ports/cortex_a8/gnu/example_build/crt0.S @@ -1,15 +1,30 @@ + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + /* .text is used instead of .section .text so it works with arm-aout too. */ .text - .code 32 .align 0 +#if defined(THUMB_MODE) + .thumb_func +#endif .global _mainCRTStartup +_mainCRTStartup: +#if defined(THUMB_MODE) + .thumb_func +#endif .global _start +_start: +#if defined(THUMB_MODE) + .thumb_func +#endif .global start start: -_start: -_mainCRTStartup: /* Start by setting up a stack */ /* Set up the stack pointer to a fixed value */ @@ -69,24 +84,12 @@ _mainCRTStartup: .word _fini #endif */ /* Return ... */ -#ifdef __APCS_26__ - movs pc, lr -#else -#ifdef __THUMB_INTERWORK bx lr -#else - mov pc, lr -#endif -#endif .global _fini .type _fini,function _fini: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif /* Workspace for Angel calls. */ .data diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_restore.S b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a8/gnu/src/tx_thread_schedule.S b/ports/cortex_a8/gnu/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a8/gnu/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a8/gnu/src/tx_thread_stack_build.S b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a8/gnu/src/tx_thread_system_return.S b/ports/cortex_a8/gnu/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a8/gnu/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a8/gnu/src/tx_timer_interrupt.S b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a8/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a9/ac6/src/tx_thread_context_restore.S b/ports/cortex_a9/ac6/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a9/ac6/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a9/ac6/src/tx_thread_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a9/ac6/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a9/ac6/src/tx_thread_schedule.S b/ports/cortex_a9/ac6/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a9/ac6/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a9/ac6/src/tx_thread_stack_build.S b/ports/cortex_a9/ac6/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a9/ac6/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a9/ac6/src/tx_thread_system_return.S b/ports/cortex_a9/ac6/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a9/ac6/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a9/ac6/src/tx_timer_interrupt.S b/ports/cortex_a9/ac6/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a9/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a9/ac6/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a9/gnu/example_build/crt0.S b/ports/cortex_a9/gnu/example_build/crt0.S index d25196ef..abc817d5 100644 --- a/ports/cortex_a9/gnu/example_build/crt0.S +++ b/ports/cortex_a9/gnu/example_build/crt0.S @@ -1,15 +1,30 @@ + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + /* .text is used instead of .section .text so it works with arm-aout too. */ .text - .code 32 .align 0 +#if defined(THUMB_MODE) + .thumb_func +#endif .global _mainCRTStartup +_mainCRTStartup: +#if defined(THUMB_MODE) + .thumb_func +#endif .global _start +_start: +#if defined(THUMB_MODE) + .thumb_func +#endif .global start start: -_start: -_mainCRTStartup: /* Start by setting up a stack */ /* Set up the stack pointer to a fixed value */ @@ -69,24 +84,12 @@ _mainCRTStartup: .word _fini #endif */ /* Return ... */ -#ifdef __APCS_26__ - movs pc, lr -#else -#ifdef __THUMB_INTERWORK bx lr -#else - mov pc, lr -#endif -#endif .global _fini .type _fini,function _fini: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif /* Workspace for Angel calls. */ .data diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_restore.S b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports/cortex_a9/gnu/src/tx_thread_schedule.S b/ports/cortex_a9/gnu/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a9/gnu/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports/cortex_a9/gnu/src/tx_thread_stack_build.S b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports/cortex_a9/gnu/src/tx_thread_system_return.S b/ports/cortex_a9/gnu/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a9/gnu/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports/cortex_a9/gnu/src/tx_timer_interrupt.S b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports/cortex_a9/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S index 3f72e593..0a1b296b 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S @@ -23,16 +23,16 @@ #include "tx_user.h" #endif - .arm - -#ifdef TX_ENABLE_FIQ_SUPPORT -SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode -IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode + .syntax unified +#if defined(THUMB_MODE) + .thumb #else -SVC_MODE = 0x93 // Disable IRQ, SVC mode -IRQ_MODE = 0x92 // Disable IRQ, IRQ mode + .arm #endif +SVC_MODE = 0x13 // SVC mode +IRQ_MODE = 0x12 // IRQ mode + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_thread_execute_ptr @@ -45,7 +45,6 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -53,7 +52,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore @@ -129,9 +131,9 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_not_nested_restore: @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* Recover the saved context and return to the point of interrupt. */ - LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs MSR SPSR_cxsf, r0 // Put SPSR back - LDMIA sp!, {r0-r3} // Recover r0-r3 + POP {r0-r3} // Recover r0-r3 MOVS pc, lr // Return to point of interrupt __tx_thread_preempt_restore: - LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + POP {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - MOV r2, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r2 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode STR r1, [sp, #-4]! // Save point of interrupt - STMDB sp!, {r4-r12, lr} // Save upper half of registers + PUSH {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - MOV r2, #IRQ_MODE // Build IRQ mode CPSR - MSR CPSR_c, r2 // Enter IRQ mode - LDMIA sp!, {r0-r3} // Recover r0-r3 - MOV r5, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r5 // Enter SVC mode - STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + CPS #IRQ_MODE // Enter IRQ mode + POP {r0-r3} // Recover r0-r3 + CPS #SVC_MODE // Enter SVC mode + PUSH {r0-r3} // Save r0-r3 on thread's stack LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -192,13 +191,11 @@ __tx_thread_preempt_restore: STR r2, [sp, #-4]! // Save FPSCR VSTMDB sp!, {D16-D31} // Save D16-D31 VSTMDB sp!, {D0-D15} // Save D0-D15 - _tx_skip_irq_vfp_save: - #endif MOV r3, #1 // Build interrupt stack type - STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + PUSH {r3, r4} // Save interrupt stack type and SPSR STR sp, [r0, #8] // Save stack pointer in thread control // block @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts: __tx_thread_idle_system_restore: /* Just return back to the scheduler! */ - MOV r0, #SVC_MODE // Build SVC mode CPSR - MSR CPSR_c, r0 // Enter SVC mode + CPS #SVC_MODE // Enter SVC mode B _tx_thread_schedule // Return to scheduler diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S index 53703935..5c26fbda 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_irq_processing_return @@ -31,7 +38,6 @@ /* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save since it will never be called 16-bit mode. */ - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +45,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +85,9 @@ /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save @@ -90,7 +99,7 @@ _tx_thread_context_save: /* Check for a nested interrupt condition. */ - STMDB sp!, {r0-r3} // Save some working registers + PUSH {r0-r3} // Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable FIQ interrupts #endif @@ -101,15 +110,15 @@ _tx_thread_context_save: /* Nested interrupt condition. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable /* Save the rest of the scratch registers on the stack and return to the calling ISR. */ MRS r0, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r0, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r0, r10, r12, lr} // Store other registers /* Return to the ISR. */ @@ -129,7 +138,7 @@ _tx_thread_context_save: __tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - ADD r2, r2, #1 // Increment the interrupt counter + ADD r2, #1 // Increment the interrupt counter STR r2, [r3] // Store it back in the variable LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR r0, [r1] // Pickup current thread pointer @@ -140,8 +149,8 @@ __tx_thread_not_nested_save: /* Save minimal context of interrupted thread. */ MRS r2, SPSR // Pickup saved SPSR - SUB lr, lr, #4 // Adjust point of interrupt - STMDB sp!, {r2, r10, r12, lr} // Store other registers + SUB lr, #4 // Adjust point of interrupt + PUSH {r2, r10, r12, lr} // Store other registers MOV r10, #0 // Clear stack limit @@ -174,5 +183,5 @@ __tx_thread_idle_system_save: POP {lr} // Recover ISR lr #endif - ADD sp, sp, #16 // Recover saved registers + ADD sp, #16 // Recover saved registers B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S index 2cffa546..79ba41e6 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask FIQ_MODE_BITS = 0x11 // FIQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_end .type _tx_thread_fiq_nesting_end,function _tx_thread_fiq_nesting_end: @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end: ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S index d8ce930c..3f8fbbce 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_fiq_nesting_start .type _tx_thread_fiq_nesting_start,function _tx_thread_fiq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S index fba205f3..50a0aa8f 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S @@ -23,25 +23,18 @@ #include "tx_user.h" #endif -INT_MASK = 0x03F - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_control -$_tx_thread_interrupt_control: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +INT_MASK = 0x0C0 +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -50,7 +43,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,25 +79,35 @@ $_tx_thread_interrupt_control: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function _tx_thread_interrupt_control: + MRS r1, CPSR // Pickup current CPSR - /* Pickup current interrupt lockout posture. */ - - MRS r3, CPSR // Pickup current CPSR - MOV r2, #INT_MASK // Build interrupt mask - AND r1, r3, r2 // Clear interrupt lockout bits - ORR r1, r1, r0 // Or-in new interrupt lockout bits - - /* Apply the new interrupt posture. */ - - MSR CPSR_c, r1 // Setup new CPSR - BIC r0, r3, r2 // Return previous interrupt mask -#ifdef __THUMB_INTERWORK - BX lr // Return to caller +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ #else - MOV pc, lr // Return to caller + CPSID i // Disable IRQ #endif + + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + + AND r0, r1, #INT_MASK + BX lr diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S index 6b6b9783..233c5196 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S @@ -23,22 +23,12 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_disable -$_tx_thread_interrupt_disable: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - +#endif .text .align 2 @@ -47,7 +37,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,8 +72,14 @@ $_tx_thread_interrupt_disable: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function _tx_thread_interrupt_disable: @@ -100,8 +96,4 @@ _tx_thread_interrupt_disable: CPSID i // Disable IRQ #endif -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S index 8f138bae..e980aa47 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S @@ -23,22 +23,17 @@ #include "tx_user.h" #endif -/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_interrupt_restore -$_tx_thread_interrupt_restore: - .thumb - BX pc // Switch to 32-bit mode - NOP // + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller +#endif +IRQ_MASK = 0x080 +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif .text .align 2 @@ -47,7 +42,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,17 +78,27 @@ $_tx_thread_interrupt_restore: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function _tx_thread_interrupt_restore: - /* Apply the new interrupt posture. */ + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif - MSR CPSR_c, r0 // Setup new CPSR -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S index 78ca9fc5..a844e608 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S @@ -23,6 +23,13 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts #else @@ -31,11 +38,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts MODE_MASK = 0x1F // Mode mask IRQ_MODE_BITS = 0x12 // IRQ mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,8 +90,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function _tx_thread_irq_nesting_end: @@ -102,8 +110,4 @@ _tx_thread_irq_nesting_end: BIC r0, r0, #MODE_MASK // Clear mode bits ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR MSR CPSR_c, r0 // Reenter IRQ mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S index 6f2b367b..e79e1802 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S @@ -23,15 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask SYS_MODE_BITS = 0x1F // System mode bits - -/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start - since it will never be called 16-bit mode. */ - - .arm .text .align 2 /**************************************************************************/ @@ -39,7 +41,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function _tx_thread_irq_nesting_start: @@ -95,8 +103,4 @@ _tx_thread_irq_nesting_start: // and push r1 just to keep 8-byte alignment BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR MSR CPSR_c, r0 // Enter system mode -#ifdef __THUMB_INTERWORK BX r3 // Return to caller -#else - MOV pc, r3 // Return to caller -#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S index e3c76dc9..33eba1c3 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S @@ -23,37 +23,29 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice - -/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for - applications calling this function from to 16-bit Thumb mode. */ - .text - .align 2 - .global $_tx_thread_schedule - .type $_tx_thread_schedule,function -$_tx_thread_schedule: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_schedule // Call _tx_thread_schedule function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller + .align 2 +#define IRQ_MODE 0x12 // IRQ mode +#define SVC_MODE 0x13 // SVC mode - .text - .align 2 /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,8 +87,14 @@ $_tx_thread_schedule: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_schedule .type _tx_thread_schedule,function _tx_thread_schedule: @@ -140,30 +138,39 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ - LDR r2, =_tx_timer_time_slice // Pickup address of time-slice - // variable - LDR sp, [r0, #8] // Switch stack pointers + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable STR r3, [r2] // Setup time-slice + LDR sp, [r0, #8] // Switch stack pointers + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - /* Call the thread entry function to indicate the thread is executing. */ + /* Call the thread entry function to indicate the thread is executing. */ MOV r5, r0 // Save r0 BL _tx_execution_thread_enter // Call the thread execution enter function MOV r0, r5 // Restore r0 #endif - /* Determine if an interrupt frame or a synchronous task suspension frame - is present. */ + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + POP {r4, r5} // Pickup the stack type and saved CPSR CMP r4, #0 // Check for synchronous context switch BEQ _tx_solicited_return + +#if !defined(THUMB_MODE) + MSR SPSR_cxsf, r5 // Setup SPSR for return +#else + CPS #IRQ_MODE // Enter IRQ mode MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SVC_MODE // Enter SVC mode +#endif + #ifdef TX_ENABLE_VFP_SUPPORT - LDR r1, [r0, #144] // Pickup the VFP enabled flag - CMP r1, #0 // Is the VFP enabled? + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore VLDMIA sp!, {D0-D15} // Recover D0-D15 VLDMIA sp!, {D16-D31} // Recover D16-D31 @@ -171,7 +178,15 @@ __tx_thread_schedule_loop: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_interrupt_vfp_restore: #endif + +#if !defined(THUMB_MODE) LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt +#else + POP {r0-r12, lr} // Restore registers + ADD sp, #4 // Fix stack pointer (skip PC saved on stack) + CPS #IRQ_MODE // Enter IRQ mode + SUBS pc, lr, #0 // Return to point of thread interrupt +#endif _tx_solicited_return: @@ -185,52 +200,63 @@ _tx_solicited_return: VMSR FPSCR, r4 // Restore FPSCR _tx_skip_solicited_vfp_restore: #endif + MSR CPSR_cxsf, r5 // Recover CPSR - LDMIA sp!, {r4-r11, lr} // Return to thread synchronously -#ifdef __THUMB_INTERWORK + POP {r4-r11, lr} // Restore registers BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif #ifdef TX_ENABLE_VFP_SUPPORT +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_enable .type tx_thread_vfp_enable,function tx_thread_vfp_enable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable - MOV r0, #1 // Build enable value - STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP enable + MOV r2, #1 // Build enable value + STR r2, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + B restore_ints +#if defined(THUMB_MODE) + .thumb_func +#endif .global tx_thread_vfp_disable .type tx_thread_vfp_disable,function tx_thread_vfp_disable: - MRS r2, CPSR // Pickup the CPSR + MRS r0, CPSR // Pickup current CPSR #ifdef TX_ENABLE_FIQ_SUPPORT - CPSID if // Enable IRQ and FIQ interrupts + CPSID if // Disable IRQ and FIQ #else - CPSID i // Enable IRQ interrupts + CPSID i // Disable IRQ #endif - LDR r0, =_tx_thread_current_ptr // Build current thread pointer address - LDR r1, [r0] // Pickup current thread pointer + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r2] // Pickup current thread pointer CMP r1, #0 // Check for NULL thread pointer - BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable - MOV r0, #0 // Build disable value - STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: - MSR CPSR_cxsf, r2 // Recover CPSR - BX LR // Return to caller + BEQ restore_ints // If NULL, skip VFP disable + MOV r2, #0 // Build disable value + STR r2, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) + +restore_ints: + TST r0, #IRQ_MASK + BNE no_irq + CPSIE i +no_irq: +#ifdef TX_ENABLE_FIQ_SUPPORT + TST r0, #FIQ_MASK + BNE no_fiq + CPSIE f +no_fiq: +#endif + BX lr #endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S index c187f7c4..8401cd61 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S @@ -23,34 +23,23 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm +#endif SVC_MODE = 0x13 // SVC mode + +THUMB_MASK = 0x20 // Thumb bit mask + #ifdef TX_ENABLE_FIQ_SUPPORT -CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled #else -CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled #endif - -/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_thread_stack_build - .type $_tx_thread_stack_build,function -$_tx_thread_stack_build: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_stack_build // Call _tx_thread_stack_build function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -58,7 +47,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -96,8 +85,14 @@ $_tx_thread_stack_build: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_stack_build .type _tx_thread_stack_build,function _tx_thread_stack_build: @@ -135,6 +130,15 @@ _tx_thread_stack_build: MOV r3, #1 // Build interrupt stack type STR r3, [r2, #0] // Store stack type + + MRS r3, CPSR // Pickup CPSR + BIC r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, #SVC_MODE // Build CPSR, SYS mode, interrupts enabled + TST r1, #1 // Check if the initial PC is a Thumb function + IT NE + ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this + STR r3, [r2, #4] // Store initial CPSR + MOV r3, #0 // Build initial register value STR r3, [r2, #8] // Store initial r0 STR r3, [r2, #12] // Store initial r1 @@ -146,26 +150,20 @@ _tx_thread_stack_build: STR r3, [r2, #36] // Store initial r7 STR r3, [r2, #40] // Store initial r8 STR r3, [r2, #44] // Store initial r9 + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #68] // 0 for back-trace + LDR r3, [r0, #12] // Pickup stack starting address STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace STR r3, [r2, #60] // Store initial r14 (lr) - MOV r3, #0 // Build initial register value - STR r3, [r2, #52] // Store initial r11 - STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc - STR r3, [r2, #68] // 0 for back-trace - MRS r1, CPSR // Pickup CPSR - BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR - ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - STR r3, [r2, #4] // Store initial CPSR /* Setup stack pointer. */ STR r2, [r0, #8] // Save stack pointer in thread's // control block -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S index 1cc85acc..d17de10d 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S @@ -23,33 +23,17 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif .global _tx_thread_current_ptr .global _tx_timer_time_slice .global _tx_thread_schedule - - -/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .global $_tx_thread_system_return - .type $_tx_thread_system_return,function -$_tx_thread_system_return: - .thumb - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_thread_system_return // Call _tx_thread_system_return function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -57,7 +41,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,15 +82,21 @@ $_tx_thread_system_return: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_thread_system_return .type _tx_thread_system_return,function _tx_thread_system_return: /* Save minimal context on the stack. */ - STMDB sp!, {r4-r11, lr} // Save minimal context + PUSH {r4-r11, lr} // Save minimal context LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr LDR r5, [r4] // Pickup current thread pointer @@ -123,8 +113,11 @@ _tx_skip_solicited_vfp_save: #endif MOV r0, #0 // Build a solicited stack type - MRS r1, CPSR // Pickup the CPSR - STMDB sp!, {r0-r1} // Save type and CPSR + MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware + TST lr, #1 // Check if calling function is in Thumb mode + IT NE + ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return + PUSH {r0-r1} // Save type and CPSR /* Lockout interrupts. */ diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S b/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S index a56f3955..b4745f27 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S @@ -23,8 +23,12 @@ #include "tx_user.h" #endif + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else .arm - +#endif /* Define Assembly language external references... */ @@ -37,26 +41,6 @@ .global _tx_timer_expired .global _tx_thread_time_slice - - -/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for - applications calling this function from to 16-bit Thumb mode. */ - - .text - .align 2 - .thumb - .global $_tx_timer_interrupt - .type $_tx_timer_interrupt,function -$_tx_timer_interrupt: - BX pc // Switch to 32-bit mode - NOP // - .arm - STMFD sp!, {lr} // Save return address - BL _tx_timer_interrupt // Call _tx_timer_interrupt function - LDMFD sp!, {lr} // Recover saved return address - BX lr // Return to 16-bit caller - - .text .align 2 /**************************************************************************/ @@ -64,7 +48,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.3.0 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,8 +88,14 @@ $_tx_timer_interrupt: /* 10-31-2023 Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ /* resulting in version 6.3.0 */ +/* xx-xx-xxxx Yajun Xia Modified comment(s), */ +/* Added thumb mode support, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ +#if defined(THUMB_MODE) + .thumb_func +#endif .global _tx_timer_interrupt .type _tx_timer_interrupt,function _tx_timer_interrupt: @@ -197,7 +187,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -225,13 +215,9 @@ __tx_timer_dont_activate: __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment __tx_timer_nothing_expired: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/crt0.S b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/crt0.S index d25196ef..abc817d5 100644 --- a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/crt0.S +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/crt0.S @@ -1,15 +1,30 @@ + .syntax unified +#if defined(THUMB_MODE) + .thumb +#else + .arm +#endif + /* .text is used instead of .section .text so it works with arm-aout too. */ .text - .code 32 .align 0 +#if defined(THUMB_MODE) + .thumb_func +#endif .global _mainCRTStartup +_mainCRTStartup: +#if defined(THUMB_MODE) + .thumb_func +#endif .global _start +_start: +#if defined(THUMB_MODE) + .thumb_func +#endif .global start start: -_start: -_mainCRTStartup: /* Start by setting up a stack */ /* Set up the stack pointer to a fixed value */ @@ -69,24 +84,12 @@ _mainCRTStartup: .word _fini #endif */ /* Return ... */ -#ifdef __APCS_26__ - movs pc, lr -#else -#ifdef __THUMB_INTERWORK bx lr -#else - mov pc, lr -#endif -#endif .global _fini .type _fini,function _fini: -#ifdef __THUMB_INTERWORK BX lr // Return to caller -#else - MOV pc, lr // Return to caller -#endif /* Workspace for Angel calls. */ .data diff --git a/test/ports/azrtos_test_tx_gnu_cortex_a5.log.expected b/test/ports/azrtos_test_tx_gnu_cortex_a5.log.expected index 6bbb7579..74929dbb 100644 --- a/test/ports/azrtos_test_tx_gnu_cortex_a5.log.expected +++ b/test/ports/azrtos_test_tx_gnu_cortex_a5.log.expected @@ -1,9 +1,9 @@ >output thread_0_counter 10 >output thread_1_counter -599068 +599009 >output thread_2_counter -599046 +598944 >output thread_3_counter 23 >output thread_4_counter diff --git a/test/ports/azrtos_test_tx_gnu_cortex_a7.log.expected b/test/ports/azrtos_test_tx_gnu_cortex_a7.log.expected index 21efba52..522be230 100644 --- a/test/ports/azrtos_test_tx_gnu_cortex_a7.log.expected +++ b/test/ports/azrtos_test_tx_gnu_cortex_a7.log.expected @@ -3,7 +3,7 @@ >output thread_1_counter 299267 >output thread_2_counter -299268 +299185 >output thread_3_counter 23 >output thread_4_counter diff --git a/test/ports/azrtos_test_tx_gnu_cortex_a8.log.expected b/test/ports/azrtos_test_tx_gnu_cortex_a8.log.expected index 21efba52..64eb59b5 100644 --- a/test/ports/azrtos_test_tx_gnu_cortex_a8.log.expected +++ b/test/ports/azrtos_test_tx_gnu_cortex_a8.log.expected @@ -3,7 +3,7 @@ >output thread_1_counter 299267 >output thread_2_counter -299268 +299184 >output thread_3_counter 23 >output thread_4_counter diff --git a/test/ports/azrtos_test_tx_gnu_cortex_a9.log.expected b/test/ports/azrtos_test_tx_gnu_cortex_a9.log.expected index 6bbb7579..74929dbb 100644 --- a/test/ports/azrtos_test_tx_gnu_cortex_a9.log.expected +++ b/test/ports/azrtos_test_tx_gnu_cortex_a9.log.expected @@ -1,9 +1,9 @@ >output thread_0_counter 10 >output thread_1_counter -599068 +599009 >output thread_2_counter -599046 +598944 >output thread_3_counter 23 >output thread_4_counter |