Ran the interrupt handler from ATCM, and measured what that buys (#630)

The TCM work so far enabled ATCM and left it empty, which buys nothing.
This places code in it and measures the result.

link.lds gains an ATCM region and an .atcm_text section whose run address
is in the bank and whose load address is in CODE. tcm_copy_atcm_text
moves it, using 64-bit stores because ECC is enabled on this part and
ATCM requires them (Cortex-R52 TRM 6.2.2); both ends of the section are
8-byte aligned so there is no narrower tail to leave without check bits.
The copy runs after T4 and T5, which write test patterns to the first and
last words of the bank and would otherwise land on top of the code.

s32z280_atcm.elf is the same image as s32z280_boot.elf with the interrupt
service body placed in ATCM. Both targets exist so the comparison can be
repeated on one board in one session without reconfiguring. The service
routine is split into a timed wrapper that stays in .text and a body that
moves, so the wrapper's own cost appears in both measurements and cancels.

Measured in PMU cycles over 64 samples, caches enabled in both:

                 code RAM    ATCM    change
    min               454     334    -26.4%
    mean              458     340    -25.8%
    max               612     466    -23.9%
    spread            158     132    -16.5%

CNTPCT is not used for this: at 8 MHz it cannot resolve a handler body,
let alone the variation in one.

The level shift is the solid part. ATCM is a quarter faster even though
the caches were on and code RAM had the instruction cache available,
which says the handler does not stay resident between interrupts 10 ms
apart -- so each one pays a cold fetch from code RAM, which runs at half
the core frequency where ATCM runs at full speed with one wait state
(S32Z2 RM 6.3.6).

The determinism claim deserves less weight than the numbers first
suggest. The spread narrows by only 16%, and ATCM's worst case still sits
slightly above code RAM's best case, so the two distributions overlap at
the tails rather than separating. Whatever jitter remains is not
dominated by instruction fetch.

Both images pass six of six boot probes.

Assisted-by: Claude Code (Opus 5) <[email protected]>

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