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| author | Akif Ejaz <[email protected]> | 2026-05-19 20:03:23 +0500 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-05-19 11:03:23 -0400 |
| commit | c1e3678797d5249268756287a33e5aca729a7631 (patch) | |
| tree | 6279923a90fd3ad0206df4b167b46246bf71e2d0 /common_modules/module_lib/src/txm_queue_delete.c | |
| parent | 0dd6d28afb54c17eae485fa8e7c9e6a7999353ff (diff) | |
Add QEMU based CI regression test infra for RV32 and RV64 (#526)
Added a QEMU virt-machine BSP and CTest infrastructure to run the
ThreadX regression suite on both RISC-V 32-bit and 64-bit targets
in CI.
New components:
- BSP (entry, trap, PLIC, CLINT timer, UART, linker script) targeting
QEMU virt machine for RV32 and RV64
- CMake build system with Ninja, supporting multiple build configs
- CI scripts: install_riscv.sh (toolchain + QEMU), build_tx_riscv.sh,
test_tx_riscv.sh
- GitHub Actions workflow job for RISC-V regression gating
Port fixes:
- RV32 tx_thread_context_restore.S: set MPIE alongside MPP (0x1800 →
0x1880) so mret re-enables interrupts
- RV32/RV64 tx_port.h: add TX_REGRESSION_TEST extension macros needed
by the test harness
- RV32/RV64 example_build scripts: add compile and QEMU launch steps
Regression test portability fixes:
- Block memory tests: increase pool sizes (320 → 340) to accommodate
larger RISC-V block-header alignment
- Byte memory test: replace hardcoded offsets with BYTE_POOL_OVERHEAD
macro for portable pool-size computation
- Event flag timeout test: make counter tolerance unconditional,
removing linux-only guard
Signed-off-by: Akif Ejaz <[email protected]>
Diffstat (limited to 'common_modules/module_lib/src/txm_queue_delete.c')
0 files changed, 0 insertions, 0 deletions
