riscv64: spec compliance and regression test fix (#698)

* spec compliance

Signed-off-by: Akif Ejaz <[email protected]>

* revert the demo changes

Signed-off-by: Akif Ejaz <[email protected]>

* Restored the FPU demo hook so the RISC-V64 functional test can pass

The new check-functional-riscv64 target verifies FPU context switching by
watching fpu_test_val advance by 1.1f on each pass through
thread_6_and_7_entry. The GDB script deliberately treats a missing symbol
as a failure rather than silently skipping the check, but the demo no
longer defined it, so the target failed on every run:

    FPU_VERIFIED_FAIL_NO_SYMBOL

The definition and the increment are restored, matching what the risc-v32
demo already carries. The functional target now passes end to end.

Three small corrections are folded in:

- tx_port.h carried a comment stating that the ISA string must include
  Zicsr, but nothing enforced it, so an rv64imac build failed with a wall
  of assembler "unrecognized opcode" errors. It now stops at one clear
  diagnostic.
- Removed TX_RISCV_TRAP_CALL_FRAME_SIZE, which nothing referenced.
- The example .gitignore listed qemu-riscv32.log, but the runner writes
  qemu-riscv64.log, so the generated log showed up as an untracked file.

Assisted-by: Claude Code (Opus 5) <[email protected]>

---------

Signed-off-by: Akif Ejaz <[email protected]>
Co-authored-by: Frédéric Desbiens <[email protected]>

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