diff options
| author | tameraw <[email protected]> | 2020-07-16 14:32:40 -0700 |
|---|---|---|
| committer | tameraw <[email protected]> | 2020-07-16 14:32:40 -0700 |
| commit | 2c35570dc9ced8690ea269d1efab201c361fea98 (patch) | |
| tree | a950c056346ab9a2260ba92a6be8ee3dd91ab7b6 /ports/c667x/ccs/example_build | |
| parent | f8e91d47625881614fe28efbcd43470922590d42 (diff) | |
updated to 6.0.1 and added additional processors/toolchains
Diffstat (limited to 'ports/c667x/ccs/example_build')
48 files changed, 12824 insertions, 0 deletions
diff --git a/ports/c667x/ccs/example_build/include/C66XX.h b/ports/c667x/ccs/example_build/include/C66XX.h new file mode 100644 index 00000000..581b563e --- /dev/null +++ b/ports/c667x/ccs/example_build/include/C66XX.h @@ -0,0 +1,150 @@ +/****************************************************************************** + TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. + Definitions, macros and API functions for DSP Environment. + (C) MicroLAB Systems, 2015 + + + http://www.mlabsys.com + ftp://ftp.mlabsys.com + email: [email protected] + + + Description: + ------------ + This file contains definitions, macros and API functions for KeyStone + Multicore DSP environment and must be included in the user C-application. + DSP Software Development Kit library is based on TI Chip Support Library + (CSL), so it's needed to add CSL libraries into the project along with DSP + Software Development Kit library. + + Note that C66xx CorePac interrupt controller (INTC) functions are not + included in this DSP Software Utilities library. + It's delivered as a separate library from the remaining DSP Software + Utilities. When using an embedded operating system that contains interrupt + controller/dispatcher support, do not link in the INTC library. + For interrupt controller support, SYS/BIOS users should use + the HWI (Hardware Interrupt) and ECM (Event Combiner Manager) modules + supported under SYS/BIOS v5.21 or later. + + + Revision history: + ----------------- + rev.1A - 2014, initial release for C6678 DSP. + rev.1B - 2015, fixed minor bugs. + rev.1C - 2015: + - changed C66XX_init_ddr3() DDR3 initialization + function; + - added DSP chip-level (CPINTC) interrupt controller + functions; + rev.2A - 2015, totally redesigned DSP SDK; + + + Notes: + ------ + 1. This C-header file is an include file for TI C6xxx C/C++ Code + Generation Tools, which must be invoked to compile code for C66xx DSP + platform. + + 2. The following additional libraries should be included: + TI Chip Support Library (CSL) (ti.csl.ae66) should be included in + Linker options (this library is located at + $(TI_PDK_C6678_INSTALL_DIR)\packages\ti\csl\lib). + + 3. This file is best viewed with the TAB setting set to '4'. + + 4. This header file is externally controlled from user C-code by run-time + compiler keys definitions in order to apply DSP-type specific + definitions to refer to particular definitions included for different + DSP type: + + __C66XX_SELECT_C6678_DSP__ + - if defined in user code prior inclusion of this header file, + then DSP-type specific definitions are applied to C6678 DSP + + Copyright: + ---------- + This utility is supplied free of charge as it is without any obligation + from MicroLAB Systems. No responsibility is assumed for any use or misuse + of these utilities. + +******************************************************************************/ + + +/** + * @file C66XX.h + * + * @brief KeyStone Multicore DSP SDK include file + * + * This file contains definitions, macros and API functions for KeyStone + * Multicore DSP environment + * + */ + + +#ifndef __C66XX_H__ // check for this file has been already included +#define __C66XX_H__ 1 + + +// General defs +#define C66XX_ON 1 +#define C66XX_OFF 0 + + +//============================================================================= +//------------ DSP-type specific run-time compiler keys processing ------------ +// (this is required in order to exclude key confusions) + +// Default setting is C6678 definitions +#ifndef __C66XX_SELECT_C6678_DSP__ +#define __C66XX_SELECT_C6678_DSP__ 1 +#endif /* __C66XX_SELECT_C6678_DSP__ */ + +//============================================================================= + + +/** KeyStone Multicore DSP SDK revision ID */ +#define C66XX_SDK_REVISION_ID "2A" + + +// Include TI Chip Support Library (CSL) defs +// CSL Chip Functional Layer +#include <ti/csl/csl_chipAux.h> +// CSL TSC Functional Layer +#include <ti/csl/csl_tsc.h> +// CSL Cache Functional Layer +#include <ti/csl/csl_cacheAux.h> +// CSL Boot configuration defs +#include <ti/csl/csl_bootcfgAux.h> +// CSL Power and Sleep Controller defs +#include <ti/csl/csl_pscAux.h> +// CSL XMC Controller defs +#include <ti/csl/csl_xmcAux.h> +// CSL DDR3 defs +#include <ti/csl/csl_emif4f.h> +#include <ti/csl/csl_emif4fAux.h> +// CSL INTC defs +#include <ti/csl/src/intc/csl_intcAux.h> +// CSL CPINTC defs +#include <ti/csl/csl_cpIntcAux.h> +// CSL SGMII defs +#include <ti/csl/csl_cpsgmiiAux.h> +#include <ti/csl/csl_cpgmac_slAux.h> +// CSL GPIO Functional Layer +#include <ti/csl/csl_gpioAux.h> +// CSL Timer Functional Layer +#include <ti/csl/csl_tmrAux.h> +// CSL UART Functional Layer +#include <ti/csl/cslr_uart.h> +// CSL SRIO Functional Layer +#include <ti/csl/csl_srioAux.h> +#include <ti/csl/csl_srioAuxPhyLayer.h> + + +// Include C66xx DSP defs, macros and aux functions +#include "C66XX_DEF.hxx" +#include "C66XX_MACROS.hxx" +#include "C66XX_FUNCTIONS.hxx" + + +//============================================================================= +#endif /* __C66XX_H__ */ diff --git a/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx b/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx new file mode 100644 index 00000000..9764a47f --- /dev/null +++ b/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx @@ -0,0 +1,1678 @@ +/****************************************************************************** + TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. + (C) MicroLAB Systems, 2014-2015 + + File: Definitions + ----- + + Notes: + ------ + 1. This C-header file contains general DSP definitions and + is used with C66XX.h C-header file. + + 2. This file is best viewed with the TAB setting set to '4'. + +******************************************************************************/ + + +/** + * @file C66XX_DEF.hxx + * + * @brief Definitions + * + * This file contains general C66xx DSP definitions + * + */ + + +#ifndef __C66XX_DEF_HXX__ // check for this file has been already included +#define __C66XX_DEF_HXX__ 1 + + +//============================================================================= +//============ DSP CPU ID ===================================================== +//============================================================================= + +// DSP CPU ID is located at CSR register and is used to identify the chip +#define C66XX_DSP_CPU_ID 0x15 +//============================================================================= + + + +#ifdef __C66XX_SELECT_C6678_DSP__ +//============================================================================= +//============ DSP cores number =============================================== +//============================================================================= +#define C66XX_DSP_NUMBER_OF_CORES 8 +//============================================================================= + + +//============================================================================= +//============ DSP memory map ================================================= +//============================================================================= +// All address ranges refer to 32-bit LOGICAL addresses!!! + +// Local L2 SRAM - 512KB +#define C66XX_LOCAL_L2_SRAM_SADDR 0x00800000 +#define C66XX_LOCAL_L2_SRAM_EADDR 0x0087ffff +#define C66XX_LOCAL_L2_SRAM_LEN (C66XX_LOCAL_L2_SRAM_EADDR - C66XX_LOCAL_L2_SRAM_SADDR + 1) + +// Local L1P SRAM - 32KB +#define C66XX_LOCAL_L1P_SRAM_SADDR 0x00e00000 +#define C66XX_LOCAL_L1P_SRAM_EADDR 0x00e07fff +#define C66XX_LOCAL_L1P_SRAM_LEN (C66XX_LOCAL_L1P_SRAM_EADDR - C66XX_LOCAL_L1P_SRAM_SADDR + 1) + +// Local L1D SRAM - 32KB +#define C66XX_LOCAL_L1D_SRAM_SADDR 0x00f00000 +#define C66XX_LOCAL_L1D_SRAM_EADDR 0x00f07fff +#define C66XX_LOCAL_L1D_SRAM_LEN (C66XX_LOCAL_L1D_SRAM_EADDR - C66XX_LOCAL_L1D_SRAM_SADDR + 1) + +// C66xx CorePack registers area - 4MB +#define C66XX_DSP_RG_AREA_SADDR 0x01800000 +#define C66XX_DSP_RG_AREA_EADDR 0x01bfffff +#define C66XX_DSP_RG_AREA_LEN (C66XX_DSP_RG_AREA_EADDR - C66XX_DSP_RG_AREA_SADDR + 1) + +// Tracer MSMC 0 registers area - 128B +#define C66XX_TRACER_MSMC_0_RG_AREA_SADDR 0x01d00000 +#define C66XX_TRACER_MSMC_0_RG_AREA_EADDR 0x01d0007f +#define C66XX_TRACER_MSMC_0_RG_AREA_LEN (C66XX_TRACER_MSMC_0_RG_AREA_EADDR - C66XX_TRACER_MSMC_0_RG_AREA_SADDR + 1) + +// Tracer MSMC 1 registers area - 128B +#define C66XX_TRACER_MSMC_1_RG_AREA_SADDR 0x01d08000 +#define C66XX_TRACER_MSMC_1_RG_AREA_EADDR 0x01d0807f +#define C66XX_TRACER_MSMC_1_RG_AREA_LEN (C66XX_TRACER_MSMC_1_RG_AREA_EADDR - C66XX_TRACER_MSMC_1_RG_AREA_SADDR + 1) + +// Tracer MSMC 2 registers area - 128B +#define C66XX_TRACER_MSMC_2_RG_AREA_SADDR 0x01d10000 +#define C66XX_TRACER_MSMC_2_RG_AREA_EADDR 0x01d1007f +#define C66XX_TRACER_MSMC_2_RG_AREA_LEN (C66XX_TRACER_MSMC_2_RG_AREA_EADDR - C66XX_TRACER_MSMC_2_RG_AREA_SADDR + 1) + +// Tracer MSMC 3 registers area - 128B +#define C66XX_TRACER_MSMC_3_RG_AREA_SADDR 0x01d18000 +#define C66XX_TRACER_MSMC_3_RG_AREA_EADDR 0x01d1807f +#define C66XX_TRACER_MSMC_3_RG_AREA_LEN (C66XX_TRACER_MSMC_3_RG_AREA_EADDR - C66XX_TRACER_MSMC_3_RG_AREA_SADDR + 1) + +// Tracer QM DMA registers area - 128B +#define C66XX_TRACER_QM_DMA_RG_AREA_SADDR 0x01d20000 +#define C66XX_TRACER_QM_DMA_RG_AREA_EADDR 0x01d2007f +#define C66XX_TRACER_QM_DMA_RG_AREA_LEN (C66XX_TRACER_QM_DMA_RG_AREA_EADDR - C66XX_TRACER_QM_DMA_RG_AREA_SADDR + 1) + +// Tracer DDR registers area - 128B +#define C66XX_TRACER_DDR_RG_AREA_SADDR 0x01d28000 +#define C66XX_TRACER_DDR_RG_AREA_EADDR 0x01d2807f +#define C66XX_TRACER_DDR_RG_AREA_LEN (C66XX_TRACER_DDR_RG_AREA_EADDR - C66XX_TRACER_DDR_RG_AREA_SADDR + 1) + +// Tracer SM registers area - 128B +#define C66XX_TRACER_SM_RG_AREA_SADDR 0x01d30000 +#define C66XX_TRACER_SM_RG_AREA_EADDR 0x01d3007f +#define C66XX_TRACER_SM_RG_AREA_LEN (C66XX_TRACER_SM_RG_AREA_EADDR - C66XX_TRACER_SM_RG_AREA_SADDR + 1) + +// Tracer QM CFG registers area - 128B +#define C66XX_TRACER_QM_CFG_RG_AREA_SADDR 0x01d38000 +#define C66XX_TRACER_QM_CFG_RG_AREA_EADDR 0x01d3807f +#define C66XX_TRACER_QM_CFG_RG_AREA_LEN (C66XX_TRACER_QM_CFG_RG_AREA_EADDR - C66XX_TRACER_QM_CFG_RG_AREA_SADDR + 1) + +// Tracer CFG registers area - 128B +#define C66XX_TRACER_CFG_RG_AREA_SADDR 0x01d40000 +#define C66XX_TRACER_CFG_RG_AREA_EADDR 0x01d4007f +#define C66XX_TRACER_CFG_RG_AREA_LEN (C66XX_TRACER_CFG_RG_AREA_EADDR - C66XX_TRACER_CFG_RG_AREA_SADDR + 1) + +// Tracer L2 0 registers area - 128B +#define C66XX_TRACER_L2_0_RG_AREA_SADDR 0x01d48000 +#define C66XX_TRACER_L2_0_RG_AREA_EADDR 0x01d4807f +#define C66XX_TRACER_L2_0_RG_AREA_LEN (C66XX_TRACER_L2_0_RG_AREA_EADDR - C66XX_TRACER_L2_0_RG_AREA_SADDR + 1) + +// Tracer L2 1 registers area - 128B +#define C66XX_TRACER_L2_1_RG_AREA_SADDR 0x01d50000 +#define C66XX_TRACER_L2_1_RG_AREA_EADDR 0x01d5007f +#define C66XX_TRACER_L2_1_RG_AREA_LEN (C66XX_TRACER_L2_1_RG_AREA_EADDR - C66XX_TRACER_L2_1_RG_AREA_SADDR + 1) + +// Tracer L2 2 registers area - 128B +#define C66XX_TRACER_L2_2_RG_AREA_SADDR 0x01d58000 +#define C66XX_TRACER_L2_2_RG_AREA_EADDR 0x01d5807f +#define C66XX_TRACER_L2_2_RG_AREA_LEN (C66XX_TRACER_L2_2_RG_AREA_EADDR - C66XX_TRACER_L2_2_RG_AREA_SADDR + 1) + +// Tracer L2 3 registers area - 128B +#define C66XX_TRACER_L2_3_RG_AREA_SADDR 0x01d60000 +#define C66XX_TRACER_L2_3_RG_AREA_EADDR 0x01d6007f +#define C66XX_TRACER_L2_3_RG_AREA_LEN (C66XX_TRACER_L2_3_RG_AREA_EADDR - C66XX_TRACER_L2_3_RG_AREA_SADDR + 1) + +// Tracer L2 4 registers area - 128B +#define C66XX_TRACER_L2_4_RG_AREA_SADDR 0x01d68000 +#define C66XX_TRACER_L2_4_RG_AREA_EADDR 0x01d6807f +#define C66XX_TRACER_L2_4_RG_AREA_LEN (C66XX_TRACER_L2_4_RG_AREA_EADDR - C66XX_TRACER_L2_4_RG_AREA_SADDR + 1) + +// Tracer L2 5 registers area - 128B +#define C66XX_TRACER_L2_5_RG_AREA_SADDR 0x01d70000 +#define C66XX_TRACER_L2_5_RG_AREA_EADDR 0x01d7007f +#define C66XX_TRACER_L2_5_RG_AREA_LEN (C66XX_TRACER_L2_5_RG_AREA_EADDR - C66XX_TRACER_L2_5_RG_AREA_SADDR + 1) + +// Tracer L2 6 registers area - 128B +#define C66XX_TRACER_L2_6_RG_AREA_SADDR 0x01d78000 +#define C66XX_TRACER_L2_6_RG_AREA_EADDR 0x01d7807f +#define C66XX_TRACER_L2_6_RG_AREA_LEN (C66XX_TRACER_L2_6_RG_AREA_EADDR - C66XX_TRACER_L2_6_RG_AREA_SADDR + 1) + +// Tracer L2 7 registers area - 128B +#define C66XX_TRACER_L2_7_RG_AREA_SADDR 0x01d80000 +#define C66XX_TRACER_L2_7_RG_AREA_EADDR 0x01d8007f +#define C66XX_TRACER_L2_7_RG_AREA_LEN (C66XX_TRACER_L2_7_RG_AREA_EADDR - C66XX_TRACER_L2_7_RG_AREA_SADDR + 1) + +// Telecom Serial Interface Port (TSIP) 0 registers area - 256KB +#define C66XX_TSIP_0_RG_AREA_SADDR 0x01e00000 +#define C66XX_TSIP_0_RG_AREA_EADDR 0x01e3ffff +#define C66XX_TSIP_0_RG_AREA_LEN (C66XX_TSIP_0_RG_AREA_EADDR - C66XX_TSIP_0_RG_AREA_SADDR + 1) + +// Telecom Serial Interface Port (TSIP) 1 registers area - 256KB +#define C66XX_TSIP_1_RG_AREA_SADDR 0x01e80000 +#define C66XX_TSIP_1_RG_AREA_EADDR 0x01ebffff +#define C66XX_TSIP_1_RG_AREA_LEN (C66XX_TSIP_1_RG_AREA_EADDR - C66XX_TSIP_1_RG_AREA_SADDR + 1) + +// Network Coprocessor (NETCP) registers area - 1MB +#define C66XX_NETCP_RG_AREA_SADDR 0x02000000 +#define C66XX_NETCP_RG_AREA_EADDR 0x020fffff +#define C66XX_NETCP_RG_AREA_LEN (C66XX_NETCP_RG_AREA_EADDR - C66XX_NETCP_RG_AREA_SADDR + 1) + +// Timer0 registers area - 128B +#define C66XX_TIMER_0_RG_AREA_SADDR 0x02200000 +#define C66XX_TIMER_0_RG_AREA_EADDR 0x0220007f +#define C66XX_TIMER_0_RG_AREA_LEN (C66XX_TIMER_0_RG_AREA_EADDR - C66XX_TIMER_0_RG_AREA_SADDR + 1) + +// Timer1 registers area - 128B +#define C66XX_TIMER_1_RG_AREA_SADDR 0x02210000 +#define C66XX_TIMER_1_RG_AREA_EADDR 0x0221007f +#define C66XX_TIMER_1_RG_AREA_LEN (C66XX_TIMER_1_RG_AREA_EADDR - C66XX_TIMER_1_RG_AREA_SADDR + 1) + +// Timer2 registers area - 128B +#define C66XX_TIMER_2_RG_AREA_SADDR 0x02220000 +#define C66XX_TIMER_2_RG_AREA_EADDR 0x0222007f +#define C66XX_TIMER_2_RG_AREA_LEN (C66XX_TIMER_2_RG_AREA_EADDR - C66XX_TIMER_2_RG_AREA_SADDR + 1) + +// Timer3 registers area - 128B +#define C66XX_TIMER_3_RG_AREA_SADDR 0x02230000 +#define C66XX_TIMER_3_RG_AREA_EADDR 0x0223007f +#define C66XX_TIMER_3_RG_AREA_LEN (C66XX_TIMER_3_RG_AREA_EADDR - C66XX_TIMER_3_RG_AREA_SADDR + 1) + +// Timer4 registers area - 128B +#define C66XX_TIMER_4_RG_AREA_SADDR 0x02240000 +#define C66XX_TIMER_4_RG_AREA_EADDR 0x0224007f +#define C66XX_TIMER_4_RG_AREA_LEN (C66XX_TIMER_4_RG_AREA_EADDR - C66XX_TIMER_4_RG_AREA_SADDR + 1) + +// Timer5 registers area - 128B +#define C66XX_TIMER_5_RG_AREA_SADDR 0x02250000 +#define C66XX_TIMER_5_RG_AREA_EADDR 0x0225007f +#define C66XX_TIMER_5_RG_AREA_LEN (C66XX_TIMER_5_RG_AREA_EADDR - C66XX_TIMER_5_RG_AREA_SADDR + 1) + +// Timer6 registers area - 128B +#define C66XX_TIMER_6_RG_AREA_SADDR 0x02260000 +#define C66XX_TIMER_6_RG_AREA_EADDR 0x0226007f +#define C66XX_TIMER_6_RG_AREA_LEN (C66XX_TIMER_6_RG_AREA_EADDR - C66XX_TIMER_6_RG_AREA_SADDR + 1) + +// Timer7 registers area - 128B +#define C66XX_TIMER_7_RG_AREA_SADDR 0x02270000 +#define C66XX_TIMER_7_RG_AREA_EADDR 0x0227007f +#define C66XX_TIMER_7_RG_AREA_LEN (C66XX_TIMER_7_RG_AREA_EADDR - C66XX_TIMER_7_RG_AREA_SADDR + 1) + +// Timer8 registers area - 128B +#define C66XX_TIMER_8_RG_AREA_SADDR 0x02280000 +#define C66XX_TIMER_8_RG_AREA_EADDR 0x0228007f +#define C66XX_TIMER_8_RG_AREA_LEN (C66XX_TIMER_8_RG_AREA_EADDR - C66XX_TIMER_8_RG_AREA_SADDR + 1) + +// Timer9 registers area - 128B +#define C66XX_TIMER_9_RG_AREA_SADDR 0x02290000 +#define C66XX_TIMER_9_RG_AREA_EADDR 0x0229007f +#define C66XX_TIMER_9_RG_AREA_LEN (C66XX_TIMER_9_RG_AREA_EADDR - C66XX_TIMER_9_RG_AREA_SADDR + 1) + +// Timer10 registers area - 128B +#define C66XX_TIMER_10_RG_AREA_SADDR 0x022a0000 +#define C66XX_TIMER_10_RG_AREA_EADDR 0x022a007f +#define C66XX_TIMER_10_RG_AREA_LEN (C66XX_TIMER_10_RG_AREA_EADDR - C66XX_TIMER_10_RG_AREA_SADDR + 1) + +// Timer11 registers area - 128B +#define C66XX_TIMER_11_RG_AREA_SADDR 0x022b0000 +#define C66XX_TIMER_11_RG_AREA_EADDR 0x022b007f +#define C66XX_TIMER_11_RG_AREA_LEN (C66XX_TIMER_11_RG_AREA_EADDR - C66XX_TIMER_11_RG_AREA_SADDR + 1) + +// Timer12 registers area - 128B +#define C66XX_TIMER_12_RG_AREA_SADDR 0x022c0000 +#define C66XX_TIMER_12_RG_AREA_EADDR 0x022c007f +#define C66XX_TIMER_12_RG_AREA_LEN (C66XX_TIMER_12_RG_AREA_EADDR - C66XX_TIMER_12_RG_AREA_SADDR + 1) + +// Timer13 registers area - 128B +#define C66XX_TIMER_13_RG_AREA_SADDR 0x022d0000 +#define C66XX_TIMER_13_RG_AREA_EADDR 0x022d007f +#define C66XX_TIMER_13_RG_AREA_LEN (C66XX_TIMER_13_RG_AREA_EADDR - C66XX_TIMER_13_RG_AREA_SADDR + 1) + +// Timer14 registers area - 128B +#define C66XX_TIMER_14_RG_AREA_SADDR 0x022e0000 +#define C66XX_TIMER_14_RG_AREA_EADDR 0x022e007f +#define C66XX_TIMER_14_RG_AREA_LEN (C66XX_TIMER_14_RG_AREA_EADDR - C66XX_TIMER_14_RG_AREA_SADDR + 1) + +// Timer15 registers area - 128B +#define C66XX_TIMER_15_RG_AREA_SADDR 0x022f0000 +#define C66XX_TIMER_15_RG_AREA_EADDR 0x022f007f +#define C66XX_TIMER_15_RG_AREA_LEN (C66XX_TIMER_15_RG_AREA_EADDR - C66XX_TIMER_15_RG_AREA_SADDR + 1) + +// PLL controller registers area - 512B +#define C66XX_PLL_RG_AREA_SADDR 0x02310000 +#define C66XX_PLL_RG_AREA_EADDR 0x023101ff +#define C66XX_PLL_RG_AREA_LEN (C66XX_PLL_RG_AREA_EADDR - C66XX_PLL_RG_AREA_SADDR + 1) + +// GPIO registers area - 256B +#define C66XX_GPIO_RG_AREA_SADDR 0x02320000 +#define C66XX_GPIO_RG_AREA_EADDR 0x023200ff +#define C66XX_GPIO_RG_AREA_LEN (C66XX_GPIO_RG_AREA_EADDR - C66XX_GPIO_RG_AREA_SADDR + 1) + +// SmartReflex registers area - 256B +#define C66XX_SMARTREFLEX_RG_AREA_SADDR 0x02330000 +#define C66XX_SMARTREFLEX_RG_AREA_EADDR 0x023303ff +#define C66XX_SMARTREFLEX_RG_AREA_LEN (C66XX_SMARTREFLEX_RG_AREA_EADDR - C66XX_SMARTREFLEX_RG_AREA_SADDR + 1) + +// Power Sleep Controller (PSC) registers area - 4KB +#define C66XX_PSC_RG_AREA_SADDR 0x02350000 +#define C66XX_PSC_RG_AREA_EADDR 0x02350fff +#define C66XX_PSC_RG_AREA_LEN (C66XX_PSC_RG_AREA_EADDR - C66XX_PSC_RG_AREA_SADDR + 1) + +// Memory Protection Unit (MPU) 0 registers area - 1KB +#define C66XX_MPU_0_RG_AREA_SADDR 0x02360000 +#define C66XX_MPU_0_RG_AREA_EADDR 0x023603ff +#define C66XX_MPU_0_RG_AREA_LEN (C66XX_MPU_0_RG_AREA_EADDR - C66XX_MPU_0_RG_AREA_SADDR + 1) + +// Memory Protection Unit (MPU) 1 registers area - 1KB +#define C66XX_MPU_1_RG_AREA_SADDR 0x02368000 +#define C66XX_MPU_1_RG_AREA_EADDR 0x023683ff +#define C66XX_MPU_1_RG_AREA_LEN (C66XX_MPU_1_RG_AREA_EADDR - C66XX_MPU_1_RG_AREA_SADDR + 1) + +// Memory Protection Unit (MPU) 2 registers area - 1KB +#define C66XX_MPU_2_RG_AREA_SADDR 0x02370000 +#define C66XX_MPU_2_RG_AREA_EADDR 0x023703ff +#define C66XX_MPU_2_RG_AREA_LEN (C66XX_MPU_2_RG_AREA_EADDR - C66XX_MPU_2_RG_AREA_SADDR + 1) + +// Memory Protection Unit (MPU) 3 registers area - 1KB +#define C66XX_MPU_3_RG_AREA_SADDR 0x02378000 +#define C66XX_MPU_3_RG_AREA_EADDR 0x023783ff +#define C66XX_MPU_3_RG_AREA_LEN (C66XX_MPU_3_RG_AREA_EADDR - C66XX_MPU_3_RG_AREA_SADDR + 1) + +// Debug subsystem configuration registers area - 256KB +#define C66XX_DEBUG_CFG_RG_AREA_SADDR 0x02400000 +#define C66XX_DEBUG_CFG_RG_AREA_EADDR 0x0243ffff +#define C66XX_DEBUG_CFG_RG_AREA_LEN (C66XX_DEBUG_CFG_RG_AREA_EADDR - C66XX_DEBUG_CFG_RG_AREA_SADDR + 1) + +// DSP trace formatter 0 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_SADDR 0x02440000 +#define C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_EADDR 0x02443fff +#define C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_SADDR + 1) + +// DSP trace formatter 1 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_SADDR 0x02450000 +#define C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_EADDR 0x02453fff +#define C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_SADDR + 1) + +// DSP trace formatter 2 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_SADDR 0x02460000 +#define C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_EADDR 0x02463fff +#define C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_SADDR + 1) + +// DSP trace formatter 3 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_SADDR 0x02470000 +#define C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_EADDR 0x02473fff +#define C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_SADDR + 1) + +// DSP trace formatter 4 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_SADDR 0x02480000 +#define C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_EADDR 0x02483fff +#define C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_SADDR + 1) + +// DSP trace formatter 5 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_SADDR 0x02490000 +#define C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_EADDR 0x02493fff +#define C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_SADDR + 1) + +// DSP trace formatter 6 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_SADDR 0x024a0000 +#define C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_EADDR 0x024a3fff +#define C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_SADDR + 1) + +// DSP trace formatter 7 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_SADDR 0x024b0000 +#define C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_EADDR 0x024b3fff +#define C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_SADDR + 1) + +// I2C registers area - 128B +#define C66XX_I2C_RG_AREA_SADDR 0x02530000 +#define C66XX_I2C_RG_AREA_EADDR 0x0253007f +#define C66XX_I2C_RG_AREA_LEN (C66XX_I2C_RG_AREA_EADDR - C66XX_I2C_RG_AREA_SADDR + 1) + +// UART registers area - 64B +#define C66XX_UART_RG_AREA_SADDR 0x02540000 +#define C66XX_UART_RG_AREA_EADDR 0x0254003f +#define C66XX_UART_RG_AREA_LEN (C66XX_UART_RG_AREA_EADDR - C66XX_UART_RG_AREA_SADDR + 1) + +// Chip Interrupt Controller (CIC) 0 registers area - 8KB +#define C66XX_CIC_0_RG_AREA_SADDR 0x02600000 +#define C66XX_CIC_0_RG_AREA_EADDR 0x02601fff +#define C66XX_CIC_0_RG_AREA_LEN (C66XX_CIC_0_RG_AREA_EADDR - C66XX_CIC_0_RG_AREA_SADDR + 1) + +// Chip Interrupt Controller (CIC) 1 registers area - 8KB +#define C66XX_CIC_1_RG_AREA_SADDR 0x02604000 +#define C66XX_CIC_1_RG_AREA_EADDR 0x02605fff +#define C66XX_CIC_1_RG_AREA_LEN (C66XX_CIC_1_RG_AREA_EADDR - C66XX_CIC_1_RG_AREA_SADDR + 1) + +// Chip Interrupt Controller (CIC) 2 registers area - 8KB +#define C66XX_CIC_2_RG_AREA_SADDR 0x02608000 +#define C66XX_CIC_2_RG_AREA_EADDR 0x02609fff +#define C66XX_CIC_2_RG_AREA_LEN (C66XX_CIC_2_RG_AREA_EADDR - C66XX_CIC_2_RG_AREA_SADDR + 1) + +// Chip Interrupt Controller (CIC) 3 registers area - 8KB +#define C66XX_CIC_3_RG_AREA_SADDR 0x0260c000 +#define C66XX_CIC_3_RG_AREA_EADDR 0x0260dfff +#define C66XX_CIC_3_RG_AREA_LEN (C66XX_CIC_3_RG_AREA_EADDR - C66XX_CIC_3_RG_AREA_SADDR + 1) + +// Device State Control registers area - 2KB +#define C66XX_BOOTCFG_RG_AREA_SADDR 0x02620000 +#define C66XX_BOOTCFG_RG_AREA_EADDR 0x026207ff +#define C66XX_BOOTCFG_RG_AREA_LEN (C66XX_BOOTCFG_RG_AREA_EADDR - C66XX_BOOTCFG_RG_AREA_SADDR + 1) + +// Semaphore (SEM) registers area - 2KB +#define C66XX_SEM_RG_AREA_SADDR 0x02640000 +#define C66XX_SEM_RG_AREA_EADDR 0x026407ff +#define C66XX_SEM_RG_AREA_LEN (C66XX_SEM_RG_AREA_EADDR - C66XX_SEM_RG_AREA_SADDR + 1) + +// EDMA3 Channel Controller (EDMA3CC) 0 registers area - 32KB +#define C66XX_EDMA3CC_0_RG_AREA_SADDR 0x02700000 +#define C66XX_EDMA3CC_0_RG_AREA_EADDR 0x02707fff +#define C66XX_EDMA3CC_0_RG_AREA_LEN (C66XX_EDMA3CC_0_RG_AREA_EADDR - C66XX_EDMA3CC_0_RG_AREA_SADDR + 1) + +// EDMA3 Channel Controller (EDMA3CC) 1 registers area - 32KB +#define C66XX_EDMA3CC_1_RG_AREA_SADDR 0x02720000 +#define C66XX_EDMA3CC_1_RG_AREA_EADDR 0x02727fff +#define C66XX_EDMA3CC_1_RG_AREA_LEN (C66XX_EDMA3CC_1_RG_AREA_EADDR - C66XX_EDMA3CC_1_RG_AREA_SADDR + 1) + +// EDMA3 Channel Controller (EDMA3CC) 2 registers area - 32KB +#define C66XX_EDMA3CC_2_RG_AREA_SADDR 0x02740000 +#define C66XX_EDMA3CC_2_RG_AREA_EADDR 0x02747fff +#define C66XX_EDMA3CC_2_RG_AREA_LEN (C66XX_EDMA3CC_2_RG_AREA_EADDR - C66XX_EDMA3CC_2_RG_AREA_SADDR + 1) + +// EDMA3CC0 Transfer Controller (EDMA3TC) 0 registers area - 1KB +#define C66XX_EDMA3CC_0_TC_0_RG_AREA_SADDR 0x02760000 +#define C66XX_EDMA3CC_0_TC_0_RG_AREA_EADDR 0x027603ff +#define C66XX_EDMA3CC_0_TC_0_RG_AREA_LEN (C66XX_EDMA3CC_0_TC_0_RG_AREA_EADDR - C66XX_EDMA3CC_0_TC_0_RG_AREA_SADDR + 1) + +// EDMA3CC0 Transfer Controller (EDMA3TC) 1 registers area - 1KB +#define C66XX_EDMA3CC_0_TC_1_RG_AREA_SADDR 0x02768000 +#define C66XX_EDMA3CC_0_TC_1_RG_AREA_EADDR 0x027683ff +#define C66XX_EDMA3CC_0_TC_1_RG_AREA_LEN (C66XX_EDMA3CC_0_TC_1_RG_AREA_EADDR - C66XX_EDMA3CC_0_TC_1_RG_AREA_SADDR + 1) + +// EDMA3CC1 Transfer Controller (EDMA3TC) 0 registers area - 1KB +#define C66XX_EDMA3CC_1_TC_0_RG_AREA_SADDR 0x02770000 +#define C66XX_EDMA3CC_1_TC_0_RG_AREA_EADDR 0x027703ff +#define C66XX_EDMA3CC_1_TC_0_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_0_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_0_RG_AREA_SADDR + 1) + +// EDMA3CC1 Transfer Controller (EDMA3TC) 1 registers area - 1KB +#define C66XX_EDMA3CC_1_TC_1_RG_AREA_SADDR 0x02778000 +#define C66XX_EDMA3CC_1_TC_1_RG_AREA_EADDR 0x027783ff +#define C66XX_EDMA3CC_1_TC_1_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_1_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_1_RG_AREA_SADDR + 1) + +// EDMA3CC1 Transfer Controller (EDMA3TC) 2 registers area - 1KB +#define C66XX_EDMA3CC_1_TC_2_RG_AREA_SADDR 0x02780000 +#define C66XX_EDMA3CC_1_TC_2_RG_AREA_EADDR 0x027803ff +#define C66XX_EDMA3CC_1_TC_2_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_2_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_2_RG_AREA_SADDR + 1) + +// EDMA3CC1 Transfer Controller (EDMA3TC) 3 registers area - 1KB +#define C66XX_EDMA3CC_1_TC_3_RG_AREA_SADDR 0x02788000 +#define C66XX_EDMA3CC_1_TC_3_RG_AREA_EADDR 0x027883ff +#define C66XX_EDMA3CC_1_TC_3_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_3_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_3_RG_AREA_SADDR + 1) + +// EDMA3CC2 Transfer Controller (EDMA3TC) 0 registers area - 1KB +#define C66XX_EDMA3CC_2_TC_0_RG_AREA_SADDR 0x02790000 +#define C66XX_EDMA3CC_2_TC_0_RG_AREA_EADDR 0x027903ff +#define C66XX_EDMA3CC_2_TC_0_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_0_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_0_RG_AREA_SADDR + 1) + +// EDMA3CC2 Transfer Controller (EDMA3TC) 1 registers area - 1KB +#define C66XX_EDMA3CC_2_TC_1_RG_AREA_SADDR 0x02798000 +#define C66XX_EDMA3CC_2_TC_1_RG_AREA_EADDR 0x027983ff +#define C66XX_EDMA3CC_2_TC_1_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_1_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_1_RG_AREA_SADDR + 1) + +// EDMA3CC2 Transfer Controller (EDMA3TC) 2 registers area - 1KB +#define C66XX_EDMA3CC_2_TC_2_RG_AREA_SADDR 0x027a0000 +#define C66XX_EDMA3CC_2_TC_2_RG_AREA_EADDR 0x027a03ff +#define C66XX_EDMA3CC_2_TC_2_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_2_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_2_RG_AREA_SADDR + 1) + +// EDMA3CC2 Transfer Controller (EDMA3TC) 3 registers area - 1KB +#define C66XX_EDMA3CC_2_TC_3_RG_AREA_SADDR 0x027a8000 +#define C66XX_EDMA3CC_2_TC_3_RG_AREA_EADDR 0x027a83ff +#define C66XX_EDMA3CC_2_TC_3_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_3_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_3_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac0 registers area - 4KB +#define C66XX_TETB_0_RG_AREA_SADDR 0x027d0000 +#define C66XX_TETB_0_RG_AREA_EADDR 0x027d0fff +#define C66XX_TETB_0_RG_AREA_LEN (C66XX_TETB_0_RG_AREA_EADDR - C66XX_TETB_0_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac1 registers area - 4KB +#define C66XX_TETB_1_RG_AREA_SADDR 0x027e0000 +#define C66XX_TETB_1_RG_AREA_EADDR 0x027e0fff +#define C66XX_TETB_1_RG_AREA_LEN (C66XX_TETB_1_RG_AREA_EADDR - C66XX_TETB_1_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac2 registers area - 4KB +#define C66XX_TETB_2_RG_AREA_SADDR 0x027f0000 +#define C66XX_TETB_2_RG_AREA_EADDR 0x027f0fff +#define C66XX_TETB_2_RG_AREA_LEN (C66XX_TETB_2_RG_AREA_EADDR - C66XX_TETB_2_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac3 registers area - 4KB +#define C66XX_TETB_3_RG_AREA_SADDR 0x02800000 +#define C66XX_TETB_3_RG_AREA_EADDR 0x02800fff +#define C66XX_TETB_3_RG_AREA_LEN (C66XX_TETB_3_RG_AREA_EADDR - C66XX_TETB_3_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac4 registers area - 4KB +#define C66XX_TETB_4_RG_AREA_SADDR 0x02810000 +#define C66XX_TETB_4_RG_AREA_EADDR 0x02810fff +#define C66XX_TETB_4_RG_AREA_LEN (C66XX_TETB_4_RG_AREA_EADDR - C66XX_TETB_4_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac5 registers area - 4KB +#define C66XX_TETB_5_RG_AREA_SADDR 0x02820000 +#define C66XX_TETB_5_RG_AREA_EADDR 0x02820fff +#define C66XX_TETB_5_RG_AREA_LEN (C66XX_TETB_5_RG_AREA_EADDR - C66XX_TETB_5_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac6 registers area - 4KB +#define C66XX_TETB_6_RG_AREA_SADDR 0x02830000 +#define C66XX_TETB_6_RG_AREA_EADDR 0x02830fff +#define C66XX_TETB_6_RG_AREA_LEN (C66XX_TETB_6_RG_AREA_EADDR - C66XX_TETB_6_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac7 registers area - 4KB +#define C66XX_TETB_7_RG_AREA_SADDR 0x02840000 +#define C66XX_TETB_7_RG_AREA_EADDR 0x02840fff +#define C66XX_TETB_7_RG_AREA_LEN (C66XX_TETB_7_RG_AREA_EADDR - C66XX_TETB_7_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) system registers area - 32KB +#define C66XX_TETB_SYSTEM_RG_AREA_SADDR 0x02850000 +#define C66XX_TETB_SYSTEM_RG_AREA_EADDR 0x02857fff +#define C66XX_TETB_SYSTEM_RG_AREA_LEN (C66XX_TETB_SYSTEM_RG_AREA_EADDR - C66XX_TETB_SYSTEM_RG_AREA_SADDR + 1) + +// Serial RapidIO (SRIO) configuration registers area - 132KB +#define C66XX_SRIO_RG_AREA_SADDR 0x02900000 +#define C66XX_SRIO_RG_AREA_EADDR 0x02920fff +#define C66XX_SRIO_RG_AREA_LEN (C66XX_SRIO_RG_AREA_EADDR - C66XX_SRIO_RG_AREA_SADDR + 1) + +// Queue manager subsystem (QMSS) configuration registers area - 2MB +#define C66XX_QMSS_RG_AREA_SADDR 0x02a00000 +#define C66XX_QMSS_RG_AREA_EADDR 0x02bfffff +#define C66XX_QMSS_RG_AREA_LEN (C66XX_QMSS_RG_AREA_EADDR - C66XX_QMSS_RG_AREA_SADDR + 1) + +// Extended memory controller (XMC) configuration registers area - 64KB +#define C66XX_XMC_RG_AREA_SADDR 0x08000000 +#define C66XX_XMC_RG_AREA_EADDR 0x0800ffff +#define C66XX_XMC_RG_AREA_LEN (C66XX_XMC_RG_AREA_EADDR - C66XX_XMC_RG_AREA_SADDR + 1) + +// Multicore shared memory controller (MSMC) configuration registers area - 1MB +#define C66XX_MSMC_RG_AREA_SADDR 0x0bc00000 +#define C66XX_MSMC_RG_AREA_EADDR 0x0bcfffff +#define C66XX_MSMC_RG_AREA_LEN (C66XX_MSMC_RG_AREA_EADDR - C66XX_MSMC_RG_AREA_SADDR + 1) + +// Multicore shared memory (MSM) area - 4MB +#define C66XX_MSM_SRAM_AREA_SADDR 0x0c000000 +#define C66XX_MSM_SRAM_AREA_EADDR 0x0c3fffff +#define C66XX_MSM_SRAM_AREA_LEN (C66XX_MSM_SRAM_AREA_EADDR - C66XX_MSM_SRAM_AREA_SADDR + 1) + +// CorePac0 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_0_L2_SRAM_SADDR 0x10800000 +#define C66XX_DSP_0_L2_SRAM_EADDR 0x1087ffff +#define C66XX_DSP_0_L2_SRAM_LEN (C66XX_DSP_0_L2_SRAM_EADDR - C66XX_DSP_0_L2_SRAM_SADDR + 1) + +// CorePac0 L1P SRAM - 32KB +#define C66XX_DSP_0_L1P_SRAM_SADDR 0x10e00000 +#define C66XX_DSP_0_L1P_SRAM_EADDR 0x10e07fff +#define C66XX_DSP_0_L1P_SRAM_LEN (C66XX_DSP_0_L1P_SRAM_EADDR - C66XX_DSP_0_L1P_SRAM_SADDR + 1) + +// CorePac0 L1D SRAM - 32KB +#define C66XX_DSP_0_L1D_SRAM_SADDR 0x10f00000 +#define C66XX_DSP_0_L1D_SRAM_EADDR 0x10f07fff +#define C66XX_DSP_0_L1D_SRAM_LEN (C66XX_DSP_0_L1D_SRAM_EADDR - C66XX_DSP_0_L1D_SRAM_SADDR + 1) + +// CorePac1 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_1_L2_SRAM_SADDR 0x11800000 +#define C66XX_DSP_1_L2_SRAM_EADDR 0x1187ffff +#define C66XX_DSP_1_L2_SRAM_LEN (C66XX_DSP_1_L2_SRAM_EADDR - C66XX_DSP_1_L2_SRAM_SADDR + 1) + +// CorePac1 L1P SRAM - 32KB +#define C66XX_DSP_1_L1P_SRAM_SADDR 0x11e00000 +#define C66XX_DSP_1_L1P_SRAM_EADDR 0x11e07fff +#define C66XX_DSP_1_L1P_SRAM_LEN (C66XX_DSP_1_L1P_SRAM_EADDR - C66XX_DSP_1_L1P_SRAM_SADDR + 1) + +// CorePac1 L1D SRAM - 32KB +#define C66XX_DSP_1_L1D_SRAM_SADDR 0x11f00000 +#define C66XX_DSP_1_L1D_SRAM_EADDR 0x11f07fff +#define C66XX_DSP_1_L1D_SRAM_LEN (C66XX_DSP_1_L1D_SRAM_EADDR - C66XX_DSP_1_L1D_SRAM_SADDR + 1) + +// CorePac2 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_2_L2_SRAM_SADDR 0x12800000 +#define C66XX_DSP_2_L2_SRAM_EADDR 0x1287ffff +#define C66XX_DSP_2_L2_SRAM_LEN (C66XX_DSP_2_L2_SRAM_EADDR - C66XX_DSP_2_L2_SRAM_SADDR + 1) + +// CorePac2 L1P SRAM - 32KB +#define C66XX_DSP_2_L1P_SRAM_SADDR 0x12e00000 +#define C66XX_DSP_2_L1P_SRAM_EADDR 0x12e07fff +#define C66XX_DSP_2_L1P_SRAM_LEN (C66XX_DSP_2_L1P_SRAM_EADDR - C66XX_DSP_2_L1P_SRAM_SADDR + 1) + +// CorePac2 L1D SRAM - 32KB +#define C66XX_DSP_2_L1D_SRAM_SADDR 0x12f00000 +#define C66XX_DSP_2_L1D_SRAM_EADDR 0x12f07fff +#define C66XX_DSP_2_L1D_SRAM_LEN (C66XX_DSP_2_L1D_SRAM_EADDR - C66XX_DSP_2_L1D_SRAM_SADDR + 1) + +// CorePac3 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_3_L2_SRAM_SADDR 0x13800000 +#define C66XX_DSP_3_L2_SRAM_EADDR 0x1387ffff +#define C66XX_DSP_3_L2_SRAM_LEN (C66XX_DSP_3_L2_SRAM_EADDR - C66XX_DSP_3_L2_SRAM_SADDR + 1) + +// CorePac3 L1P SRAM - 32KB +#define C66XX_DSP_3_L1P_SRAM_SADDR 0x13e00000 +#define C66XX_DSP_3_L1P_SRAM_EADDR 0x13e07fff +#define C66XX_DSP_3_L1P_SRAM_LEN (C66XX_DSP_3_L1P_SRAM_EADDR - C66XX_DSP_3_L1P_SRAM_SADDR + 1) + +// CorePac3 L1D SRAM - 32KB +#define C66XX_DSP_3_L1D_SRAM_SADDR 0x13f00000 +#define C66XX_DSP_3_L1D_SRAM_EADDR 0x13f07fff +#define C66XX_DSP_3_L1D_SRAM_LEN (C66XX_DSP_3_L1D_SRAM_EADDR - C66XX_DSP_3_L1D_SRAM_SADDR + 1) + +// CorePac4 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_4_L2_SRAM_SADDR 0x14800000 +#define C66XX_DSP_4_L2_SRAM_EADDR 0x1487ffff +#define C66XX_DSP_4_L2_SRAM_LEN (C66XX_DSP_4_L2_SRAM_EADDR - C66XX_DSP_4_L2_SRAM_SADDR + 1) + +// CorePac4 L1P SRAM - 32KB +#define C66XX_DSP_4_L1P_SRAM_SADDR 0x14e00000 +#define C66XX_DSP_4_L1P_SRAM_EADDR 0x14e07fff +#define C66XX_DSP_4_L1P_SRAM_LEN (C66XX_DSP_4_L1P_SRAM_EADDR - C66XX_DSP_4_L1P_SRAM_SADDR + 1) + +// CorePac4 L1D SRAM - 32KB +#define C66XX_DSP_4_L1D_SRAM_SADDR 0x14f00000 +#define C66XX_DSP_4_L1D_SRAM_EADDR 0x14f07fff +#define C66XX_DSP_4_L1D_SRAM_LEN (C66XX_DSP_4_L1D_SRAM_EADDR - C66XX_DSP_4_L1D_SRAM_SADDR + 1) + +// CorePac5 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_5_L2_SRAM_SADDR 0x15800000 +#define C66XX_DSP_5_L2_SRAM_EADDR 0x1587ffff +#define C66XX_DSP_5_L2_SRAM_LEN (C66XX_DSP_5_L2_SRAM_EADDR - C66XX_DSP_5_L2_SRAM_SADDR + 1) + +// CorePac5 L1P SRAM - 32KB +#define C66XX_DSP_5_L1P_SRAM_SADDR 0x15e00000 +#define C66XX_DSP_5_L1P_SRAM_EADDR 0x15e07fff +#define C66XX_DSP_5_L1P_SRAM_LEN (C66XX_DSP_5_L1P_SRAM_EADDR - C66XX_DSP_5_L1P_SRAM_SADDR + 1) + +// CorePac5 L1D SRAM - 32KB +#define C66XX_DSP_5_L1D_SRAM_SADDR 0x15f00000 +#define C66XX_DSP_5_L1D_SRAM_EADDR 0x15f07fff +#define C66XX_DSP_5_L1D_SRAM_LEN (C66XX_DSP_5_L1D_SRAM_EADDR - C66XX_DSP_5_L1D_SRAM_SADDR + 1) + +// CorePac6 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_6_L2_SRAM_SADDR 0x16800000 +#define C66XX_DSP_6_L2_SRAM_EADDR 0x1687ffff +#define C66XX_DSP_6_L2_SRAM_LEN (C66XX_DSP_6_L2_SRAM_EADDR - C66XX_DSP_6_L2_SRAM_SADDR + 1) + +// CorePac6 L1P SRAM - 32KB +#define C66XX_DSP_6_L1P_SRAM_SADDR 0x16e00000 +#define C66XX_DSP_6_L1P_SRAM_EADDR 0x16e07fff +#define C66XX_DSP_6_L1P_SRAM_LEN (C66XX_DSP_6_L1P_SRAM_EADDR - C66XX_DSP_6_L1P_SRAM_SADDR + 1) + +// CorePac6 L1D SRAM - 32KB +#define C66XX_DSP_6_L1D_SRAM_SADDR 0x16f00000 +#define C66XX_DSP_6_L1D_SRAM_EADDR 0x16f07fff +#define C66XX_DSP_6_L1D_SRAM_LEN (C66XX_DSP_6_L1D_SRAM_EADDR - C66XX_DSP_6_L1D_SRAM_SADDR + 1) + +// CorePac7 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_7_L2_SRAM_SADDR 0x17800000 +#define C66XX_DSP_7_L2_SRAM_EADDR 0x1787ffff +#define C66XX_DSP_7_L2_SRAM_LEN (C66XX_DSP_7_L2_SRAM_EADDR - C66XX_DSP_7_L2_SRAM_SADDR + 1) + +// CorePac7 L1P SRAM - 32KB +#define C66XX_DSP_7_L1P_SRAM_SADDR 0x17e00000 +#define C66XX_DSP_7_L1P_SRAM_EADDR 0x17e07fff +#define C66XX_DSP_7_L1P_SRAM_LEN (C66XX_DSP_7_L1P_SRAM_EADDR - C66XX_DSP_7_L1P_SRAM_SADDR + 1) + +// CorePac7 L1D SRAM - 32KB +#define C66XX_DSP_7_L1D_SRAM_SADDR 0x17f00000 +#define C66XX_DSP_7_L1D_SRAM_EADDR 0x17f07fff +#define C66XX_DSP_7_L1D_SRAM_LEN (C66XX_DSP_7_L1D_SRAM_EADDR - C66XX_DSP_7_L1D_SRAM_SADDR + 1) + +// System trace manager (STM) configuration registers area - 1MB +#define C66XX_STM_RG_AREA_SADDR 0x20000000 +#define C66XX_STM_RG_AREA_EADDR 0x200fffff +#define C66XX_STM_RG_AREA_LEN (C66XX_STM_RG_AREA_EADDR - C66XX_STM_RG_AREA_SADDR + 1) + +// Boot ROM - 128KB +#define C66XX_BOOT_ROM_SADDR 0x20b00000 +#define C66XX_BOOT_ROM_EADDR 0x20b1ffff +#define C66XX_BOOT_ROM_LEN (C66XX_BOOT_ROM_EADDR - C66XX_BOOT_ROM_SADDR + 1) + +// SPI configuration registers area - 512B +#define C66XX_SPI_RG_AREA_SADDR 0x20bf0000 +#define C66XX_SPI_RG_AREA_EADDR 0x20bf01ff +#define C66XX_SPI_RG_AREA_LEN (C66XX_SPI_RG_AREA_EADDR - C66XX_SPI_RG_AREA_SADDR + 1) + +// EMIF16 configuration registers area - 256B +#define C66XX_EMIF16_RG_AREA_SADDR 0x20c00000 +#define C66XX_EMIF16_RG_AREA_EADDR 0x20c000ff +#define C66XX_EMIF16_RG_AREA_LEN (C66XX_EMIF16_RG_AREA_EADDR - C66XX_EMIF16_RG_AREA_SADDR + 1) + +// DDR3 EMIF configuration registers area - 512B +#define C66XX_DDR3_EMIF_RG_AREA_SADDR 0x21000000 +#define C66XX_DDR3_EMIF_RG_AREA_EADDR 0x210001ff +#define C66XX_DDR3_EMIF_RG_AREA_LEN (C66XX_DDR3_EMIF_RG_AREA_EADDR - C66XX_DDR3_EMIF_RG_AREA_SADDR + 1) + +// HyperLink configuration registers area - 256B +#define C66XX_HYPERLINK_RG_AREA_SADDR 0x21400000 +#define C66XX_HYPERLINK_RG_AREA_EADDR 0x214000ff +#define C66XX_HYPERLINK_RG_AREA_LEN (C66XX_HYPERLINK_RG_AREA_EADDR - C66XX_HYPERLINK_RG_AREA_SADDR + 1) + +// PCIe configuration registers area - 32KB +#define C66XX_PCIE_RG_AREA_SADDR 0x21800000 +#define C66XX_PCIE_RG_AREA_EADDR 0x21807fff +#define C66XX_PCIE_RG_AREA_LEN (C66XX_PCIE_RG_AREA_EADDR - C66XX_PCIE_RG_AREA_SADDR + 1) + +// Queue manager subsystem (QMSS) data area - 2MB +#define C66XX_QMSS_DATA_AREA_SADDR 0x34000000 +#define C66XX_QMSS_DATA_AREA_EADDR 0x341fffff +#define C66XX_QMSS_DATA_AREA_LEN (C66XX_QMSS_DATA_AREA_EADDR - C66XX_QMSS_DATA_AREA_SADDR + 1) + +// HyperLink data area - 256MB +#define C66XX_HYPERLINK_DATA_AREA_SADDR 0x40000000 +#define C66XX_HYPERLINK_DATA_AREA_EADDR 0x4fffffff +#define C66XX_HYPERLINK_DATA_AREA_LEN (C66XX_HYPERLINK_DATA_AREA_EADDR - C66XX_HYPERLINK_DATA_AREA_SADDR + 1) + +// PCIe data area - 256MB +#define C66XX_PCIE_DATA_AREA_SADDR 0x60000000 +#define C66XX_PCIE_DATA_AREA_EADDR 0x6fffffff +#define C66XX_PCIE_DATA_AREA_LEN (C66XX_PCIE_DATA_AREA_EADDR - C66XX_PCIE_DATA_AREA_SADDR + 1) + +// EMIF16 CE0 area - 64MB +#define C66XX_EMIF16_CE0_AREA_SADDR 0x70000000 +#define C66XX_EMIF16_CE0_AREA_EADDR 0x73ffffff +#define C66XX_EMIF16_CE0_AREA_LEN (C66XX_EMIF16_CE0_AREA_EADDR - C66XX_EMIF16_CE0_AREA_SADDR + 1) + +// EMIF16 CE1 area - 64MB +#define C66XX_EMIF16_CE1_AREA_SADDR 0x74000000 +#define C66XX_EMIF16_CE1_AREA_EADDR 0x77ffffff +#define C66XX_EMIF16_CE1_AREA_LEN (C66XX_EMIF16_CE1_AREA_EADDR - C66XX_EMIF16_CE1_AREA_SADDR + 1) + +// EMIF16 CE2 area - 64MB +#define C66XX_EMIF16_CE2_AREA_SADDR 0x78000000 +#define C66XX_EMIF16_CE2_AREA_EADDR 0x7bffffff +#define C66XX_EMIF16_CE2_AREA_LEN (C66XX_EMIF16_CE2_AREA_EADDR - C66XX_EMIF16_CE2_AREA_SADDR + 1) + +// EMIF16 CE3 area - 64MB +#define C66XX_EMIF16_CE3_AREA_SADDR 0x7c000000 +#define C66XX_EMIF16_CE3_AREA_EADDR 0x7fffffff +#define C66XX_EMIF16_CE3_AREA_LEN (C66XX_EMIF16_CE3_AREA_EADDR - C66XX_EMIF16_CE3_AREA_SADDR + 1) + +// DDR3 EMIF data area - 2GB +#define C66XX_DDR3_AREA_SADDR 0x80000000 +#define C66XX_DDR3_AREA_EADDR 0xffffffff +#define C66XX_DDR3_AREA_LEN (C66XX_DDR3_AREA_EADDR - C66XX_DDR3_AREA_SADDR + 1) + +//============================================================================= +#endif /* __C66XX_SELECT_C6678_DSP__ */ + + + +//============================================================================= +//============ DSP core registers ============================================= +//============================================================================= +// DSP CorePack revision register - r-only +#define C66XX_CORE_MM_REVID_RG_ADDR 0x01812000 + +//------------ DSP CorePack revision register defs ---------------------------- +#define C66XX_CORE_MM_REVID_VERSION_BITMASK 0xffff0000 +#define C66XX_CORE_MM_REVID_VERSION_BITSHIFT 16 +#define C66XX_CORE_MM_REVID_REVISION_BITMASK 0x0000ffff +#define C66XX_CORE_MM_REVID_REVISION_BITSHIFT 0 + +#define C66XX_CORE_MM_REVID_VERSION_C6678 0x0008 +#define C66XX_CORE_MM_REVID_REVISION_1_0 0x0 +#define C66XX_CORE_MM_REVID_REVISION_2_0 0x1 + + +// DSP interrupt controller registers addresses + +// DSP Event Flag register 0 - r-only +#define C66XX_CORE_EVTFLAG0_RG_ADDR 0x01800000 +// DSP Event Flag register 1 - r-only +#define C66XX_CORE_EVTFLAG1_RG_ADDR 0x01800004 +// DSP Event Flag register 2 - r-only +#define C66XX_CORE_EVTFLAG2_RG_ADDR 0x01800008 +// DSP Event Flag register 3 - r-only +#define C66XX_CORE_EVTFLAG3_RG_ADDR 0x0180000c +// DSP Event Set register 0 - r/w +#define C66XX_CORE_EVTSET0_RG_ADDR 0x01800020 +// DSP Event Set register 1 - r/w +#define C66XX_CORE_EVTSET1_RG_ADDR 0x01800024 +// DSP Event Set register 2 - r/w +#define C66XX_CORE_EVTSET2_RG_ADDR 0x01800028 +// DSP Event Set register 3 - r/w +#define C66XX_CORE_EVTSET3_RG_ADDR 0x0180002c +// DSP Event Clear register 0 - r/w +#define C66XX_CORE_EVTCLR0_RG_ADDR 0x01800040 +// DSP Event Clear register 1 - r/w +#define C66XX_CORE_EVTCLR1_RG_ADDR 0x01800044 +// DSP Event Clear register 2 - r/w +#define C66XX_CORE_EVTCLR2_RG_ADDR 0x01800048 +// DSP Event Clear register 3 - r/w +#define C66XX_CORE_EVTCLR3_RG_ADDR 0x0180004c +// DSP Event Mask register 0 - r/w +#define C66XX_CORE_EVTMASK0_RG_ADDR 0x01800080 +// DSP Event Mask register 1 - r/w +#define C66XX_CORE_EVTMASK1_RG_ADDR 0x01800084 +// DSP Event Mask register 2 - r/w +#define C66XX_CORE_EVTMASK2_RG_ADDR 0x01800088 +// DSP Event Mask register 3 - r/w +#define C66XX_CORE_EVTMASK3_RG_ADDR 0x0180008c + +// DSP Event Flag registers base address +#define C66XX_CORE_EVTFLAG_RG_BADDR 0x01800000 +// DSP Event Flag registers offset +#define C66XX_CORE_EVTFLAG_RG_OFFSET 0x00000004 + +// DSP Event Set registers base address +#define C66XX_CORE_EVTSET_RG_BADDR 0x01800020 +// DSP Event Set registers offset +#define C66XX_CORE_EVTSET_RG_OFFSET 0x00000004 + +// DSP Event Clear registers base address +#define C66XX_CORE_EVTCLR_RG_BADDR 0x01800040 +// DSP Event Clear registers offset +#define C66XX_CORE_EVTCLR_RG_OFFSET 0x00000004 + +// DSP Event Mask registers base address +#define C66XX_CORE_EVTMASK_RG_BADDR 0x01800080 +// DSP Event Mask registers offset +#define C66XX_CORE_EVTMASK_RG_OFFSET 0x00000004 + +//============================================================================= + + + +//============================================================================= +//============ PLL controller registers ======================================= +//============================================================================= +// PLL control register - r/w +#define C66XX_PLL_PLLCTL_RG_OFFSET 0x100 +// PLL secondary control register - r/w +#define C66XX_PLL_SECCTL_RG_OFFSET 0x108 +// PLL multiplier control register - r/w +#define C66XX_PLL_PLLM_RG_OFFSET 0x110 +// PLL controller divider 1 register - r/w +#define C66XX_PLL_PLLDIV1_RG_OFFSET 0x118 +// PLL controller divider 2 register - r/w +#define C66XX_PLL_PLLDIV2_RG_OFFSET 0x11c +// PLL controller divider 3 register - r/w +#define C66XX_PLL_PLLDIV3_RG_OFFSET 0x120 +// PLL controller command register - r/w +#define C66XX_PLL_PLLCMD_RG_OFFSET 0x138 +// PLL controller status register - r/w +#define C66XX_PLL_PLLSTAT_RG_OFFSET 0x13c +// PLL controller clock align control register - r/w +#define C66XX_PLL_ALNCTL_RG_OFFSET 0x140 +// PLL controller divider ratio change status register - r/w +#define C66XX_PLL_DCHANGE_RG_OFFSET 0x144 +// SYSCLK status register - r-only +#define C66XX_PLL_SYSTAT_RG_OFFSET 0x150 +// PLL controller divider 4 register - r/w +#define C66XX_PLL_PLLDIV4_RG_OFFSET 0x160 +// PLL controller divider 5 register - r/w +#define C66XX_PLL_PLLDIV5_RG_OFFSET 0x164 +// PLL controller divider 6 register - r/w +#define C66XX_PLL_PLLDIV6_RG_OFFSET 0x168 +// PLL controller divider 7 register - r/w +#define C66XX_PLL_PLLDIV7_RG_OFFSET 0x16c +// PLL controller divider 8 register - r/w +#define C66XX_PLL_PLLDIV8_RG_OFFSET 0x170 +// PLL controller divider 9 register - r/w +#define C66XX_PLL_PLLDIV9_RG_OFFSET 0x174 +// PLL controller divider 10 register - r/w +#define C66XX_PLL_PLLDIV10_RG_OFFSET 0x178 +// PLL controller divider 11 register - r/w +#define C66XX_PLL_PLLDIV11_RG_OFFSET 0x17c +// PLL controller divider 12 register - r/w +#define C66XX_PLL_PLLDIV12_RG_OFFSET 0x180 +// PLL controller divider 13 register - r/w +#define C66XX_PLL_PLLDIV13_RG_OFFSET 0x184 +// PLL controller divider 14 register - r/w +#define C66XX_PLL_PLLDIV14_RG_OFFSET 0x188 +// PLL controller divider 15 register - r/w +#define C66XX_PLL_PLLDIV15_RG_OFFSET 0x18c +// PLL controller divider 16 register - r/w +#define C66XX_PLL_PLLDIV16_RG_OFFSET 0x190 + +#define C66XX_PLL_PLLCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLCTL_RG_OFFSET) +#define C66XX_PLL_SECCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_SECCTL_RG_OFFSET) +#define C66XX_PLL_PLLM_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLM_RG_OFFSET) +#define C66XX_PLL_PLLDIV1_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV1_RG_OFFSET) +#define C66XX_PLL_PLLDIV2_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV2_RG_OFFSET) +#define C66XX_PLL_PLLDIV3_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV3_RG_OFFSET) +#define C66XX_PLL_PLLCMD_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLCMD_RG_OFFSET) +#define C66XX_PLL_PLLSTAT_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLSTAT_RG_OFFSET) +#define C66XX_PLL_ALNCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_ALNCTL_RG_OFFSET) +#define C66XX_PLL_DCHANGE_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_DCHANGE_RG_OFFSET) +#define C66XX_PLL_SYSTAT_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_SYSTAT_RG_OFFSET) +#define C66XX_PLL_PLLDIV4_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV4_RG_OFFSET) +#define C66XX_PLL_PLLDIV5_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV5_RG_OFFSET) +#define C66XX_PLL_PLLDIV6_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV6_RG_OFFSET) +#define C66XX_PLL_PLLDIV7_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV7_RG_OFFSET) +#define C66XX_PLL_PLLDIV8_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV8_RG_OFFSET) +#define C66XX_PLL_PLLDIV9_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV9_RG_OFFSET) +#define C66XX_PLL_PLLDIV10_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV10_RG_OFFSET) +#define C66XX_PLL_PLLDIV11_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV11_RG_OFFSET) +#define C66XX_PLL_PLLDIV12_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV12_RG_OFFSET) +#define C66XX_PLL_PLLDIV13_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV13_RG_OFFSET) +#define C66XX_PLL_PLLDIV14_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV14_RG_OFFSET) +#define C66XX_PLL_PLLDIV15_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV15_RG_OFFSET) +#define C66XX_PLL_PLLDIV16_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV16_RG_OFFSET) + + +//------------ PLL control register defs -------------------------------------- +#define C66XX_PLL_PLLCTL_PLLENSRC_BITMASK 0x20 +#define C66XX_PLL_PLLCTL_PLLENSRC_BITSHIFT 5 +#define C66XX_PLL_PLLCTL_PLLRST_BITMASK 0x8 +#define C66XX_PLL_PLLCTL_PLLRST_BITSHIFT 3 +#define C66XX_PLL_PLLCTL_PLLPWRDN_BITMASK 0x2 +#define C66XX_PLL_PLLCTL_PLLPWRDN_BITSHIFT 1 +#define C66XX_PLL_PLLCTL_PLLEN_BITMASK 0x1 +#define C66XX_PLL_PLLCTL_PLLEN_BITSHIFT 0 + + +//------------ PLL secondary control register defs ---------------------------- +#define C66XX_PLL_SECCTL_BYPASS_BITMASK 0x00800000 +#define C66XX_PLL_SECCTL_BYPASS_BITSHIFT 23 +#define C66XX_PLL_SECCTL_OUTPUT_DIVIDE_BITMASK 0x00780000 +#define C66XX_PLL_SECCTL_OUTPUT_DIVIDE_BITSHIFT 19 + + +//------------ PLL multiplier control register defs --------------------------- +#define C66XX_PLL_PLLM_PLLM_BITMASK 0x3f +#define C66XX_PLL_PLLM_PLLM_BITSHIFT 0 + + +//------------ PLL controller divider registers defs -------------------------- +#define C66XX_PLL_PLLDIV_DEN_BITMASK 0x8000 +#define C66XX_PLL_PLLDIV_DEN_BITSHIFT 15 +#define C66XX_PLL_PLLDIV_RATIO_BITMASK 0xff +#define C66XX_PLL_PLLDIV_RATIO_BITSHIFT 0 + + +//------------ PLL controller command register defs --------------------------- +#define C66XX_PLL_PLLCMD_GOSET_BITMASK 0x1 +#define C66XX_PLL_PLLCMD_GOSET_BITSHIFT 0 + + +//------------ PLL controller status register defs ---------------------------- +#define C66XX_PLL_PLLSTAT_GOSTAT_BITMASK 0x1 +#define C66XX_PLL_PLLSTAT_GOSTAT_BITSHIFT 0 + + +//------------ PLL controller clock align control register defs --------------- +#define C66XX_PLL_ALNCTL_ALN_BITMASK 0xffff +#define C66XX_PLL_ALNCTL_ALN_BITSHIFT 0 + + +//------------ PLL controller divider ratio change status register defs ------- +#define C66XX_PLL_DCHANGE_SYS_BITMASK 0xffff +#define C66XX_PLL_DCHANGE_SYS_BITSHIFT 0 + + +//------------ SYSCLK status register defs ------------------------------------ +#define C66XX_PLL_SYSTAT_SYSON_BITMASK 0xffff +#define C66XX_PLL_SYSTAT_SYSON_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +//============ Device State Control registers ================================= +//============================================================================= +/* + * !!! Note that this section contains only those definitions + * that are missed in TI C6000 Chip Support Library (CSL) !!! + */ + +// JTAG ID register - r-only +#define C66XX_BOOTCFG_JTAGID_RG_OFFSET 0x18 +// Device status register - r/w +#define C66XX_BOOTCFG_DEVSTAT_RG_OFFSET 0x20 +// Boot kicker 0 register - r/w +#define C66XX_BOOTCFG_KICK0_RG_OFFSET 0x38 +// Boot kicker 1 register - r/w +#define C66XX_BOOTCFG_KICK1_RG_OFFSET 0x3c +// DSP0 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR0_RG_OFFSET 0x40 +// DSP1 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR1_RG_OFFSET 0x44 +// DSP2 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR2_RG_OFFSET 0x48 +// DSP3 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR3_RG_OFFSET 0x4c +// DSP4 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR4_RG_OFFSET 0x50 +// DSP5 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR5_RG_OFFSET 0x54 +// DSP6 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR6_RG_OFFSET 0x58 +// DSP7 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR7_RG_OFFSET 0x5c +// MAC 1 address register - r-only +#define C66XX_BOOTCFG_MACID1_RG_OFFSET 0x110 +// MAC 2 address register - r-only +#define C66XX_BOOTCFG_MACID2_RG_OFFSET 0x114 +// LRESETNMI PIN status clear register - r/w +#define C66XX_BOOTCFG_LRSTNMIPINSTAT_CLR_RG_OFFSET 0x130 +// Reset status clear register - r/w +#define C66XX_BOOTCFG_RESET_STAT_CLR_RG_OFFSET 0x134 +// Boot complete register - r/w +#define C66XX_BOOTCFG_BOOTCOMPLETE_RG_OFFSET 0x13c +// Reset status register - r-only +#define C66XX_BOOTCFG_RESET_STAT_RG_OFFSET 0x144 +// LRESETNMI PIN status register - r-only +#define C66XX_BOOTCFG_LRSTNMIPINSTAT_RG_OFFSET 0x148 +// Device configuration register - r/w +#define C66XX_BOOTCFG_DEVCFG_RG_OFFSET 0x14c +// Power state control register - r/w +#define C66XX_BOOTCFG_PWRSTATECTL_RG_OFFSET 0x150 +// SRIO SerDes macro status register - r-only +#define C66XX_BOOTCFG_SRIO_SERDES_STS_RG_OFFSET 0x154 +// SMGII SerDes macro status register - r-only +#define C66XX_BOOTCFG_SMGII_SERDES_STS_RG_OFFSET 0x158 +// PCIe SerDes macro status register - r-only +#define C66XX_BOOTCFG_PCIE_SERDES_STS_RG_OFFSET 0x15c +// HyperLink SerDes macro status register - r-only +#define C66XX_BOOTCFG_HYPERLINK_SERDES_STS_RG_OFFSET 0x160 +// NMI generation for CorePac0 register - r/w +#define C66XX_BOOTCFG_NMIGR0_RG_OFFSET 0x200 +// NMI generation for CorePac1 register - r/w +#define C66XX_BOOTCFG_NMIGR1_RG_OFFSET 0x204 +// NMI generation for CorePac2 register - r/w +#define C66XX_BOOTCFG_NMIGR2_RG_OFFSET 0x208 +// NMI generation for CorePac3 register - r/w +#define C66XX_BOOTCFG_NMIGR3_RG_OFFSET 0x20c +// NMI generation for CorePac4 register - r/w +#define C66XX_BOOTCFG_NMIGR4_RG_OFFSET 0x210 +// NMI generation for CorePac5 register - r/w +#define C66XX_BOOTCFG_NMIGR5_RG_OFFSET 0x214 +// NMI generation for CorePac6 register - r/w +#define C66XX_BOOTCFG_NMIGR6_RG_OFFSET 0x218 +// NMI generation for CorePac7 register - r/w +#define C66XX_BOOTCFG_NMIGR7_RG_OFFSET 0x21c +// IPC generation for CorePac0 register - r/w +#define C66XX_BOOTCFG_IPCGR0_RG_OFFSET 0x240 +// IPC generation for CorePac1 register - r/w +#define C66XX_BOOTCFG_IPCGR1_RG_OFFSET 0x244 +// IPC generation for CorePac2 register - r/w +#define C66XX_BOOTCFG_IPCGR2_RG_OFFSET 0x248 +// IPC generation for CorePac3 register - r/w +#define C66XX_BOOTCFG_IPCGR3_RG_OFFSET 0x24c +// IPC generation for CorePac4 register - r/w +#define C66XX_BOOTCFG_IPCGR4_RG_OFFSET 0x250 +// IPC generation for CorePac5 register - r/w +#define C66XX_BOOTCFG_IPCGR5_RG_OFFSET 0x254 +// IPC generation for CorePac6 register - r/w +#define C66XX_BOOTCFG_IPCGR6_RG_OFFSET 0x258 +// IPC generation for CorePac7 register - r/w +#define C66XX_BOOTCFG_IPCGR7_RG_OFFSET 0x25c + +// Timer Input Selection register - r/w +#define C66XX_BOOTCFG_TINPSEL_RG_OFFSET 0x300 +// Timer Output Selection register - r/w +#define C66XX_BOOTCFG_TOUTPSEL_RG_OFFSET 0x304 + +// Main PLL Control register 0 - r/w +#define C66XX_BOOTCFG_MAINPLLCTL0_RG_OFFSET 0x328 +// Main PLL Control register 1 - r/w +#define C66XX_BOOTCFG_MAINPLLCTL1_RG_OFFSET 0x32c +// DDR3 PLL Control register 0 - r/w +#define C66XX_BOOTCFG_DDR3PLLCTL0_RG_OFFSET 0x330 +// DDR3 PLL Control register 1 - r/w +#define C66XX_BOOTCFG_DDR3PLLCTL1_RG_OFFSET 0x334 +// Pass PLL Control register 0 - r/w +#define C66XX_BOOTCFG_PASSPLLCTL0_RG_OFFSET 0x338 +// Pass PLL Control register 1 - r/w +#define C66XX_BOOTCFG_PASSPLLCTL1_RG_OFFSET 0x33c +// Device speed register - r-only +#define C66XX_BOOTCFG_DEVSPEED_RG_OFFSET 0x3f8 + +#define C66XX_BOOTCFG_TINPSEL_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_TINPSEL_RG_OFFSET) +#define C66XX_BOOTCFG_TOUTPSEL_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_TOUTPSEL_RG_OFFSET) +#define C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_MAINPLLCTL0_RG_OFFSET) +#define C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_MAINPLLCTL1_RG_OFFSET) +#define C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_DDR3PLLCTL0_RG_OFFSET) +#define C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_DDR3PLLCTL1_RG_OFFSET) +#define C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_PASSPLLCTL0_RG_OFFSET) +#define C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_PASSPLLCTL1_RG_OFFSET) +#define C66XX_BOOTCFG_DEVSPEED_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_DEVSPEED_RG_OFFSET) + + +//------------ Main PLL Control register 0 defs ------------------------------- +#define C66XX_BOOTCFG_MAINPLLCTL0_BWADJ_BITMASK 0xff000000 +#define C66XX_BOOTCFG_MAINPLLCTL0_BWADJ_BITSHIFT 24 +#define C66XX_BOOTCFG_MAINPLLCTL0_PLLM_BITMASK 0x7f000 +#define C66XX_BOOTCFG_MAINPLLCTL0_PLLM_BITSHIFT 12 +#define C66XX_BOOTCFG_MAINPLLCTL0_PLLD_BITMASK 0x3f +#define C66XX_BOOTCFG_MAINPLLCTL0_PLLD_BITSHIFT 0 + + +//------------ Main PLL Control register 1 defs ------------------------------- +#define C66XX_BOOTCFG_MAINPLLCTL1_ENSAT_BITMASK 0x40 +#define C66XX_BOOTCFG_MAINPLLCTL1_ENSAT_BITSHIFT 6 +#define C66XX_BOOTCFG_MAINPLLCTL1_BWADJ_BITMASK 0xf +#define C66XX_BOOTCFG_MAINPLLCTL1_BWADJ_BITSHIFT 0 + + +//------------ DDR3 PLL Control register 0 defs ------------------------------- +#define C66XX_BOOTCFG_DDR3PLLCTL0_BWADJ_BITMASK 0xff000000 +#define C66XX_BOOTCFG_DDR3PLLCTL0_BWADJ_BITSHIFT 24 +#define C66XX_BOOTCFG_DDR3PLLCTL0_BYPASS_BITMASK 0x800000 +#define C66XX_BOOTCFG_DDR3PLLCTL0_BYPASS_BITSHIFT 23 +#define C66XX_BOOTCFG_DDR3PLLCTL0_PLLM_BITMASK 0x7ffc0 +#define C66XX_BOOTCFG_DDR3PLLCTL0_PLLM_BITSHIFT 6 +#define C66XX_BOOTCFG_DDR3PLLCTL0_PLLD_BITMASK 0x3f +#define C66XX_BOOTCFG_DDR3PLLCTL0_PLLD_BITSHIFT 0 + + +//------------ DDR3 PLL Control register 1 defs ------------------------------- +#define C66XX_BOOTCFG_DDR3PLLCTL1_PLLRST_BITMASK 0x2000 +#define C66XX_BOOTCFG_DDR3PLLCTL1_PLLRST_BITSHIFT 13 +#define C66XX_BOOTCFG_DDR3PLLCTL1_ENSAT_BITMASK 0x40 +#define C66XX_BOOTCFG_DDR3PLLCTL1_ENSAT_BITSHIFT 6 +#define C66XX_BOOTCFG_DDR3PLLCTL1_BWADJ_BITMASK 0xf +#define C66XX_BOOTCFG_DDR3PLLCTL1_BWADJ_BITSHIFT 0 + + +//------------ PASS PLL Control register 0 defs ------------------------------- +#define C66XX_BOOTCFG_PASSPLLCTL0_BWADJ_BITMASK 0xff000000 +#define C66XX_BOOTCFG_PASSPLLCTL0_BWADJ_BITSHIFT 24 +#define C66XX_BOOTCFG_PASSPLLCTL0_BYPASS_BITMASK 0x800000 +#define C66XX_BOOTCFG_PASSPLLCTL0_BYPASS_BITSHIFT 23 +#define C66XX_BOOTCFG_PASSPLLCTL0_PLLM_BITMASK 0x7ffc0 +#define C66XX_BOOTCFG_PASSPLLCTL0_PLLM_BITSHIFT 6 +#define C66XX_BOOTCFG_PASSPLLCTL0_PLLD_BITMASK 0x3f +#define C66XX_BOOTCFG_PASSPLLCTL0_PLLD_BITSHIFT 0 + + +//------------ PASS PLL Control register 1 defs ------------------------------- +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLRST_BITMASK 0x4000 +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLRST_BITSHIFT 14 +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLSELECT_BITMASK 0x2000 +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLSELECT_BITSHIFT 13 +#define C66XX_BOOTCFG_PASSPLLCTL1_ENSAT_BITMASK 0x40 +#define C66XX_BOOTCFG_PASSPLLCTL1_ENSAT_BITSHIFT 6 +#define C66XX_BOOTCFG_PASSPLLCTL1_BWADJ_BITMASK 0xf +#define C66XX_BOOTCFG_PASSPLLCTL1_BWADJ_BITSHIFT 0 + + +//------------ Device speed register defs ------------------------------------- +#define C66XX_BOOTCFG_DEVSPEED_DEVSPEED_BITMASK 0xff800000 +#define C66XX_BOOTCFG_DEVSPEED_DEVSPEED_BITSHIFT 23 + +// DSP core speed defs in MHz +#define C66XX_DSP_CORE_SPEED_800MHZ 800 +#define C66XX_DSP_CORE_SPEED_1000MHZ 1000 +#define C66XX_DSP_CORE_SPEED_1200MHZ 1200 +#define C66XX_DSP_CORE_SPEED_1250MHZ 1250 +#define C66XX_DSP_CORE_SPEED_1400MHZ 1400 + + +//------------ MACID2 register defs ------------------------------------------- +#define C66XX_BOOTCFG_MACID2_MACID_BITMASK 0xffff +#define C66XX_BOOTCFG_MACID2_MACID_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +//============ Power & sleep controller definitions =========================== +//============================================================================= +/* + * !!! Note that this section contains only those definitions + * that are missed in TI C6000 Chip Support Library (CSL) !!! + */ + +// Power Domains Definitions +#define C66XX_PSC_PD_ALWAYSON 0 +#define C66XX_PSC_PD_TETB 1 +#define C66XX_PSC_PD_PA 2 +#define C66XX_PSC_PD_PCIE 3 +#define C66XX_PSC_PD_SRIO 4 +#define C66XX_PSC_PD_HYPERLINK 5 +#define C66XX_PSC_PD_MSM_SRAM 7 +#define C66XX_PSC_PD_DSP0 8 +#define C66XX_PSC_PD_DSP1 9 +#define C66XX_PSC_PD_DSP2 10 +#define C66XX_PSC_PD_DSP3 11 +#define C66XX_PSC_PD_DSP4 12 +#define C66XX_PSC_PD_DSP5 13 +#define C66XX_PSC_PD_DSP6 14 +#define C66XX_PSC_PD_DSP7 15 +#define C66XX_PSC_PD_COUNT (C66XX_PSC_PD_DSP7 + 1) + +// Power Domains State Definitions +#define C66XX_PSC_PD_STATE_OFF PSC_PDSTATE_OFF +#define C66XX_PSC_PD_STATE_ON PSC_PDSTATE_ON + + +// Power & Sleep Controller Clock Domains Definitions +#define C66XX_PSC_LPSC_SHARED_LPSC 0 +#define C66XX_PSC_LPSC_SMARTREFLEX 1 +#define C66XX_PSC_LPSC_DDR3_EMIF 2 +#define C66XX_PSC_LPSC_EMIF16_SPI 3 +#define C66XX_PSC_LPSC_TSIP 4 +#define C66XX_PSC_LPSC_DEBUG_TRACE 5 +#define C66XX_PSC_LPSC_TETB 6 +#define C66XX_PSC_LPSC_PA 7 +#define C66XX_PSC_LPSC_ETHERNET 8 +#define C66XX_PSC_LPSC_SA 9 +#define C66XX_PSC_LPSC_PCIE 10 +#define C66XX_PSC_LPSC_SRIO 11 +#define C66XX_PSC_LPSC_HYPERLINK 12 +#define C66XX_PSC_LPSC_MSM_SRAM 14 +#define C66XX_PSC_LPSC_DSP0 15 +#define C66XX_PSC_LPSC_DSP1 16 +#define C66XX_PSC_LPSC_DSP2 17 +#define C66XX_PSC_LPSC_DSP3 18 +#define C66XX_PSC_LPSC_DSP4 19 +#define C66XX_PSC_LPSC_DSP5 20 +#define C66XX_PSC_LPSC_DSP6 21 +#define C66XX_PSC_LPSC_DSP7 22 +#define C66XX_PSC_LPSC_COUNT (C66XX_PSC_LPSC_DSP7 + 1) + +// Clock Domains State Definitions +#define C66XX_PSC_LPSC_STATE_OFF PSC_MODSTATE_SWRSTDISABLE +#define C66XX_PSC_LPSC_STATE_ON PSC_MODSTATE_ENABLE + +//============================================================================= + + + +//============================================================================= +//============ I2C definitions ================================================ +//============================================================================= +/* + * !!! Note that this section contains only those definitions + * that are missed in TI C6000 Chip Support Library (CSL) !!! + */ + +// I2C own address register - r/w +#define C66XX_I2C_ICOAR_RG_OFFSET 0x00 +// I2C interrupt mask register - r/w +#define C66XX_I2C_ICIMR_RG_OFFSET 0x04 +// I2C interrupt status register - r/w +#define C66XX_I2C_ICSTR_RG_OFFSET 0x08 +// I2C clock low-time divider register - r/w +#define C66XX_I2C_ICCLKL_RG_OFFSET 0x0c +// I2C clock high-time divider register - r/w +#define C66XX_I2C_ICCLKH_RG_OFFSET 0x10 +// I2C data count register - r/w +#define C66XX_I2C_ICCNT_RG_OFFSET 0x14 +// I2C data receive register - r-only +#define C66XX_I2C_ICDRR_RG_OFFSET 0x18 +// I2C slave address register - r/w +#define C66XX_I2C_ICSAR_RG_OFFSET 0x1c +// I2C data transmit register - r/w +#define C66XX_I2C_ICDXR_RG_OFFSET 0x20 +// I2C mode register - r/w +#define C66XX_I2C_ICMDR_RG_OFFSET 0x24 +// I2C interrupt vector register - r/w +#define C66XX_I2C_ICIVR_RG_OFFSET 0x28 +// I2C extended mode register - r/w +#define C66XX_I2C_ICEMDR_RG_OFFSET 0x2c +// I2C prescaler register - r/w +#define C66XX_I2C_ICPSC_RG_OFFSET 0x30 +// I2C peripheral identification 1 register - r/w +#define C66XX_I2C_ICPID1_RG_OFFSET 0x34 +// I2C peripheral identification 2 register - r/w +#define C66XX_I2C_ICPID2_RG_OFFSET 0x38 + +#define C66XX_I2C_ICOAR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICOAR_RG_OFFSET) +#define C66XX_I2C_ICIMR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICIMR_RG_OFFSET) +#define C66XX_I2C_ICSTR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICSTR_RG_OFFSET) +#define C66XX_I2C_ICCLKL_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICCLKL_RG_OFFSET) +#define C66XX_I2C_ICCLKH_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICCLKH_RG_OFFSET) +#define C66XX_I2C_ICCNT_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICCNT_RG_OFFSET) +#define C66XX_I2C_ICDRR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICDRR_RG_OFFSET) +#define C66XX_I2C_ICSAR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICSAR_RG_OFFSET) +#define C66XX_I2C_ICDXR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICDXR_RG_OFFSET) +#define C66XX_I2C_ICMDR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICMDR_RG_OFFSET) +#define C66XX_I2C_ICIVR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICIVR_RG_OFFSET) +#define C66XX_I2C_ICEMDR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICEMDR_RG_OFFSET) +#define C66XX_I2C_ICPSC_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICPSC_RG_OFFSET) +#define C66XX_I2C_ICPID1_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICPID1_RG_OFFSET) +#define C66XX_I2C_ICPID2_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICPID2_RG_OFFSET) + + +//------------ I2C own address register defs ---------------------------------- +#define C66XX_I2C_ICOAR_OADDR_BITMASK 0x3ff +#define C66XX_I2C_ICOAR_OADDR_BITSHIFT 0 + + +//------------ I2C interrupt mask register defs ------------------------------- +#define C66XX_I2C_ICIMR_AAS_BITMASK 0x40 +#define C66XX_I2C_ICIMR_AAS_BITSHIFT 6 +#define C66XX_I2C_ICIMR_SCD_BITMASK 0x20 +#define C66XX_I2C_ICIMR_SCD_BITSHIFT 5 +#define C66XX_I2C_ICIMR_ICXRDY_BITMASK 0x10 +#define C66XX_I2C_ICIMR_ICXRDY_BITSHIFT 4 +#define C66XX_I2C_ICIMR_ICRDRDY_BITMASK 0x8 +#define C66XX_I2C_ICIMR_ICRDRDY_BITSHIFT 3 +#define C66XX_I2C_ICIMR_ARDY_BITMASK 0x4 +#define C66XX_I2C_ICIMR_ARDY_BITSHIFT 2 +#define C66XX_I2C_ICIMR_NACK_BITMASK 0x2 +#define C66XX_I2C_ICIMR_NACK_BITSHIFT 1 +#define C66XX_I2C_ICIMR_AL_BITMASK 0x1 +#define C66XX_I2C_ICIMR_AL_BITSHIFT 0 +#define C66XX_I2C_ICIMR_RG_BITMASK 0x7f + + +//------------ I2C interrupt status register defs ----------------------------- +#define C66XX_I2C_ICSTR_SDIR_BITMASK 0x4000 +#define C66XX_I2C_ICSTR_SDIR_BITSHIFT 14 +#define C66XX_I2C_ICSTR_NACKSNT_BITMASK 0x2000 +#define C66XX_I2C_ICSTR_NACKSNT_BITSHIFT 13 +#define C66XX_I2C_ICSTR_BB_BITMASK 0x1000 +#define C66XX_I2C_ICSTR_BB_BITSHIFT 12 +#define C66XX_I2C_ICSTR_RSFULL_BITMASK 0x800 +#define C66XX_I2C_ICSTR_RSFULL_BITSHIFT 11 +#define C66XX_I2C_ICSTR_XSMT_BITMASK 0x400 +#define C66XX_I2C_ICSTR_XSMT_BITSHIFT 10 +#define C66XX_I2C_ICSTR_AAS_BITMASK 0x200 +#define C66XX_I2C_ICSTR_AAS_BITSHIFT 9 +#define C66XX_I2C_ICSTR_AD0_BITMASK 0x100 +#define C66XX_I2C_ICSTR_AD0_BITSHIFT 8 +#define C66XX_I2C_ICSTR_SCD_BITMASK 0x20 +#define C66XX_I2C_ICSTR_SCD_BITSHIFT 5 +#define C66XX_I2C_ICSTR_ICXRDY_BITMASK 0x10 +#define C66XX_I2C_ICSTR_ICXRDY_BITSHIFT 4 +#define C66XX_I2C_ICSTR_ICRDRDY_BITMASK 0x8 +#define C66XX_I2C_ICSTR_ICRDRDY_BITSHIFT 3 +#define C66XX_I2C_ICSTR_ARDY_BITMASK 0x4 +#define C66XX_I2C_ICSTR_ARDY_BITSHIFT 2 +#define C66XX_I2C_ICSTR_NACK_BITMASK 0x2 +#define C66XX_I2C_ICSTR_NACK_BITSHIFT 1 +#define C66XX_I2C_ICSTR_AL_BITMASK 0x1 +#define C66XX_I2C_ICSTR_AL_BITSHIFT 0 + + +//------------ I2C clock low-time divider register defs ----------------------- +#define C66XX_I2C_ICCLKL_ICCL_BITMASK 0xffff +#define C66XX_I2C_ICCLKL_ICCL_BITSHIFT 0 + + +//------------ I2C clock high-time divider register defs ---------------------- +#define C66XX_I2C_ICCLKH_ICCH_BITMASK 0xffff +#define C66XX_I2C_ICCLKH_ICCH_BITSHIFT 0 + + +//------------ I2C data count register defs ----------------------------------- +#define C66XX_I2C_ICCNT_ICDC_BITMASK 0xffff +#define C66XX_I2C_ICCNT_ICDC_BITSHIFT 0 + + +//------------ I2C data receive register defs --------------------------------- +#define C66XX_I2C_ICDRR_D_BITMASK 0xff +#define C66XX_I2C_ICDRR_D_BITSHIFT 0 + + +//------------ I2C slave address register defs -------------------------------- +#define C66XX_I2C_ICSAR_SADDR_BITMASK 0x3ff +#define C66XX_I2C_ICSAR_SADDR_BITSHIFT 0 + + +//------------ I2C data transmit register defs -------------------------------- +#define C66XX_I2C_ICDXR_D_BITMASK 0xff +#define C66XX_I2C_ICDXR_D_BITSHIFT 0 + + +//------------ I2C mode register defs ----------------------------------------- +#define C66XX_I2C_ICMDR_NACKMOD_BITMASK 0x8000 +#define C66XX_I2C_ICMDR_NACKMOD_BITSHIFT 15 +#define C66XX_I2C_ICMDR_FREE_BITMASK 0x4000 +#define C66XX_I2C_ICMDR_FREE_BITSHIFT 14 +#define C66XX_I2C_ICMDR_STT_BITMASK 0x2000 +#define C66XX_I2C_ICMDR_STT_BITSHIFT 13 +#define C66XX_I2C_ICMDR_STP_BITMASK 0x800 +#define C66XX_I2C_ICMDR_STP_BITSHIFT 11 +#define C66XX_I2C_ICMDR_MST_BITMASK 0x400 +#define C66XX_I2C_ICMDR_MST_BITSHIFT 10 +#define C66XX_I2C_ICMDR_TRX_BITMASK 0x200 +#define C66XX_I2C_ICMDR_TRX_BITSHIFT 9 +#define C66XX_I2C_ICMDR_XA_BITMASK 0x100 +#define C66XX_I2C_ICMDR_XA_BITSHIFT 8 +#define C66XX_I2C_ICMDR_RM_BITMASK 0x80 +#define C66XX_I2C_ICMDR_RM_BITSHIFT 7 +#define C66XX_I2C_ICMDR_DLB_BITMASK 0x40 +#define C66XX_I2C_ICMDR_DLB_BITSHIFT 6 +#define C66XX_I2C_ICMDR_IRS_BITMASK 0x20 +#define C66XX_I2C_ICMDR_IRS_BITSHIFT 5 +#define C66XX_I2C_ICMDR_STB_BITMASK 0x10 +#define C66XX_I2C_ICMDR_STB_BITSHIFT 4 +#define C66XX_I2C_ICMDR_FDF_BITMASK 0x8 +#define C66XX_I2C_ICMDR_FDF_BITSHIFT 3 +#define C66XX_I2C_ICMDR_BC_BITMASK 0x7 +#define C66XX_I2C_ICMDR_BC_BITSHIFT 0 + + +//------------ I2C interrupt vector register defs ----------------------------- +#define C66XX_I2C_ICIVR_INTCODE_BITMASK 0x7 +#define C66XX_I2C_ICIVR_INTCODE_BITSHIFT 0 + + +//------------ I2C extended mode register defs -------------------------------- +#define C66XX_I2C_ICEMDR_IGNACK_BITMASK 0x2 +#define C66XX_I2C_ICEMDR_IGNACK_BITSHIFT 1 +#define C66XX_I2C_ICEMDR_BCM_BITMASK 0x1 +#define C66XX_I2C_ICEMDR_BCM_BITSHIFT 0 + + +//------------ I2C prescaler register defs ------------------------------------ +#define C66XX_I2C_ICPSC_IPSC_BITMASK 0xff +#define C66XX_I2C_ICPSC_IPSC_BITSHIFT 0 + + +//------------ I2C peripheral identification 1 register defs ------------------ +#define C66XX_I2C_ICPID1_CLASS_BITMASK 0xff00 +#define C66XX_I2C_ICPID1_CLASS_BITSHIFT 8 +#define C66XX_I2C_ICPID1_REVISION_BITMASK 0xff +#define C66XX_I2C_ICPID1_REVISION_BITSHIFT 0 + + +//------------ I2C peripheral identification 2 register defs ------------------ +#define C66XX_I2C_ICPID2_TYPE_BITMASK 0xffff +#define C66XX_I2C_ICPID2_TYPE_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +//============ EMIF16 configuration registers ================================= +//============================================================================= +// Revision code and status register - r-only +#define C66XX_EMIF16_RCSR_RG_OFFSET 0x00 +// Async wait cycle config register - r/w +#define C66XX_EMIF16_AWCCR_RG_OFFSET 0x04 +// Async 1 (CE0) config register - r/w +#define C66XX_EMIF16_A1CR_RG_OFFSET 0x10 +// Async 2 (CE1) config register - r/w +#define C66XX_EMIF16_A2CR_RG_OFFSET 0x14 +// Async 3 (CE2) config register - r/w +#define C66XX_EMIF16_A3CR_RG_OFFSET 0x18 +// Async 4 (CE3) config register - r/w +#define C66XX_EMIF16_A4CR_RG_OFFSET 0x1c +// Interrupt raw register - r/w +#define C66XX_EMIF16_IRR_RG_OFFSET 0x40 +// Interrupt masked register - r/w +#define C66XX_EMIF16_IMR_RG_OFFSET 0x44 +// Interrupt mask set register - r/w +#define C66XX_EMIF16_IMSR_RG_OFFSET 0x48 +// Interrupt mask clear register - r/w +#define C66XX_EMIF16_IMCR_RG_OFFSET 0x4c +// Page mode control register - r/w +#define C66XX_EMIF16_PMCR_RG_OFFSET 0x68 + +#define C66XX_EMIF16_RCSR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_RCSR_RG_OFFSET) +#define C66XX_EMIF16_AWCCR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_AWCCR_RG_OFFSET) +#define C66XX_EMIF16_A1CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A1CR_RG_OFFSET) +#define C66XX_EMIF16_A2CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A2CR_RG_OFFSET) +#define C66XX_EMIF16_A3CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A3CR_RG_OFFSET) +#define C66XX_EMIF16_A4CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A4CR_RG_OFFSET) +#define C66XX_EMIF16_IRR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IRR_RG_OFFSET) +#define C66XX_EMIF16_IMR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IMR_RG_OFFSET) +#define C66XX_EMIF16_IMSR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IMSR_RG_OFFSET) +#define C66XX_EMIF16_IMCR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IMCR_RG_OFFSET) +#define C66XX_EMIF16_PMCR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_PMCR_RG_OFFSET) + + +//------------ Revision code and status register defs ------------------------- +#define C66XX_EMIF16_RCSR_BE_BITMASK 0x80000000 +#define C66XX_EMIF16_RCSR_BE_BITSHIFT 31 +#define C66XX_EMIF16_RCSR_MOD_ID_BITMASK 0x3fff0000 +#define C66XX_EMIF16_RCSR_MOD_ID_BITSHIFT 16 +#define C66XX_EMIF16_RCSR_MJ_REV_BITMASK 0xff00 +#define C66XX_EMIF16_RCSR_MJ_REV_BITSHIFT 8 +#define C66XX_EMIF16_RCSR_MIN_REV_BITMASK 0xff +#define C66XX_EMIF16_RCSR_MIN_REV_BITSHIFT 0 + +#define C66XX_EMIF16_RCSR_MOD_ID_DEFAULT_VALUE 0x46 +#define C66XX_EMIF16_RCSR_MJ_REV_DEFAULT_VALUE 0x4 +#define C66XX_EMIF16_RCSR_MIN_REV_DEFAULT_VALUE 0x0 + + +//------------ Async wait cycle config register defs -------------------------- +#define C66XX_EMIF16_AWCCR_WP1_BITMASK 0x20000000 +#define C66XX_EMIF16_AWCCR_WP1_BITSHIFT 29 +#define C66XX_EMIF16_AWCCR_WP0_BITMASK 0x10000000 +#define C66XX_EMIF16_AWCCR_WP0_BITSHIFT 28 +#define C66XX_EMIF16_AWCCR_CS5_WAIT_BITMASK 0xc00000 +#define C66XX_EMIF16_AWCCR_CS5_WAIT_BITSHIFT 22 +#define C66XX_EMIF16_AWCCR_CS4_WAIT_BITMASK 0x300000 +#define C66XX_EMIF16_AWCCR_CS4_WAIT_BITSHIFT 20 +#define C66XX_EMIF16_AWCCR_CS3_WAIT_BITMASK 0xc0000 +#define C66XX_EMIF16_AWCCR_CS3_WAIT_BITSHIFT 18 +#define C66XX_EMIF16_AWCCR_CS2_WAIT_BITMASK 0x30000 +#define C66XX_EMIF16_AWCCR_CS2_WAIT_BITSHIFT 16 +#define C66XX_EMIF16_AWCCR_MAX_EXT_WAIT_BITMASK 0xff +#define C66XX_EMIF16_AWCCR_MAX_EXT_WAIT_BITSHIFT 0 + + +//------------ Async 1 config register defs ----------------------------------- +#define C66XX_EMIF16_A1CR_SS_BITMASK 0x80000000 +#define C66XX_EMIF16_A1CR_SS_BITSHIFT 31 +#define C66XX_EMIF16_A1CR_EW_BITMASK 0x40000000 +#define C66XX_EMIF16_A1CR_EW_BITSHIFT 30 +#define C66XX_EMIF16_A1CR_W_SETUP_BITMASK 0x3c000000 +#define C66XX_EMIF16_A1CR_W_SETUP_BITSHIFT 26 +#define C66XX_EMIF16_A1CR_W_STROBE_BITMASK 0x3f00000 +#define C66XX_EMIF16_A1CR_W_STROBE_BITSHIFT 20 +#define C66XX_EMIF16_A1CR_W_HOLD_BITMASK 0xe0000 +#define C66XX_EMIF16_A1CR_W_HOLD_BITSHIFT 17 +#define C66XX_EMIF16_A1CR_R_SETUP_BITMASK 0x1e000 +#define C66XX_EMIF16_A1CR_R_SETUP_BITSHIFT 13 +#define C66XX_EMIF16_A1CR_R_STROBE_BITMASK 0x1f80 +#define C66XX_EMIF16_A1CR_R_STROBE_BITSHIFT 7 +#define C66XX_EMIF16_A1CR_R_HOLD_BITMASK 0x70 +#define C66XX_EMIF16_A1CR_R_HOLD_BITSHIFT 4 +#define C66XX_EMIF16_A1CR_TA_BITMASK 0xc +#define C66XX_EMIF16_A1CR_TA_BITSHIFT 2 +#define C66XX_EMIF16_A1CR_ASIZE_BITMASK 0x3 +#define C66XX_EMIF16_A1CR_ASIZE_BITSHIFT 0 + +#define C66XX_EMIF16_A1CR_ASIZE_8BIT 0 +#define C66XX_EMIF16_A1CR_ASIZE_16BIT 1 + + +//------------ Interrupt raw register defs ------------------------------------ +#define C66XX_EMIF16_IRR_WR_BITMASK 0x3c +#define C66XX_EMIF16_IRR_WR_BITSHIFT 2 +#define C66XX_EMIF16_IRR_AT_BITMASK 0x1 +#define C66XX_EMIF16_IRR_AT_BITSHIFT 0 + + +//------------ Interrupt masked register defs --------------------------------- +#define C66XX_EMIF16_IMR_WR_MASKED_BITMASK 0x3c +#define C66XX_EMIF16_IMR_WR_MASKED_BITSHIFT 2 +#define C66XX_EMIF16_IMR_AT_MASKED_BITMASK 0x1 +#define C66XX_EMIF16_IMR_AT_MASKED_BITSHIFT 0 + + +//------------ Interrupt mask set register defs ------------------------------- +#define C66XX_EMIF16_IMSR_WR_MASK_SET_BITMASK 0x3c +#define C66XX_EMIF16_IMSR_WR_MASK_SET_BITSHIFT 2 +#define C66XX_EMIF16_IMSR_AT_MASK_SET_BITMASK 0x1 +#define C66XX_EMIF16_IMSR_AT_MASK_SET_BITSHIFT 0 + + +//------------ Interrupt mask clear register defs ----------------------------- +#define C66XX_EMIF16_IMCR_WR_MASK_CLR_BITMASK 0x3c +#define C66XX_EMIF16_IMCR_WR_MASK_CLR_BITSHIFT 2 +#define C66XX_EMIF16_IMCR_AT_MASK_CLR_BITMASK 0x1 +#define C66XX_EMIF16_IMCR_AT_MASK_CLR_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +//============ Timer definitions ============================================== +//============================================================================= + +// Emulation Management and Clock Speed register - r-only +#define C66XX_TIMER_EMUMGT_CLKSPD_RG_OFFSET 0x0004 +// Counter register low register - r/w +#define C66XX_TIMER_CNTLO_RG_OFFSET 0x0010 +// Counter register high register - r/w +#define C66XX_TIMER_CNTHI_RG_OFFSET 0x0014 +// Period register low register - r/w +#define C66XX_TIMER_PRDLO_RG_OFFSET 0x0018 +// Period register high register - r/w +#define C66XX_TIMER_PRDHI_RG_OFFSET 0x001c +// Timer control register - r/w +#define C66XX_TIMER_TCR_RG_OFFSET 0x0020 +// Timer global control register - r/w +#define C66XX_TIMER_TGCR_RG_OFFSET 0x0024 +// Watchdog timer control register - r/w +#define C66XX_TIMER_WDTCR_RG_OFFSET 0x0028 +// Timer Reload register low register - r/w +#define C66XX_TIMER_RELLO_RG_OFFSET 0x0034 +// Timer Reload register high register - r/w +#define C66XX_TIMER_RELHI_RG_OFFSET 0x0038 +// Timer Capture register low register - r/w +#define C66XX_TIMER_CAPLO_RG_OFFSET 0x003c +// Timer Capture register high register - r/w +#define C66XX_TIMER_CAPHI_RG_OFFSET 0x0040 +// Timer interrupt control and status register - r/w +#define C66XX_TIMER_INTCTLSTAT_RG_OFFSET 0x0044 + +// Timer 0-15 registers area offset addresses +#define C66XX_TIMER_RG_AREA_OFFSET 0x00010000 +// Timer 0-15 registers addresses: timer = 0-15 +#define C66XX_TIMER_EMUMGT_CLKSPD_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_EMUMGT_CLKSPD_RG_OFFSET) +#define C66XX_TIMER_CNTLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CNTLO_RG_OFFSET) +#define C66XX_TIMER_CNTHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CNTHI_RG_OFFSET) +#define C66XX_TIMER_PRDLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_PRDLO_RG_OFFSET) +#define C66XX_TIMER_PRDHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_PRDHI_RG_OFFSET) +#define C66XX_TIMER_TCR_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_TCR_RG_OFFSET) +#define C66XX_TIMER_TGCR_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_TGCR_RG_OFFSET) +#define C66XX_TIMER_WDTCR_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_WDTCR_RG_OFFSET) +#define C66XX_TIMER_RELLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_RELLO_RG_OFFSET) +#define C66XX_TIMER_RELHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_RELHI_RG_OFFSET) +#define C66XX_TIMER_CAPLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CAPLO_RG_OFFSET) +#define C66XX_TIMER_CAPHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CAPHI_RG_OFFSET) +#define C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_INTCTLSTAT_RG_OFFSET) + + +//------------ Emulation Management and Clock Speed register defs ------------- +#define C66XX_TIMER_EMUMGT_CLKSPD_CLKDIV_BITMASK 0x000f0000 +#define C66XX_TIMER_EMUMGT_CLKSPD_CLKDIV_BITSHIFT 16 + + +//------------ Timer control register defs ------------------------------------ +#define C66XX_TIMER_TCR_READRSTMODE_HI_BITMASK 0x04000000 +#define C66XX_TIMER_TCR_READRSTMODE_HI_BITSHIFT 26 +#define C66XX_TIMER_TCR_ENAMODE_HI_BITMASK 0x00c00000 +#define C66XX_TIMER_TCR_ENAMODE_HI_BITSHIFT 22 +#define C66XX_TIMER_TCR_PWID_HI_BITMASK 0x00300000 +#define C66XX_TIMER_TCR_PWID_HI_BITSHIFT 20 +#define C66XX_TIMER_TCR_CP_HI_BITMASK 0x00080000 +#define C66XX_TIMER_TCR_CP_HI_BITSHIFT 19 +#define C66XX_TIMER_TCR_INVOUTP_HI_BITMASK 0x00020000 +#define C66XX_TIMER_TCR_INVOUTP_HI_BITSHIFT 17 +#define C66XX_TIMER_TCR_TSTAT_HI_BITMASK 0x00010000 +#define C66XX_TIMER_TCR_TSTAT_HI_BITSHIFT 16 +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_BITMASK 0x00003000 +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_BITSHIFT 12 +#define C66XX_TIMER_TCR_CAPMODE_LO_BITMASK 0x00000800 +#define C66XX_TIMER_TCR_CAPMODE_LO_BITSHIFT 11 +#define C66XX_TIMER_TCR_READRSTMODE_LO_BITMASK 0x00000400 +#define C66XX_TIMER_TCR_READRSTMODE_LO_BITSHIFT 10 +#define C66XX_TIMER_TCR_TIEN_LO_BITMASK 0x00000200 +#define C66XX_TIMER_TCR_TIEN_LO_BITSHIFT 9 +#define C66XX_TIMER_TCR_CLKSRC_LO_BITMASK 0x00000100 +#define C66XX_TIMER_TCR_CLKSRC_LO_BITSHIFT 8 +#define C66XX_TIMER_TCR_ENAMODE_LO_BITMASK 0x000000c0 +#define C66XX_TIMER_TCR_ENAMODE_LO_BITSHIFT 6 +#define C66XX_TIMER_TCR_PWID_LO_BITMASK 0x00000030 +#define C66XX_TIMER_TCR_PWID_LO_BITSHIFT 4 +#define C66XX_TIMER_TCR_CP_LO_BITMASK 0x00000008 +#define C66XX_TIMER_TCR_CP_LO_BITSHIFT 3 +#define C66XX_TIMER_TCR_INVINP_LO_BITMASK 0x00000004 +#define C66XX_TIMER_TCR_INVINP_LO_BITSHIFT 2 +#define C66XX_TIMER_TCR_INVOUTP_LO_BITMASK 0x00000002 +#define C66XX_TIMER_TCR_INVOUTP_LO_BITSHIFT 1 +#define C66XX_TIMER_TCR_TSTAT_LO_BITMASK 0x00000001 +#define C66XX_TIMER_TCR_TSTAT_LO_BITSHIFT 0 + +#define C66XX_TIMER_TCR_ENAMODE_DISABLED 0 +#define C66XX_TIMER_TCR_ENAMODE_ONE_SHOT 1 +#define C66XX_TIMER_TCR_ENAMODE_CONT 2 +#define C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD 3 + +#define C66XX_TIMER_TCR_PWID_1_CLK 0 +#define C66XX_TIMER_TCR_PWID_2_CLK 1 +#define C66XX_TIMER_TCR_PWID_3_CLK 2 +#define C66XX_TIMER_TCR_PWID_4_CLK 3 + +#define C66XX_TIMER_TCR_CAPEVTMODE_RISING_EDGE 0 +#define C66XX_TIMER_TCR_CAPEVTMODE_FALLING_EDGE 1 +#define C66XX_TIMER_TCR_CAPEVTMODE_ANY_EDGE 2 + + +//------------ Timer global control register defs ----------------------------- +#define C66XX_TIMER_TGCR_TDDRHI_BITMASK 0x0000f000 +#define C66XX_TIMER_TGCR_TDDRHI_BITSHIFT 12 +#define C66XX_TIMER_TGCR_PSCHI_BITMASK 0x00000f00 +#define C66XX_TIMER_TGCR_PSCHI_BITSHIFT 8 +#define C66XX_TIMER_TGCR_PLUSEN_BITMASK 0x00000010 +#define C66XX_TIMER_TGCR_PLUSEN_BITSHIFT 4 +#define C66XX_TIMER_TGCR_TIMMODE_BITMASK 0x0000000c +#define C66XX_TIMER_TGCR_TIMMODE_BITSHIFT 2 +#define C66XX_TIMER_TGCR_TIMHIRS_BITMASK 0x00000002 +#define C66XX_TIMER_TGCR_TIMHIRS_BITSHIFT 1 +#define C66XX_TIMER_TGCR_TIMLORS_BITMASK 0x00000001 +#define C66XX_TIMER_TGCR_TIMLORS_BITSHIFT 0 + +#define C66XX_TIMER_TGCR_TIMMODE_64BIT_GPT 0 +#define C66XX_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED 1 +#define C66XX_TIMER_TGCR_TIMMODE_64BIT_WDT 2 +#define C66XX_TIMER_TGCR_TIMMODE_32BIT_CHAINED 3 + + +//------------ Watchdog Timer Control Register defs --------------------------- +#define C66XX_TIMER_WDTCR_WDKEY_BITMASK 0xffff0000 +#define C66XX_TIMER_WDTCR_WDKEY_BITSHIFT 16 +#define C66XX_TIMER_WDTCR_WDFLAG_BITMASK 0x00008000 +#define C66XX_TIMER_WDTCR_WDFLAG_BITSHIFT 15 +#define C66XX_TIMER_WDTCR_WDEN_BITMASK 0x00004000 +#define C66XX_TIMER_WDTCR_WDEN_BITSHIFT 14 + +#define C66XX_TIMER_WDTCR_WDKEY_FIRST_KEY 0xa5c6 +#define C66XX_TIMER_WDTCR_WDKEY_SECOND_KEY 0xda7e + + +//------------ Timer interrupt control and status register defs --------------- +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_HI_BITMASK 0x00080000 +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_HI_BITSHIFT 19 +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_HI_BITMASK 0x00040000 +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_HI_BITSHIFT 18 +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_HI_BITMASK 0x00020000 +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_HI_BITSHIFT 17 +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_HI_BITMASK 0x00010000 +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_HI_BITSHIFT 16 +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_LO_BITMASK 0x00000008 +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_LO_BITSHIFT 3 +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_LO_BITMASK 0x00000004 +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_LO_BITSHIFT 2 +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_LO_BITMASK 0x00000002 +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_LO_BITSHIFT 1 +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_LO_BITMASK 0x00000001 +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_LO_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +#endif /* __C66XX_DEF_HXX__ */ diff --git a/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx b/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx new file mode 100644 index 00000000..8564e44d --- /dev/null +++ b/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx @@ -0,0 +1,1693 @@ +/****************************************************************************** + TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. + (C) MicroLAB Systems, 2014-2015 + + File: C66xx DSP SDK API functions declarations + ----- + + Notes: + ------ + 1. This C-header file contains C66xx DSP SDK API functions declarations + and is used with C66XX.h C-header file. + + 2. This file is best viewed with the TAB setting set to '4'. + +******************************************************************************/ + + +/** + * @file C66XX_FUNCTIONS.hxx + * + * @brief SDK API functions declarations + * + * This file contains C66xx DSP SDK API functions declarations + * + */ + + +#ifndef __C66XX_FUNCTIONS_HXX__ // check for this file has been already included +#define __C66XX_FUNCTIONS_HXX__ 1 + + + +//============================================================================= +//============ Returned error codes =========================================== +//============================================================================= +/** @addtogroup C66XX_ERRORS DSP SDK API returned error codes + * @{ + */ +#define C66XX_OK 0 /**< No errors */ +#define C66XX_PARAM_ERR -1 /**< Invalid function parameter */ +#define C66XX_INVALID_HW_ERR -2 /**< Invalid H/W error (invalid board, etc.) */ +#define C66XX_HW_ERR -3 /**< H/W error (error writing to the DSP control registers, etc) */ +#define C66XX_I2C_ERR -10 /**< I2C module is not correctly operated */ +#define C66XX_I2C_AL_ERR -11 /**< I2C module arbitration lost error */ +#define C66XX_I2C_RSFULL_ERR -12 /**< I2C module overrun error */ +#define C66XX_I2C_XSMT_ERR -13 /**< I2C module underflow error */ +#define C66XX_I2C_NACK_ERR -14 /**< I2C module no-acknowledgement error */ +#define C66XX_I2C_ARDY_ERR -15 /**< I2C module register-access-ready error */ +#define C66XX_I2C_READ_ERR -16 /**< I2C module read error */ +#define C66XX_I2C_WRITE_ERR -17 /**< I2C module write error */ +#define C66XX_I2C_TIMEOUT_ERR -18 /**< I2C bus timeout error */ +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ SDK API functions ID defs ====================================== +//============================================================================= +/** @addtogroup C66XX_FUNCTIONS_ID SDK API functions ID defs + * @{ + */ + +enum +{ + C66XX_GET_ERROR_MESSAGE_FUNCTION_ID = 0, + C66XX_GET_FUNCTION_NAME_FUNCTION_ID, + C66XX_SYS_SET_CORE_RESET_STATE_FUNCTION_ID, + C66XX_SYS_GET_CORE_RESET_STATE_FUNCTION_ID, + C66XX_SYS_GET_CORE_RESET_SOURCE_FUNCTION_ID, + C66XX_SYS_SET_CORE_BOOT_ADDRESS_FUNCTION_ID, + C66XX_SYS_INIT_MAIN_PLL_FUNCTION_ID, + C66XX_SYS_GET_MAIN_PLL_SETTINGS_FUNCTION_ID, + C66XX_SYS_INIT_DDR3_PLL_FUNCTION_ID, + C66XX_SYS_GET_DDR3_PLL_SETTINGS_FUNCTION_ID, + C66XX_SYS_INIT_PASS_PLL_FUNCTION_ID, + C66XX_SYS_GET_PASS_PLL_SETTINGS_FUNCTION_ID, + C66XX_SYS_ENABLE_POWER_DOMAIN_FUNCTION_ID, + C66XX_MEM_INIT_XMC_MPAX_SEGMENT_FUNCTION_ID, + C66XX_MEM_INIT_DDR3_FUNCTION_ID, + C66XX_INT_INIT_CORE_FUNCTION_ID, + C66XX_INT_MAP_CORE_EVENT_HANDLER_FUNCTION_ID, + C66XX_INT_UNMAP_CORE_EVENT_HANDLER_FUNCTION_ID, + C66XX_INT_INIT_CHIP_FUNCTION_ID, + C66XX_GPIO_INIT_FUNCTION_ID, + C66XX_TIMER_INIT_FUNCTION_ID, + C66XX_TIMER_START_FUNCTION_ID, + C66XX_TIMER_STOP_FUNCTION_ID, + C66XX_TIMER_RESET_FUNCTION_ID, + C66XX_TIMER_ENABLE_INTERRUPTS_FUNCTION_ID, + C66XX_TIMER_DISABLE_INTERRUPTS_FUNCTION_ID, + C66XX_UART_INIT_FUNCTION_ID, + C66XX_I2C_INIT_FUNCTION_ID, + C66XX_I2C_WRITE_DATA_FUNCTION_ID, + C66XX_I2C_READ_DATA_FUNCTION_ID, + C66XX_GBE_INIT_SERDES_FUNCTION_ID, + C66XX_GBE_INIT_SGMII_FUNCTION_ID, + C66XX_SRIO_INIT_FUNCTION_ID, + C66XX_SRIO_MAP_TX_QUEUE_FUNCTION_ID, + C66XX_SRIO_ROUTE_DOORBELL_INTERRUPT_FUNCTION_ID, + C66XX_NUMBER_OF_FUNCTIONS +}; +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//============================================================================= +//============ General SDK API functions declarations ========================= +//============================================================================= + +/** @addtogroup C66XX_GENERAL_FUNCTIONS General DSP SDK API functions + * @{ + */ + +/*------------ C66XX_get_last_error() function ---------------------------*//** + * @brief Function returns error code of last executed API function + * + * @return Error code of last executed API function + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_get_last_error(void); + + +/*------------ C66XX_get_error_flag() function ---------------------------*//** + * @brief Function returns status of ERROR_FLAG for API functions + * + * ERROR_FLAG is set by each API function in case error has been detected. + * ERROR_FLAG can be reset by C66XX_clear_error_flag() API function + * + * @param[out] error_code - pointer to a variable to receive the error code in + * case error has been detected. In case pointer is NULL, then + * no error code is returned; + * @param[out] error_function_id - pointer to a variable to receive ID of the + * first API function, which has returned with error. In case + * pointer is NULL, then no function ID is returned; + * + * @return Status of ERROR_FLAG: ON or OFF + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_get_error_flag(int32_t *error_code, int32_t *error_function_id); + + +/*------------ C66XX_clear_error_flag() function -------------------------*//** + * @brief Function clear ERROR_FLAG for API functions + * + * @return Always OK + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_clear_error_flag(void); + + +/*------------ C66XX_get_error_message() function ------------------------*//** + * @brief Function returns the text interpretation of the error code. + * + * @param[in] error - error code to be interpreted; + * @param[out] error_message - pointer to the returned string. In case pointer + * is NULL, then no text is filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_get_error_message(int32_t error, char *error_message); + + +/*------------ C66XX_get_function_name() function ------------------------*//** + * @brief Function returns the text interpretation of API function. + * + * @param[in] function_id - ID of the API function to be interpreted; + * @param[out] function_name - pointer to the returned string. In case pointer + * is NULL, then no text is filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_get_function_name(int32_t function_id, char *function_name); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ System functions =============================================== +//============================================================================= + +/** @addtogroup C66XX_SYS System functions + * @{ + */ + + +/** DSP core reset source is global reset */ +#define C66XX_DSP_CORE_RESET_SRC_IS_GLOBAL_RESET 1 +/** DSP core reset source is local reset */ +#define C66XX_DSP_CORE_RESET_SRC_IS_LOCAL_RESET 2 + + +/** Main PLL Multiplier bitmask */ +#define C66XX_MAIN_PLL_PLLM_BITMASK 0x1fff +/** Main PLL Divider bitmask */ +#define C66XX_MAIN_PLL_PLLD_BITMASK 0x3f +/** Number of PLL dividers */ +#define C66XX_MAIN_PLL_PLLDIV_COUNT 16 + +/** Main PLL divider data descriptor */ +typedef struct +{ + uint32_t enable; /**< PLL divider enable flag */ + uint32_t ratio; /**< PLL divider value (8-bit) */ +} C66XX_MAIN_PLL_PLLDIV_DD; + +// Main PLL divider data descriptor length in bytes +#define C66XX_MAIN_PLL_PLLDIV_DD_LEN sizeof(C66XX_MAIN_PLL_PLLDIV_DD) + + +/** Main PLL data descriptor (contains parameters which are used to init PLL) */ +typedef struct +{ + uint32_t bypass; /**< PLL mode: bypass or not */ + uint32_t pllm; /**< PLL multiplier value (13-bit) */ + uint32_t plld; /**< PLL divider value (6-bit) */ + uint32_t output_divide; /**< PLL output divider value (4-bit) */ + C66XX_MAIN_PLL_PLLDIV_DD plldiv[C66XX_MAIN_PLL_PLLDIV_COUNT]; /**< PLL dividers */ +} C66XX_MAIN_PLL_DD; + +// Main PLL data descriptor length in bytes +#define C66XX_MAIN_PLL_DD_LEN sizeof(C66XX_MAIN_PLL_DD) + + +/** DDR3 PLL data descriptor (contains parameters which are used to init DDR3 PLL) */ +typedef struct +{ + uint32_t pllm; /**< PLL multiplier value (13-bit) */ + uint32_t plld; /**< PLL divider value (6-bit) */ +} C66XX_DDR3_PLL_DD; + +// DDR3 PLL data descriptor length in bytes +#define C66XX_DDR3_PLL_DD_LEN sizeof(C66XX_DDR3_PLL_DD) + + +/** PASS PLL data descriptor (contains parameters which are used to init PASS PLL) */ +typedef struct +{ + uint32_t pllm; /**< PLL multiplier value (13-bit) */ + uint32_t plld; /**< PLL divider value (6-bit) */ +} C66XX_PASS_PLL_DD; + +// PASS PLL data descriptor length in bytes +#define C66XX_PASS_PLL_DD_LEN sizeof(C66XX_PASS_PLL_DD) + + +/*------------ C66XX_SYS_get_core_number() function ----------------------*//** + * @brief Function returns DSP core number at which the program is running + * + * @return DSP core number + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_SYS_get_core_number(void); + + +/*------------ C66XX_SYS_get_max_core_freq() function --------------------*//** + * @brief Function returns DSP core max speed in MHz + * + * @return DSP core max speed in MHz + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_SYS_get_max_core_freq(void); + + +/*------------ C66XX_SYS_set_core_reset_state() function -----------------*//** + * @brief Function sets or releases DSP core local reset + * + * @param[in] core - DSP core number to set or release from local reset + * @param[in] state - DSP core local reset state: ON or OFF + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_set_core_reset_state(uint32_t core, uint32_t state); + + +/*------------ C66XX_SYS_get_core_reset_state() function -----------------*//** + * @brief Function returns DSP core local reset state + * + * @param[in] core - DSP core number to return local reset state + * @param[out] state - pointer to a variable to receive DSP core local reset + * state: ON or OFF + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_core_reset_state(uint32_t core, uint32_t *state); + + +/*------------ C66XX_SYS_get_core_reset_source() function ----------------*//** + * @brief Function returns DSP core reset source: global or local + * + * @param[in] core - DSP core number to return reset source + * @param[out] state - pointer to a variable to receive DSP core reset source: + * global or local + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_core_reset_source(uint32_t core, uint32_t *source); + + +/*------------ C66XX_SYS_set_core_boot_address() function ----------------*//** + * @brief Function sets DSP core boot address. After releasing DSP core from + * reset it will start execution from this memory address. + * Note that DSP core boot address should be 1024 bytes aligned + * + * @param[in] core - DSP core number to set boot address + * @param[in] addr - DSP core boot address: should be 1024 bytes aligned + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_set_core_boot_address(uint32_t core, uint32_t addr); + + +/*------------ C66XX_SYS_init_main_pll() function ------------------------*//** + * @brief Function inits DSP Main PLL according to supplied parameters + * + * @param[in] pll_dd - Main PLL data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_init_main_pll(C66XX_MAIN_PLL_DD *pll_dd); + + +/*------------ C66XX_SYS_get_main_pll_settings() function ----------------*//** + * @brief Function returns DSP Main PLL settings + * + * @param[out] pll_dd - Pointer to a main PLL data descriptor to receive data + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_main_pll_settings(C66XX_MAIN_PLL_DD *pll_dd); + + +/*------------ C66XX_SYS_init_ddr3_pll() function ------------------------*//** + * @brief Function inits DSP DDR3 PLL according to supplied parameters + * + * @param[in] ddr3_pll_dd - DDR3 PLL data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_init_ddr3_pll(C66XX_DDR3_PLL_DD *ddr3_pll_dd); + + +/*------------ C66XX_SYS_get_ddr3_pll_settings() function ----------------*//** + * @brief Function returns DSP DDR3 PLL settings + * + * @param[out] ddr3_pll_dd - Pointer to DDR3 PLL data descriptor to receive +* data + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_ddr3_pll_settings(C66XX_DDR3_PLL_DD *ddr3_pll_dd); + + +/*------------ C66XX_SYS_init_pass_pll() function ------------------------*//** + * @brief Function inits DSP PASS PLL according to supplied parameters + * + * @param[in] pass_pll_dd - PASS PLL data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_init_pass_pll(C66XX_PASS_PLL_DD *pass_pll_dd); + + +/*------------ C66XX_SYS_get_pass_pll_settings() function ----------------*//** + * @brief Function returns DSP PASS PLL settings + * + * @param[out] pass_pll_dd - Pointer to PASS PLL data descriptor to receive +* data + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_pass_pll_settings(C66XX_PASS_PLL_DD *pass_pll_dd); + + +/*------------ C66XX_SYS_enable_power_domain() function ------------------*//** + * @brief Function powers up selected power domain + * + * @param[in] domain - power domain number to enable + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_enable_power_domain(uint32_t domain); + + +/** @}*/ +//============================================================================= + + +//============================================================================= +//============ DSP memory controller functions ================================ +//============================================================================= + +/** @addtogroup C66XX_MEM DSP memory controller functions + * @{ + */ + + +/** DSP L1 (P or D) cache sizes */ +#define C66XX_CACHE_L1_0KB CACHE_L1_0KCACHE +#define C66XX_CACHE_L1_4KB CACHE_L1_4KCACHE +#define C66XX_CACHE_L1_8KB CACHE_L1_8KCACHE +#define C66XX_CACHE_L1_16KB CACHE_L1_16KCACHE +#define C66XX_CACHE_L1_32KB CACHE_L1_32KCACHE +#define C66XX_CACHE_L1_MAX_SIZE CACHE_L1_MAXIM3 + + +/** DSP L2 cache sizes */ +#define C66XX_CACHE_L2_0KB CACHE_0KCACHE +#define C66XX_CACHE_L2_32KB CACHE_32KCACHE +#define C66XX_CACHE_L2_64KB CACHE_64KCACHE +#define C66XX_CACHE_L2_128KB CACHE_128KCACHE +#define C66XX_CACHE_L2_256KB CACHE_256KCACHE +#define C66XX_CACHE_L2_512KB CACHE_512KCACHE +#define C66XX_CACHE_L2_MAX_SIZE C66XX_CACHE_L2_512KB + + +/** DDR3 controller initialization data descriptor (contains parameters which are used to init DDR3 controller) */ +typedef struct +{ + EMIF4F_TIMING1_CONFIG timing1_config; /**< DDR3 controller Timing 1 configuration */ + EMIF4F_TIMING2_CONFIG timing2_config; /**< DDR3 controller Timing 2 configuration */ + EMIF4F_TIMING3_CONFIG timing3_config; /**< DDR3 controller Timing 3 configuration */ + EMIF4F_SDRAM_CONFIG sdram_config; /**< DDR3 controller SDRAM configuration */ +} C66XX_DDR3_EMIF_DD; + +// DDR3 controller initialization data descriptor length in bytes +#define C66XX_DDR3_EMIF_DD_LEN sizeof(C66XX_DDR3_EMIF_DD) + + +/** DDR3 controller physical interface (PHY) data descriptor (contains parameters which are used to perform leveling) */ +// All these values should be obtained from DDR3 PHY Calc spreadsheet (sprabl2) provided by TI +typedef struct +{ + uint32_t data0_wrlvl_init_ratio; /**< DDR3 byte lane 7 write leveling initialization ratio */ + uint32_t data1_wrlvl_init_ratio; /**< DDR3 byte lane 6 write leveling initialization ratio */ + uint32_t data2_wrlvl_init_ratio; /**< DDR3 byte lane 5 write leveling initialization ratio */ + uint32_t data3_wrlvl_init_ratio; /**< DDR3 byte lane 4 write leveling initialization ratio */ + uint32_t data4_wrlvl_init_ratio; /**< DDR3 byte lane 3 write leveling initialization ratio */ + uint32_t data5_wrlvl_init_ratio; /**< DDR3 byte lane 2 write leveling initialization ratio */ + uint32_t data6_wrlvl_init_ratio; /**< DDR3 byte lane 1 write leveling initialization ratio */ + uint32_t data7_wrlvl_init_ratio; /**< DDR3 byte lane 0 write leveling initialization ratio */ + uint32_t data8_wrlvl_init_ratio; /**< DDR3 ECC byte lane write leveling initialization ratio */ + uint32_t data0_gatelvl_init_ratio; /**< DDR3 byte lane 7 gate leveling initialization ratio */ + uint32_t data1_gatelvl_init_ratio; /**< DDR3 byte lane 6 gate leveling initialization ratio */ + uint32_t data2_gatelvl_init_ratio; /**< DDR3 byte lane 5 gate leveling initialization ratio */ + uint32_t data3_gatelvl_init_ratio; /**< DDR3 byte lane 4 gate leveling initialization ratio */ + uint32_t data4_gatelvl_init_ratio; /**< DDR3 byte lane 3 gate leveling initialization ratio */ + uint32_t data5_gatelvl_init_ratio; /**< DDR3 byte lane 2 gate leveling initialization ratio */ + uint32_t data6_gatelvl_init_ratio; /**< DDR3 byte lane 1 gate leveling initialization ratio */ + uint32_t data7_gatelvl_init_ratio; /**< DDR3 byte lane 0 gate leveling initialization ratio */ + uint32_t data8_gatelvl_init_ratio; /**< DDR3 ECC byte lane gate leveling initialization ratio */ + uint32_t ddr3_config_reg_12_bitmask; /**< DDR3 configuration 12 register bitmask for INVERT_CLK_OUT field */ +} C66XX_DDR3_PHY_DD; + +// DDR3 controller initialization data descriptor length in bytes +#define C66XX_DDR3_PHY_DD_LEN sizeof(C66XX_DDR3_PHY_DD) + + +/*------------ C66XX_MEM_set_L1P_cache_size() function -------------------*//** + * @brief Function sets DSP L1P cache to the new size + * + * @param[in] new_size - new size of DSP L1P cache + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_MEM_set_L1P_cache_size(uint32_t new_size); + + +/*------------ C66XX_MEM_get_L1P_cache_size() function -------------------*//** + * @brief Function returns DSP L1P cache size + * + * @return DSP L1P cache size + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_get_L1P_cache_size() CACHE_getL1PSize() + + +/*------------ C66XX_MEM_set_L1D_cache_size() function -------------------*//** + * @brief Function sets DSP L1D cache to the new size + * + * @param[in] new_size - new size of DSP L1D cache + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_MEM_set_L1D_cache_size(uint32_t new_size); + + +/*------------ C66XX_MEM_get_L1D_cache_size() function -------------------*//** + * @brief Function returns DSP L1D cache size + * + * @return DSP L1D cache size + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_get_L1D_cache_size() CACHE_getL1DSize() + + +/*------------ C66XX_MEM_set_L2_cache_size() function --------------------*//** + * @brief Function sets DSP L2 cache to the new size + * + * @param[in] new_size - new size of DSP L2 cache + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_MEM_set_L2_cache_size(uint32_t new_size); + + +/*------------ C66XX_MEM_get_L2_cache_size() function --------------------*//** + * @brief Function returns DSP L2 cache size + * + * @return DSP L2 cache size + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_get_L2_cache_size() CACHE_getL2Size() + + +/*------------ C66XX_MEM_set_memory_region_cache_config() function -------*//** + * @brief Function enables or disables DSP caching for specified memory region + * + * @param[in] mar - MAR register number from 0 to 255 (note that the first 12 + * memory regions are read-only) + * @param[in] cacheable - cache mode to set: ON - enable caching, + * OFF - disable caching + * @param[in] prefetchable - DSP XMC controller prefetch mode to set: + * ON - enable prefetch support, OFF - disable prefetch support + * + * @return None + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_set_memory_region_cache_config(mar, cacheable, prefetchable) CACHE_setMemRegionInfo(mar, cacheable, prefetchable) + + +/*------------ C66XX_MEM_get_memory_region_cache_config() function -------*//** + * @brief Function returns DSP cache configuration for specified memory region + * + * @param[in] mar - MAR register number from 0 to 255 (note that the first 12 + * memory regions are read-only) + * @param[in] cacheable - pointer to a variable to receive current cache mode: + * ON - caching is enabled, OFF - caching is disabled + * @param[in] prefetchable - pointer to a variable to receive current DSP XMC + * controller prefetch mode: ON - prefetch support is enabled, + * OFF - prefetch support is disabled + * + * @return None + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_get_memory_region_cache_config(mar, cacheable, prefetchable) CACHE_getMemRegionInfo(mar, cacheable, prefetchable) + + +/*------------ C66XX_MEM_init_xmc_mpax_segment() function ----------------*//** + * @brief Function configures XMC MPAX segment according to supplied + * parameters + * + * @param[in] index - MPAX segment index from 0 to 15 (note that the first 2 + * segments are already configured by default) + * @param[in] baddr - upper 20 bit of base 32-bit address to remap + * @param[in] size - encoded segment size + * @param[in] raddr - upper 24 bit of replacement 36-bit address + * @param[in] perm - access types allowed in this segment + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_MEM_init_xmc_mpax_segment(uint32_t index, uint32_t baddr, uint32_t size, uint32_t raddr, uint32_t perm); + + +/*------------ C66XX_MEM_convert_local_to_global_address() function ------*//** + * @brief Function converts local DSP core address to global address + * + * @param[in] addr - local DSP core address to be converted + * + * @return Global address + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_MEM_convert_local_to_global_address(uint32_t addr); + + +/*------------ C66XX_MEM_init_ddr3() function --------------------------------*//** + * @brief Function inits DDR3 controller according to supplied parameters + * + * @param[in] ddr3_emif_dd - DDR3 controller initialization data descriptor + * @param[in] ddr3_phy_dd - DDR3 PHY controller initialization data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_MEM_init_ddr3(C66XX_DDR3_EMIF_DD *ddr3_emif_dd, C66XX_DDR3_PHY_DD *ddr3_phy_dd); + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Timer TSC functions ============================================ +//============================================================================= + +/** @addtogroup C66XX_TSC DSP 64-bit Time Stamp Counter (TSC) functions + * @{ + */ + +/*------------ C66XX_TSC_get_current_value() function --------------------*//** + * @brief Function returns DSP TSC current value + * + * @return 64-bit Time Stamp Counter value + * +-----------------------------------------------------------------------------*/ +uint64_t C66XX_TSC_get_current_value(void); + + +/*------------ C66XX_TSC_get_duration_s() function -----------------------*//** + * @brief Function returns time duration in seconds from Time Stamp Counter + * start value + * + * @param[in] start - 64-bit Time Stamp Counter value + * + * @return Time duration in seconds + * +-----------------------------------------------------------------------------*/ +double C66XX_TSC_get_duration_s(uint64_t start); + + +/*------------ C66XX_TSC_set_delay_us() function -------------------------*//** + * @brief Function is used to delay the execution for selected number of + * microseconds + * + * @param[in] us - Number of microseconds to delay + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_TSC_set_delay_us(uint32_t us); + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ C66xx interrupt controller functions =========================== +//============================================================================= + +/** @addtogroup C66XX_INT C66xx interrupt controller functions + * @{ + */ + + +/** DSP interrupt vector IDs */ +#define C66XX_DSP_VECTID_NMI CSL_INTC_VECTID_NMI +#define C66XX_DSP_VECTID_4 CSL_INTC_VECTID_4 +#define C66XX_DSP_VECTID_5 CSL_INTC_VECTID_5 +#define C66XX_DSP_VECTID_6 CSL_INTC_VECTID_6 +#define C66XX_DSP_VECTID_7 CSL_INTC_VECTID_7 +#define C66XX_DSP_VECTID_8 CSL_INTC_VECTID_8 +#define C66XX_DSP_VECTID_9 CSL_INTC_VECTID_9 +#define C66XX_DSP_VECTID_10 CSL_INTC_VECTID_10 +#define C66XX_DSP_VECTID_11 CSL_INTC_VECTID_11 +#define C66XX_DSP_VECTID_12 CSL_INTC_VECTID_12 +#define C66XX_DSP_VECTID_13 CSL_INTC_VECTID_13 +#define C66XX_DSP_VECTID_14 CSL_INTC_VECTID_14 +#define C66XX_DSP_VECTID_15 CSL_INTC_VECTID_15 +#define C66XX_DSP_VECTID_COMBINE CSL_INTC_VECTID_COMBINE +#define C66XX_DSP_VECTID_EXCEP CSL_INTC_VECTID_EXCEP + + +/*------------ C66XX_INT_init_core() function ----------------------------*//** + * @brief Function initializes C66x CorePac interrupt controller (INTC) using + * CSL library. + * + * If SYS/BIOS RTOS is used, then it's recommended to use the relevant + * SYS/BIOS interrupt API (HWI, EventCombiner and CpIntc), as there will be + * conflicts since both CSL and SYS/BIOS will use their own Interrupt Service + * Table Pointer (ISTP). + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_init_core(void); + + +/*------------ C66XX_INT_map_core_event_handler() function ---------------*//** + * @brief Function maps DSP interrupt vector to INTC input event ID, plugs + * the specified function as DSP interrupt handler function, and enables DSP + * interrupt + * + * @param[in] dsp_vector_id - DSP interrupt vector + * @param[in] input_event_id - INTC input event ID + * @param[in] handler - pointer to DSP interrupt handler function + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_map_core_event_handler(uint32_t dsp_vector_id, uint32_t input_event_id, CSL_IntcEventHandler handler); + + +/*------------ C66XX_INT_unmap_core_event_handler() function -------------*//** + * @brief Function unmaps DSP interrupt vector and disables the corresponding + * DSP interrupt. + * + * @param[in] dsp_vector_id - DSP interrupt vector + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_unmap_core_event_handler(uint32_t dsp_vector_id); + + +/*------------ C66XX_INT_set_core_dsp_interrupt_handler() function -------*//** + * @brief Function sets the specified function as a direct handler for DSP + * interrupt vector ID. + * + * This handler function will be branched to from DSP interrupt vector table + * for specified DSP interrupt vector ID, so either it should be declared in C + * with "interrupt" keyword or manually save and restore interrupt context and + * return with "B IRP" assembler instruction. + * The specified DSP interrupt will be enabled too. + * + * @param[in] dsp_vector_id - DSP interrupt vector + * @param[in] isr_handler - direct handler function for DSP interrupt vector + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_set_core_dsp_interrupt_handler(uint32_t dsp_vector_id, void *isr_handler); + + +/** Chip interrupt controllers defs */ +#define C66XX_CPINTC_ID_0 0 +#define C66XX_CPINTC_ID_1 1 +#define C66XX_CPINTC_ID_2 2 +#define C66XX_CPINTC_ID_3 3 + + +/*------------ C66XX_INT_init_chip() function ----------------------------*//** + * @brief Function initializes the specified chip interrupt controller + * (CPINTC or CIC) and returns a handle which should be used in all subsequent + * CPINTC function calls. + * + * @param[in] cpintc_id - chip interrupt controller number to initialize (0-3) + * + * @return Handle to the CPINTC instance: >0 - OK, + * 0 - error is occurred + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_INT_init_chip(uint32_t cpintc_id); + + +/*------------ C66XX_INT_map_chip_system_to_host_event() function --------*//** + * @brief Function maps chip-level event (system event) to CPINTC output event + * (host event) end enables it. + * + * System events are those events generated by a hardware module in the system. + * These events are inputs into CPINTC. + * Host events are the output events of CPINTC, which act as event inputs to + * C66x CorePac interrupt controllers (INTC). + * + * @param[in] cpintc_handle - chip interrupt controller handle returned by + * C66XX_init_cpintc() function call; + * @param[in] system_event_id - chip-level (system) event from a hardware + * module in the system. + * @param[in] host_event_id - CPINTC output event ID + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_map_chip_system_to_host_event(uint32_t cpintc_handle, uint32_t system_event_id, uint32_t host_event_id); + + +/*------------ C66XX_INT_enable_chip_host_event() function ---------------*//** + * @brief Function enables CPINTC output event (host event). + * + * @param[in] cpintc_handle - chip interrupt controller handle returned by + * C66XX_init_cpintc() function call; + * @param[in] host_event_id - CPINTC output event ID to enable + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +#define C66XX_INT_enable_chip_host_event(cpintc_handle, host_event_id) CSL_CPINTC_enableHostInterrupt(cpintc_handle, host_event_id) + + +/*------------ C66XX_INT_disable_chip_host_event() function --------------*//** + * @brief Function disables CPINTC output event (host event). + * + * @param[in] cpintc_handle - chip interrupt controller handle returned by + * C66XX_init_cpintc() function call; + * @param[in] host_event_id - CPINTC output event ID to disable + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +#define C66XX_INT_disable_chip_host_event(cpintc_handle, host_event_id) CSL_CPINTC_disableHostInterrupt(cpintc_handle, host_event_id) + + +/*------------ C66XX_INT_clear_chip_system_event() function --------------*//** + * @brief Function clears CPINTC input event (system event). + * + * @param[in] cpintc_handle - chip interrupt controller handle returned by + * C66XX_init_cpintc() function call; + * @param[in] sys_event_id - CPINTC input event ID to clear + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +#define C66XX_INT_clear_chip_system_event(cpintc_handle, sys_event_id) CSL_CPINTC_clearSysInterrupt(cpintc_handle, sys_event_id) + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ General purpose I/O (GPIO) functions =========================== +//============================================================================= + +/** @addtogroup C66XX_GPIO DSP GPIO functions + * @{ + */ + +/** GPIO pins number defs */ +enum C66XX_GPIO_PINS +{ + C66XX_GPIO_PIN_0 = 0, + C66XX_GPIO_PIN_1, + C66XX_GPIO_PIN_2, + C66XX_GPIO_PIN_3, + C66XX_GPIO_PIN_4, + C66XX_GPIO_PIN_5, + C66XX_GPIO_PIN_6, + C66XX_GPIO_PIN_7, + C66XX_GPIO_PIN_8, + C66XX_GPIO_PIN_9, + C66XX_GPIO_PIN_10, + C66XX_GPIO_PIN_11, + C66XX_GPIO_PIN_12, + C66XX_GPIO_PIN_13, + C66XX_GPIO_PIN_14, + C66XX_GPIO_PIN_15 +}; + +/** GPIO pins bitmask defs */ +enum C66XX_GPIO_PIN_BITMASKS +{ + C66XX_GPIO_PIN_0_BITMASK = 0x0001, + C66XX_GPIO_PIN_1_BITMASK = 0x0002, + C66XX_GPIO_PIN_2_BITMASK = 0x0004, + C66XX_GPIO_PIN_3_BITMASK = 0x0008, + C66XX_GPIO_PIN_4_BITMASK = 0x0010, + C66XX_GPIO_PIN_5_BITMASK = 0x0020, + C66XX_GPIO_PIN_6_BITMASK = 0x0040, + C66XX_GPIO_PIN_7_BITMASK = 0x0080, + C66XX_GPIO_PIN_8_BITMASK = 0x0100, + C66XX_GPIO_PIN_9_BITMASK = 0x0200, + C66XX_GPIO_PIN_10_BITMASK = 0x0400, + C66XX_GPIO_PIN_11_BITMASK = 0x0800, + C66XX_GPIO_PIN_12_BITMASK = 0x1000, + C66XX_GPIO_PIN_13_BITMASK = 0x2000, + C66XX_GPIO_PIN_14_BITMASK = 0x4000, + C66XX_GPIO_PIN_15_BITMASK = 0x8000 +}; + + +/** GPIO bank number for CSL utilities */ +#define C66XX_GPIO_BANK_NUMBER 0 +/** GPIO data definitions */ +#define C66XX_GPIO_DATA_OFF 0 +#define C66XX_GPIO_DATA_ON 1 +/** GPIO direction definitions */ +#define C66XX_GPIO_DIR_OUT 0 +#define C66XX_GPIO_DIR_IN 1 +/** GPIO pin edge defs */ +#define C66XX_GPIO_PIN_EDGE_RISING 0 +#define C66XX_GPIO_PIN_EDGE_FALLING 1 +#define C66XX_GPIO_PIN_EDGE_ANY 2 +/** GPIO pins bitmask definitions */ +#define C66XX_GPIO_DATA_BITMASK 0x0000ffff + + +/*------------ C66XX_GPIO_init() function --------------------------------*//** + * @brief Function inits the GPIO peripheral: all pins are configured as + * inputs, interrupts are disabled + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_GPIO_init(void); + + +/*------------ C66XX_GPIO_set_pin_direction() function -------------------*//** + * @brief Function configures the specified GPIO pin direction + * + * @param[in] pin_number - GPIO pin number to configure + * @param[in] direction - GPIO direction definition + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_set_pin_direction(uint32_t pin_number, uint32_t direction); + + +/*------------ C66XX_GPIO_get_pin_direction() function -------------------*//** + * @brief Function returns the specified GPIO pin direction + * + * @param[in] pin_number - GPIO pin number to get direction + * + * @return GPIO direction definition + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_GPIO_get_pin_direction(uint32_t pin_number); + + +/*------------ C66XX_GPIO_set_pin_data() function ------------------------*//** + * @brief Function sets the specified GPIO pin state to data + * + * @param[in] pin_number - GPIO pin number to configure + * @param[in] data - GPIO pin state: ON or OFF + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_set_pin_data(uint32_t pin_number, uint32_t data); + + +/*------------ C66XX_GPIO_get_pin_data() function ------------------------*//** + * @brief Function returns the specified GPIO pin state + * + * @param[in] pin_number - GPIO pin number to get pin state + * + * @return GPIO pin state: ON or OFF + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_GPIO_get_pin_data(uint32_t pin_number); + + +/*------------ C66XX_GPIO_set_direction() function -----------------------*//** + * @brief Function configures the specified GPIO pins direction + * + * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to configure + * @param[in] direction - GPIO direction definition + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_set_direction(uint32_t pin_bitmask, uint32_t direction); + + +/*------------ C66XX_GPIO_get_direction() function -----------------------*//** + * @brief Function returns the specified GPIO pins direction + * + * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to get pins direction + * + * @return Specified GPIO pins direction + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_GPIO_get_direction(uint32_t pin_bitmask); + + +/*------------ C66XX_GPIO_set_data() function ----------------------------*//** + * @brief Function sets the specified GPIO pins state to data + * + * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to configure + * @param[in] data - GPIO pins state: ON or OFF + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_set_data(uint32_t pin_bitmask, uint32_t data); + + +/*------------ C66XX_GPIO_get_data() function ----------------------------*//** + * @brief Function returns the specified GPIO pins state + * + * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to get pins state + * + * @return Specified GPIO pins state + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_GPIO_get_data(uint32_t pin_bitmask); + + +/*------------ C66XX_GPIO_enable_interrupts() function -------------------*//** + * @brief Function enables GPIO peripheral interrupts + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_enable_interrupts(void); + + +/*------------ C66XX_GPIO_disable_interrupts() function ------------------*//** + * @brief Function disables GPIO peripheral interrupts + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_disable_interrupts(void); + + +/*------------ C66XX_GPIO_enable_edge_interrupt() function ---------------*//** + * @brief Function enables the specified GPIO pin edge interrupt + * + * @param[in] pin - GPIO pin number to configure + * @param[in] edge - GPIO pin edge which triggers GPIO interrupt + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_enable_edge_interrupt(uint32_t pin, uint32_t edge); + + +/*------------ C66XX_GPIO_disable_edge_interrupt() function --------------*//** + * @brief Function disables the specified GPIO pin edge interrupt + * + * @param[in] pin - GPIO pin number to configure + * @param[in] edge - GPIO pin edge which shouldn't trigger GPIO interrupt + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_disable_edge_interrupt(uint32_t pin, uint32_t edge); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Timer module functions ========================================= +//============================================================================= + +/** @addtogroup C66XX_TIMER DSP 64-bit Timer module functions + * @{ + */ + + +/** DSP 64-bit Timer module number defs */ +typedef enum +{ + C66XX_TIMER_0 = 0, + C66XX_TIMER_1, + C66XX_TIMER_2, + C66XX_TIMER_3, + C66XX_TIMER_4, + C66XX_TIMER_5, + C66XX_TIMER_6, + C66XX_TIMER_7, + C66XX_TIMER_8, + C66XX_TIMER_9, + C66XX_TIMER_10, + C66XX_TIMER_11, + C66XX_TIMER_12, + C66XX_TIMER_13, + C66XX_TIMER_14, + C66XX_TIMER_15 +} C66XX_TIMER; + + +/** DSP 64-bit Timer mode defs */ +typedef enum +{ + C66XX_TIMER_MODE_64BIT_GPT = 0, + C66XX_TIMER_MODE_32BIT_UNCHAINED, + C66XX_TIMER_MODE_64BIT_WDT, + C66XX_TIMER_MODE_32BIT_CHAINED +} C66XX_TIMER_MODE; + + +/** DSP 64-bit Timer hardware configuration defs */ +typedef enum +{ + C66XX_TIMER_HW_CFG_64BIT = 0, + C66XX_TIMER_HW_CFG_32BIT_LOW, + C66XX_TIMER_HW_CFG_32BIT_HIGH +} C66XX_TIMER_HW_CFG; + + +/** DSP 64-bit Timer count mode defs */ +typedef enum +{ + C66XX_TIMER_COUNT_MODE_DISABLED = 0, + C66XX_TIMER_COUNT_MODE_ONE_SHOT, + C66XX_TIMER_COUNT_MODE_CONTINUOUSLY, + C66XX_TIMER_COUNT_MODE_CONTINUOUSLY_RELOAD +} C66XX_TIMER_COUNT_MODE; + + +/** DSP timer input enable defs */ +typedef enum +{ + C66XX_TIMER_CLK_INPUT_DISABLED = 0, + C66XX_TIMER_CLK_INPUT_ENABLED +} C66XX_TIMER_CLK_INPUT; + + +/** DSP timer input inverter control defs */ +typedef enum +{ + C66XX_TIMER_CLK_INPUT_INVERTER_DISABLED = 0, + C66XX_TIMER_CLK_INPUT_INVERTER_ENABLED +} C66XX_TIMER_CLK_INPUT_INVERTER; + + +/** DSP timer clock source defs */ +typedef enum +{ + C66XX_TIMER_CLK_SRC_INTERNAL = 0, + C66XX_TIMER_CLK_SRC_EXTERNAL +} C66XX_TIMER_CLK_SRC; + + +/** DSP timer clock/pulse mode for timer output defs */ +typedef enum +{ + C66XX_TIMER_CLK_OUTPUT_MODE_PULSE = 0, + C66XX_TIMER_CLK_OUTPUT_MODE_CLK +} C66XX_TIMER_CLK_OUTPUT_MODE; + + +/** DSP timer pulse width used in pulse mode for timer output defs */ +typedef enum +{ + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_1CLK = 0, + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_2CLK, + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_3CLK, + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_4CLK +} C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH; + + +/** DSP timer output inverter control defs */ +typedef enum +{ + C66XX_TIMER_CLK_OUTPUT_INVERTER_DISABLED = 0, + C66XX_TIMER_CLK_OUTPUT_INVERTER_ENABLED +} C66XX_TIMER_CLK_OUTPUT_INVERTER; + + +/** DSP 32-bit Timer configuration data descriptor */ +typedef struct +{ + C66XX_TIMER_CLK_SRC clk_src; /**< Clock source for 32-bit timer */ + C66XX_TIMER_CLK_INPUT clk_input_enabled; /**< Timer clock is gated by the timer input for 32-bit timer */ + C66XX_TIMER_CLK_INPUT_INVERTER clk_input_inverter_enabled; /**< An inverted timer input drives the 32-bit timer */ + C66XX_TIMER_CLK_OUTPUT_MODE clk_src_output_mode; /**< Clock output mode for 32-bit timer */ + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH clk_src_output_pulse_width; /**< Clock output pulse width used in pulse mode for 32-bit timer */ + C66XX_TIMER_CLK_OUTPUT_INVERTER clk_output_inverter_enabled; /**< 32-bit timer output is inverted */ +} C66XX_TIMER_32BIT_CFG_DD; + + +/** DSP 64-bit Timer module configuration data descriptor */ +typedef struct +{ + C66XX_TIMER_MODE timer_mode; /**< Timer mode: 64-bit GPT, 64-bit WDT, dual 32-bit unchained or chained */ + C66XX_TIMER_32BIT_CFG_DD timer_high; /**< Configuration data descriptor for 32-bit HIGH timer */ + C66XX_TIMER_32BIT_CFG_DD timer_low; /**< Configuration data descriptor for 32-bit LOW timer */ +} C66XX_TIMER_CFG_DD; + +// DSP 64-bit Timer module configuration data descriptor length in bytes +#define C66XX_TIMER_CFG_DD_LEN sizeof(C66XX_TIMER_CFG_DD) + + +/*------------ C66XX_TIMER_init() function -------------------------------*//** + * @brief Function configures selected DSP 64-bit timer module + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] frequency - DSP timer output frequency in Hz + * @param[in] cfg_dd - pointer to filled DSP 64-bit timer module configuration + * data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_init(C66XX_TIMER timer_number, uint32_t frequency, C66XX_TIMER_CFG_DD *cfg_dd); + + +/*------------ C66XX_TIMER_start() function ------------------------------*//** + * @brief Function starts selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_start - hardware timer to start (64BIT/32BIT_LOW/ + * 32BIT_HIGH) + * @param[in] count_mode - DSP timer counting mode (DISABLED/ONE_SHOT/ + * CONTINUOUSLY/CONTINUOUSLY_RELOAD) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_start(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_start, C66XX_TIMER_COUNT_MODE count_mode); + + +/*------------ C66XX_TIMER_stop() function -------------------------------*//** + * @brief Function stops selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_stop - hardware timer to stop (64BIT/32BIT_LOW/ + * 32BIT_HIGH) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_stop(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_stop); + + +/*------------ C66XX_TIMER_reset() function ------------------------------*//** + * @brief Function resets selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_reset - hardware timer to reset (64BIT/32BIT_LOW/ + * 32BIT_HIGH) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_reset(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_reset); + + +/*------------ C66XX_TIMER_enable_interrupts() function ------------------*//** + * @brief Function enables interrupts from selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_enable - hardware timer to enable interrupts from + * (64BIT/32BIT_LOW/32BIT_HIGH) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_enable_interrupts(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_enable); + + +/*------------ C66XX_TIMER_disable_interrupts() function ------------------*//** + * @brief Function disables interrupts from selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_disable - hardware timer to disable interrupts from + * (64BIT/32BIT_LOW/32BIT_HIGH) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_disable_interrupts(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_disable); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ UART functions ================================================= +//============================================================================= + +/** @addtogroup C66XX_UART DSP UART functions + * @{ + */ + +// UART baud rate defs (max 128 kBauds) +#define C66XX_UART_BAUD_RATE_2400 2400 /**< UART baud rate 2400 bps */ +#define C66XX_UART_BAUD_RATE_4800 4800 /**< UART baud rate 4800 bps */ +#define C66XX_UART_BAUD_RATE_9600 9600 /**< UART baud rate 9600 bps */ +#define C66XX_UART_BAUD_RATE_19200 19200 /**< UART baud rate 19200 bps */ +#define C66XX_UART_BAUD_RATE_38400 38400 /**< UART baud rate 38400 bps */ +#define C66XX_UART_BAUD_RATE_57600 57600 /**< UART baud rate 57600 bps */ +#define C66XX_UART_BAUD_RATE_115200 115200 /**< UART baud rate 115200 bps */ + +// UART data bits defs +#define C66XX_UART_DATA_BITS_5BITS 5 /**< UART 5-bits data words */ +#define C66XX_UART_DATA_BITS_6BITS 6 /**< UART 6-bits data words */ +#define C66XX_UART_DATA_BITS_7BITS 7 /**< UART 7-bits data words */ +#define C66XX_UART_DATA_BITS_8BITS 8 /**< UART 8-bits data words */ + +// UART parity parameter defs +#define C66XX_UART_PARITY_NONE 0 /**< no parity */ +#define C66XX_UART_PARITY_EVEN 1 /**< even parity */ +#define C66XX_UART_PARITY_ODD 2 /**< odd parity */ + +// UART stop bits defs +#define C66XX_UART_STOP_BITS_1BIT 0 /**< one stop bit */ +#define C66XX_UART_STOP_BITS_1_5BITS 1 /**< one and a half stop bits */ +#define C66XX_UART_STOP_BITS_2BITS 2 /**< two stop bits */ + +// UART key defs +#define C66XX_UART_KEY_BEEP 0x7 /**< BELL value in HEX */ +#define C66XX_UART_KEY_ESC 0x1b /**< ESC value in HEX */ +#define C66XX_UART_KEY_CR 0xd /**< Carriage Return value in HEX */ +#define C66XX_UART_KEY_BS 0x8 /**< Back space value in HEX */ +#define C66XX_UART_LINE_LEN_MAX 80 /**< Maximum available received line length */ + + + +/*------------ C66XX_UART_init() function --------------------------------*//** + * @brief Function inits the UART peripheral + * + * @param[in] core_clk - DSP core clock frequency in MHz; + * @param[in] baud_rate - desired baud rate; + * @param[in] data_bits - number of data bits; + * @param[in] parity - parity bit; + * @param[in] stop_bits - number of stop bits; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_UART_init(uint32_t core_clk, uint32_t baud_rate, uint32_t data_bits, uint32_t parity, uint32_t stop_bits); + + +/*------------ C66XX_UART_receiver_is_ready() function -------------------*//** + * @brief Function checks if a character is received over UART + * + * @return 1 - a character is received over UART, + * 0 - otherwise + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_UART_receiver_is_ready(void); + + +/*------------ C66XX_UART_receive_char() function ------------------------*//** + * @brief Function receives a character over UART + * + * @return Received character + * +-----------------------------------------------------------------------------*/ +uint8_t C66XX_UART_receive_char(void); + + +/*------------ C66XX_UART_transmit_char() function -----------------------*//** + * @brief Function transmits a character over UART + * + * @param[in] c - A character to transmit + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_UART_transmit_char(uint8_t c); + + +/*------------ C66XX_UART_transmit_string() function ---------------------*//** + * @brief Function transmits a string until '0' character + * + * @param[in] s - A pointer to the string to transmit + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_UART_transmit_string(char *s); + + +/*------------ C66XX_UART_receive_line_string() function -----------------*//** + * @brief Function receives a line ended with CR character, and stores + * received characters into string with '\0' symbol. + * + * Note that maximum received line length should not exceed + * C66XX_UART_LINE_LEN_MAX value! + * + * @param[in] s - Pointer to a string to store received characters + * + * @return Number of received characters without '\0' symbol. + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_UART_receive_line_string(char *s); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ I2C functions ================================================== +//============================================================================= + +/** @addtogroup C66XX_I2C DSP I2C functions + * @{ + */ + + +// I2C interrupt codes +#define C66XX_I2C_INTCODE_NONE 0 /**< No interrupt */ +#define C66XX_I2C_INTCODE_AL 1 /**< Arbitration-lost interrupt */ +#define C66XX_I2C_INTCODE_NACK 2 /**< No-acknowledge interrupt */ +#define C66XX_I2C_INTCODE_ARDY 3 /**< Register-access-ready interrupt */ +#define C66XX_I2C_INTCODE_ICRRDY 4 /**< Receive-data-ready interrupt */ +#define C66XX_I2C_INTCODE_ICXRDY 5 /**< Transmit-data-ready interrupt */ +#define C66XX_I2C_INTCODE_SCD 6 /**< Stop-condition-detected interrupt */ +#define C66XX_I2C_INTCODE_AAS 7 /**< Address-as-slave interrupt */ + + +/*------------ C66XX_I2C_init() function ---------------------------------*//** + * @brief Function inits the I2C peripheral + * + * @param[in] core_clk - DSP core clock frequency in MHz; + * @param[in] i2c_clk - I2C clock in Hz; + * @param[in] own_addr - I2C own slave address; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_I2C_init(uint32_t core_clk, uint32_t i2c_clk, uint32_t own_addr); + + +/*------------ C66XX_I2C_write_data() function ---------------------------*//** + * @brief Function writes data[len] to I2C chip_addr at mem_addr memory + * address + * + * @param[in] chip_addr - I2C chip address; + * @param[in] mem_addr - memory (register) address within the chip; + * @param[in] mem_addr_len - number of bytes to use for mem_addr (typically 1, + * 2 for larger memories, 0 for register type devices with only + * one register); + * @param[in] data - pointer to data; + * @param[in] len - data len in bytes; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_I2C_write_data(uint8_t chip_addr, uint32_t mem_addr, uint32_t mem_addr_len, uint8_t *data, uint32_t len); + + +/*------------ C66XX_I2C_read_data() function ----------------------------*//** + * @brief Function reads data[len] from I2C chip_addr at mem_addr memory + * + * @param[in] chip_addr - I2C chip address; + * @param[in] mem_addr - memory (register) address within the chip; + * @param[in] mem_addr_len - number of bytes to use for mem_addr (typically 1, + * 2 for larger memories, 0 for register type devices with only + * one register); + * @param[out] buf - pointer to data buffer to store data; + * @param[in] len - data len in bytes; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_I2C_read_data(uint8_t chip_addr, uint32_t mem_addr, uint32_t mem_addr_len, uint8_t *buf, uint32_t len); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Gigabit Ethernet (GbE) Switch functions ======================== +//============================================================================= + +/** @addtogroup C66XX_GBE DSP Gigabit Ethernet Switch functions + * @{ + */ + +/*------------ C66XX_GBE_get_mac_id() function ---------------------------*//** + * @brief Function returns DSP MAC address for this device + * + * @return 64-bit variable that contains 48-bit MAC ID + * +-----------------------------------------------------------------------------*/ +uint64_t C66XX_GBE_get_mac_id(void); + + +/*------------ C66XX_GBE_init_serdes() function --------------------------*//** + * @brief Function inits Gigabit Ethernet Serdes block to the default state + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_GBE_init_serdes(void); + + +/** SGMII port Slave operation mode */ +#define C66XX_SGMII_PORT_SLAVE_MODE 0 +/** SGMII port Master operation mode */ +#define C66XX_SGMII_PORT_MASTER_MODE 1 + + +/** SGMII port autonegotiation disabled */ +#define C66XX_SGMII_PORT_AUTONEGOTIATION_DISABLED 0 +/** SGMII port autonegotiation enabled */ +#define C66XX_SGMII_PORT_AUTONEGOTIATION_ENABLED 1 + + +/*------------ C66XX_GBE_init_sgmii() function ---------------------------*//** + * @brief Function inits Gigabit Ethernet SGMII block + * + * Note that this function requires the presence of link partner connected + * at specified SGMII port - PHY or another SGMII. + * + * @param[in] port - MAC port number for which the SGMII port setup should + * be performed + * @param[in] mode - SGMII port operation mode: master or slave. + * @param[in] autoneg - flag to enable autonegotiation on this SGMII port. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_GBE_init_sgmii(uint32_t port, uint32_t mode, uint32_t autoneg); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ SRIO functions ================================================= +//============================================================================= + +/** @addtogroup C66XX_SRIO DSP SRIO functions + * @{ + */ + +/** SRIO vendor identifier */ +#define C66XX_SRIO_DEVICE_VENDOR_ID 0x30 +/** SRIO device revision */ +#define C66XX_SRIO_DEVICE_REVISION 0x0 +/** SRIO assembly identifier */ +#define C66XX_SRIO_DEVICE_ASSEMBLY_ID 0x0 +/** SRIO assembly vendor identifier */ +#define C66XX_SRIO_DEVICE_ASSEMBLY_VENDOR_ID C66XX_SRIO_DEVICE_VENDOR_ID +/** SRIO assembly device revision */ +#define C66XX_SRIO_DEVICE_ASSEMBLY_REVISION C66XX_SRIO_DEVICE_REVISION +/** SRIO assembly extension features */ +#define C66XX_SRIO_DEVICE_ASSEMBLY_FEATURES 0x0100 + + +/** SRIO link rate 1.25 Gbps */ +#define C66XX_SRIO_LINK_RATE_1_25GB 1 +/** SRIO link rate 2.5 Gbps */ +#define C66XX_SRIO_LINK_RATE_2_5GB 2 +/** SRIO link rate 3.125 Gbps */ +#define C66XX_SRIO_LINK_RATE_3_125GB 3 +/** SRIO link rate 5 Gbps */ +#define C66XX_SRIO_LINK_RATE_5GB 4 + + +// SRIO port widths defs - corresponds to SRIO path modes +/** SRIO port width with 1 receive and transmit lane */ +#define C66XX_SRIO_PORT_WIDTH_1X 0 +/** SRIO port width with 2 receive and transmit lanes */ +#define C66XX_SRIO_PORT_WIDTH_2X 3 +/** SRIO port width with 4 receive and transmit lanes */ +#define C66XX_SRIO_PORT_WIDTH_4X 4 + + +/** SRIO port 0 */ +#define C66XX_SRIO_PORT_0 0 +/** SRIO port 1 */ +#define C66XX_SRIO_PORT_1 1 +/** SRIO port 2 */ +#define C66XX_SRIO_PORT_2 2 +/** SRIO port 3 */ +#define C66XX_SRIO_PORT_3 3 + + +/** SRIO peripheral normal operation mode */ +#define C66XX_SRIO_OPMODE_NORMAL 0 +/** SRIO peripheral loopback operation mode - used to test the peripheral */ +#define C66XX_SRIO_OPMODE_LOOPBACK 1 + + +/** SRIO device identificator data descriptor */ +typedef struct +{ + uint32_t dev_id_8bit; /**< SRIO 8-bit device identificator */ + uint32_t dev_id_16bit; /**< SRIO 16-bit device identificator */ +} C66XX_SRIO_DEVICE_ID_DD; + +// SRIO device identificator data descriptor length in bytes +#define C66XX_SRIO_DEVICE_ID_DD_LEN sizeof(C66XX_SRIO_DEVICE_ID_DD) + + +/** SRIO destination device identificators number */ +#define C66XX_SRIO_DESTINATION_DEVICE_ID_COUNT 4 + + +/** SRIO messages (Type9 and Type11) transmit queues mapping data descriptor */ +typedef struct +{ + uint32_t port; /**< SRIO port to which the queue is mapped */ + uint32_t priority; /**< priority bit */ +} C66XX_SRIO_TX_QUEUE_SCH_DD; + +// SRIO messages (Type9 and Type11) transmit queues mapping data descriptor length in bytes +#define C66XX_SRIO_TX_QUEUE_SCH_DD_LEN sizeof(C66XX_SRIO_TX_QUEUE_SCH_DD) + + +/** SRIO peripheral initialization data descriptor */ +typedef struct +{ + uint32_t mode; /**< SRIO peripheral operation mode */ + uint32_t link_rate; /**< SRIO link rate definition */ + uint32_t port_width; /**< SRIO port width definition (1x, 2x, or 4x) */ + C66XX_SRIO_DEVICE_ID_DD src_dev_id_dd; /**< SRIO base device identificators */ + C66XX_SRIO_DEVICE_ID_DD dst_dev_id_dd[C66XX_SRIO_DESTINATION_DEVICE_ID_COUNT]; /**< SRIO destination device identificators */ +} C66XX_SRIO_DD; + +// SRIO peripheral initialization data descriptor length in bytes +#define C66XX_SRIO_DD_LEN sizeof(C66XX_SRIO_DD) + + +/*------------ C66XX_SRIO_init() function --------------------------------*//** + * @brief Function inits the SRIO peripheral + * + * The function does the following: + * 1. SRIO peripheral supports directIO, doorbell, data messaging (Type9 + * packets) and data streaming (Type11 packets) operations. + * 2. Max MTU length is set to 256 bytes. + * 3. SRIO 8-bit and 16-bit base device IDs are set to supplied parameters. + * 4. Available destination SRIO 8-bit and 16-bit device IDs are set + * according to supplied parameters. + * 5. Operation mode is set according to supplied parameter. + * 6. Link rate and ports configuration (4 ports are available) are set + * according to supplied parameters. + * 7. SRIO transmit queues used in data message (Type9 and Type11) operations + * are configured by default: all 16 queues send packets onto Port 0 and + * operate at the same minimum priority level. In case the different mapping + * is needed then C66XX_srio_map_tx_queue() function should be called. + * 8. 64 SRIO doorbell interrupts are configured by default: the first 16 + * interrupts (0-15) are routed to INTDST16 (Interrupt destination 16), + * 16-31 - to INTDST17 (Interrupt destination 17), 32-47 - to INTDST18 + * (Interrupt destination 18), 48-63 - to INTDST19 (Interrupt destination + * 19). In case the different interrupt routing is needed then + * C66XX_srio_route_doorbell_interrupt() function should be called. + * 9. GARBAGE queues, which can used by the TXU, are not configured. + * + * @param[in] srio_dd - SRIO peripheral initialization data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SRIO_init(C66XX_SRIO_DD *srio_dd); + + +/*------------ C66XX_SRIO_map_tx_queue() function ------------------------*//** + * @brief Function configures the selected SRIO transmit queue according to + * supplied parameters: SRIO port to which the queue is mapped and priority + * bit + * + * @param[in] queue - transmit queue number (0 - 15) + * @param[in] tx_queue_sch_dd - transmit queue mapping data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SRIO_map_tx_queue(uint32_t queue, C66XX_SRIO_TX_QUEUE_SCH_DD *tx_queue_sch_dd); + + +/*------------ C66XX_SRIO_route_doorbell_interrupt() function ------------*//** + * @brief Function configures the selected SRIO doorbell interrupt to + * specified interrupt destination number + * + * @param[in] doorbell - SRIO doorbell interrupt number (0 - 63) + * @param[in] intdst - interrupt destination number (0 - 23) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SRIO_route_doorbell_interrupt(uint32_t doorbell, uint32_t intdst); + + +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +} +#endif + + + +//============================================================================= +#endif /* __C66XX_FUNCTIONS_HXX__ */ diff --git a/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx b/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx new file mode 100644 index 00000000..54e7ef57 --- /dev/null +++ b/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx @@ -0,0 +1,1154 @@ +/****************************************************************************** + TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. + (C) MicroLAB Systems, 2014-2015 + + File: Macros + ----- + + Notes: + ------ + 1. This C-header file contains C66xx DSP macro definitions and + is used with C66XX.h C-header file. + + 2. This file is best viewed with the TAB setting set to '4'. + +******************************************************************************/ + + +/** + * @file C66XX_MACROS.hxx + * + * @brief Macros + * + * This file contains C66xx DSP macro definitions + * + */ + + +#ifndef __C66XX_MACROS_HXX__ // check for this file has been already included +#define __C66XX_MACROS_HXX__ 1 + + +//============================================================================= +//------------ I/O peripherals data type selector for C66xx DSP --------------- +// C66xx DSP has all I/O peripherals aligned as LSB of 32-bit words, then +// I/O peripherals should be accessed as UNSIGNED only. + +// The declared __C66XX_IO_DATA_TYPE__ is used to unify below macros and +// functions and to make particular selection at the run-time compilation time. +//================================================================ + +typedef volatile uint32_t __C66XX_IO_DATA_TYPE__; + +// read-back data bitmask for DSP memory-mapped registers (32-bit wide) +#define C66XX_RG_DATA_BITMASK 0xffffffff +//============================================================================= + + + +//============================================================================= +//============ General register access macros ================================= +//============================================================================= +// Macro to get selected register value +#define C66XX_GET_RG_VALUE(addr) ((*(__C66XX_IO_DATA_TYPE__ *) addr) & C66XX_RG_DATA_BITMASK) + +// Macro to set selected register to value +#define C66XX_SET_RG_VALUE(addr, val) ((*(__C66XX_IO_DATA_TYPE__ *) addr) = (val & C66XX_RG_DATA_BITMASK)) + +// Macro to make FIELD for the supplied value +#define C66XX_MAKE_FIELD(FIELD, val) (((val) << C66XX_##FIELD##_BITSHIFT) & C66XX_##FIELD##_BITMASK) + +// Macro to get FIELD value from the selected register +#define C66XX_GET_FIELD_VALUE(addr, FIELD) (((*(__C66XX_IO_DATA_TYPE__ *) addr) & C66XX_##FIELD##_BITMASK) >> C66XX_##FIELD##_BITSHIFT) + +// Macro to set FIELD to value in the selected register +#define C66XX_SET_FIELD_VALUE(addr, FIELD, val) ((*(__C66XX_IO_DATA_TYPE__ *) addr) = ((*(__C66XX_IO_DATA_TYPE__ *) addr) & ~C66XX_##FIELD##_BITMASK) | C66XX_MAKE_FIELD(FIELD, val)) + +//============================================================================= + + + +//============================================================================= +//============ DSP core registers macros ====================================== +//============================================================================= + +//------------ DSP CorePack revision register macros -------------------------- +#define C66XX_get_core_mm_revid_rg() C66XX_GET_RG_VALUE(C66XX_CORE_MM_REVID_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_core_mm_revid_version() C66XX_GET_FIELD_VALUE(C66XX_CORE_MM_REVID_RG_ADDR, CORE_MM_REVID_VERSION) +#define C66XX_get_core_mm_revid_revision() C66XX_GET_FIELD_VALUE(C66XX_CORE_MM_REVID_RG_ADDR, CORE_MM_REVID_REVISION) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_CORE_MM_REVID_VERSION_IS_C6678 (C66XX_get_core_mm_revid_version() == C66XX_CORE_MM_REVID_VERSION_C6678) +#define C66XX_CORE_MM_REVID_REVISION_IS_1_0 (C66XX_get_core_mm_revid_revision() == C66XX_CORE_MM_REVID_REVISION_1_0) +#define C66XX_CORE_MM_REVID_REVISION_IS_2_0 (C66XX_get_core_mm_revid_revision() == C66XX_CORE_MM_REVID_REVISION_2_0) + +//------------ DSP interrupt controller registers macros ---------------------- +// i index corresonds to DSP Event registers number +// Note that i index should be from 0 to 3 !!! +#define C66XX_get_core_evtflag_rg_addr(i) (C66XX_CORE_EVTFLAG_RG_BADDR + i * C66XX_CORE_EVTFLAG_RG_OFFSET) +#define C66XX_get_core_evtflag_rg(i) C66XX_GET_RG_VALUE(C66XX_get_core_evtflag_rg_addr(i)) + +#define C66XX_get_core_evtset_rg_addr(i) (C66XX_CORE_EVTSET_RG_BADDR + i * C66XX_CORE_EVTSET_RG_OFFSET) +#define C66XX_set_core_evtset_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_core_evtset_rg_addr(i), v) + +#define C66XX_get_core_evtclr_rg_addr(i) (C66XX_CORE_EVTCLR_RG_BADDR + i * C66XX_CORE_EVTCLR_RG_OFFSET) +#define C66XX_set_core_evtclr_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_core_evtclr_rg_addr(i), v) + +#define C66XX_get_core_evtmask_rg_addr(i) (C66XX_CORE_EVTMASK_RG_BADDR + i * C66XX_CORE_EVTMASK_RG_OFFSET) +#define C66XX_get_core_evtmask_rg(i) C66XX_GET_RG_VALUE(C66XX_get_core_evtmask_rg_addr(i)) +#define C66XX_set_core_evtmask_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_core_evtmask_rg_addr(i), v) + +//------------ DSP interrupt macros ------------------------------------------- +// These macros are used to set/get particular DSP Event in DSP Event registers +// i index corresonds to DSP Event ID number (0 - 127) +#define C66XX_get_core_event_id_rg(i) (i / 32) +#define C66XX_get_core_event_id_bitmask(i) (0x1 << (i % 32)) + +#define C66XX_get_core_event_id_flag(i) (C66XX_get_core_evtflag_rg(C66XX_get_core_event_id_rg(i)) & C66XX_get_core_event_id_bitmask(i)) +#define C66XX_set_core_event_id_flag(i) (C66XX_set_core_evtset_rg(C66XX_get_core_event_id_rg(i), C66XX_get_core_event_id_bitmask(i))) +#define C66XX_clear_core_event_id_flag(i) (C66XX_set_core_evtclr_rg(C66XX_get_core_event_id_rg(i), C66XX_get_core_event_id_bitmask(i))) +#define C66XX_get_core_event_id_mask(i) (C66XX_get_core_evtmask_rg(C66XX_get_core_event_id_rg(i)) & C66XX_get_core_event_id_bitmask(i)) +#define C66XX_set_core_event_id_mask(i) (C66XX_set_core_evtmask_rg(C66XX_get_core_event_id_rg(i), C66XX_get_core_event_id_bitmask(i))) + +//============================================================================= + + + +//============================================================================= +//============ PLL controller registers macros ================================ +//============================================================================= + +//------------ PLL control register macros ------------------------------------ +#define C66XX_get_pll_pllctl_rg() C66XX_GET_RG_VALUE(C66XX_PLL_PLLCTL_RG_ADDR) +#define C66XX_set_pll_pllctl_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_pllctl_pllensrc() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLENSRC) +#define C66XX_set_pll_pllctl_pllensrc(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLENSRC, v) +#define C66XX_get_pll_pllctl_pllrst() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLRST) +#define C66XX_set_pll_pllctl_pllrst(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLRST, v) +#define C66XX_get_pll_pllctl_pllpwrdn() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLPWRDN) +#define C66XX_set_pll_pllctl_pllpwrdn(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLPWRDN, v) +#define C66XX_get_pll_pllctl_pllen() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLEN) +#define C66XX_set_pll_pllctl_pllen(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLEN, v) + + // direct bit set macros +#define C66XX_SET_PLL_PLLCTL_PLLENSRC_ON C66XX_set_pll_pllctl_pllensrc(C66XX_ON) +#define C66XX_SET_PLL_PLLCTL_PLLENSRC_OFF C66XX_set_pll_pllctl_pllensrc(C66XX_OFF) +#define C66XX_SET_PLL_PLLCTL_PLLRST_ON C66XX_set_pll_pllctl_pllrst(C66XX_ON) +#define C66XX_SET_PLL_PLLCTL_PLLRST_OFF C66XX_set_pll_pllctl_pllrst(C66XX_OFF) +#define C66XX_SET_PLL_PLLCTL_PLLPWRDN_ON C66XX_set_pll_pllctl_pllpwrdn(C66XX_ON) +#define C66XX_SET_PLL_PLLCTL_PLLPWRDN_OFF C66XX_set_pll_pllctl_pllpwrdn(C66XX_OFF) +#define C66XX_SET_PLL_PLLCTL_PLLEN_ON C66XX_set_pll_pllctl_pllen(C66XX_ON) +#define C66XX_SET_PLL_PLLCTL_PLLEN_OFF C66XX_set_pll_pllctl_pllen(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_PLLCTL_PLLENSRC_IS_ON (C66XX_get_pll_pllctl_pllensrc() == C66XX_ON) +#define C66XX_PLL_PLLCTL_PLLRST_IS_ON (C66XX_get_pll_pllctl_pllrst() == C66XX_ON) +#define C66XX_PLL_PLLCTL_PLLPWRDN_IS_ON (C66XX_get_pll_pllctl_pllpwrdn() == C66XX_ON) +#define C66XX_PLL_PLLCTL_PLLEN_IS_ON (C66XX_get_pll_pllctl_pllen() == C66XX_ON) + + +//------------ PLL secondary control register macros -------------------------- +#define C66XX_get_pll_secctl_rg() C66XX_GET_RG_VALUE(C66XX_PLL_SECCTL_RG_ADDR) +#define C66XX_set_pll_secctl_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_SECCTL_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_secctl_bypass() C66XX_GET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_BYPASS) +#define C66XX_set_pll_secctl_bypass(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_BYPASS, v) +#define C66XX_get_pll_secctl_output_divide() C66XX_GET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_OUTPUT_DIVIDE) +#define C66XX_set_pll_secctl_output_divide(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_OUTPUT_DIVIDE, v) + + // direct bit set macros +#define C66XX_SET_PLL_SECCTL_BYPASS_ON C66XX_set_pll_secctl_bypass(C66XX_ON) +#define C66XX_SET_PLL_SECCTL_BYPASS_OFF C66XX_set_pll_secctl_bypass(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_SECCTL_BYPASS_IS_ON (C66XX_get_pll_secctl_bypass() == C66XX_ON) + + +//------------ PLL multiplier control register macros ------------------------- +#define C66XX_get_pll_pllm_rg() C66XX_GET_RG_VALUE(C66XX_PLL_PLLM_RG_ADDR) +#define C66XX_set_pll_pllm_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_PLLM_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_pllm_pllm() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLM_RG_ADDR, PLL_PLLM_PLLM) +#define C66XX_set_pll_pllm_pllm(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLM_RG_ADDR, PLL_PLLM_PLLM, v) + + +//------------ PLL controller divider registers macros ------------------------ +// i index corresonds to PLL controller divider registers number +// Note that i index should be from 0 to 15 instead of 1 to 16 !!! +#define C66XX_get_pll_plldiv_rg_addr(i) (i < 3 ? (C66XX_PLL_PLLDIV1_RG_ADDR + i * 0x4) : (C66XX_PLL_PLLDIV4_RG_ADDR + (i - 3) * 0x4)) +#define C66XX_get_pll_plldiv_rg(i) C66XX_GET_RG_VALUE(C66XX_get_pll_plldiv_rg_addr(i)) +#define C66XX_set_pll_plldiv_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_pll_plldiv_rg_addr(i), v) + + // dedicated bit specific macros +#define C66XX_get_pll_plldiv_den(i) C66XX_GET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_DEN) +#define C66XX_set_pll_plldiv_den(i, v) C66XX_SET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_DEN, v) +#define C66XX_get_pll_plldiv_ratio(i) C66XX_GET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_RATIO) +#define C66XX_set_pll_plldiv_ratio(i, v) C66XX_SET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_RATIO, v) + + // direct bit set macros +#define C66XX_SET_PLL_PLLDIV_DEN_ON(i) C66XX_set_pll_plldiv_den(i, C66XX_ON) +#define C66XX_SET_PLL_PLLDIV_DEN_OFF(i) C66XX_set_pll_plldiv_den(i, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_PLLDIV_DEN_IS_ON(i) (C66XX_get_pll_plldiv_den(i) == C66XX_ON) + + +//------------ PLL controller command register macros ------------------------- +#define C66XX_get_pll_pllcmd_rg() C66XX_GET_RG_VALUE(C66XX_PLL_PLLCMD_RG_ADDR) +#define C66XX_set_pll_pllcmd_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_PLLCMD_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_pllcmd_goset() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCMD_RG_ADDR, PLL_PLLCMD_GOSET) +#define C66XX_set_pll_pllcmd_goset(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCMD_RG_ADDR, PLL_PLLCMD_GOSET, v) + + // direct bit set macros +#define C66XX_SET_PLL_PLLCMD_GOSET_ON C66XX_set_pll_pllcmd_goset(C66XX_ON) +#define C66XX_SET_PLL_PLLCMD_GOSET_OFF C66XX_set_pll_pllcmd_goset(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_PLLCMD_GOSET_IS_ON (C66XX_get_pll_pllcmd_goset() == C66XX_ON) + + +//------------ PLL controller status register macros -------------------------- +#define C66XX_get_pll_pllstat_rg() C66XX_GET_RG_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR) +#define C66XX_set_pll_pllstat_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_pllstat_gostat() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR, PLL_PLLSTAT_GOSTAT) +#define C66XX_set_pll_pllstat_gostat(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR, PLL_PLLSTAT_GOSTAT, v) + + // direct bit set macros +#define C66XX_SET_PLL_PLLSTAT_GOSTAT_ON C66XX_set_pll_pllstat_gostat(C66XX_ON) +#define C66XX_SET_PLL_PLLSTAT_GOSTAT_OFF C66XX_set_pll_pllstat_gostat(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_PLLSTAT_GOSTAT_IS_ON (C66XX_get_pll_pllstat_gostat() == C66XX_ON) + + +//------------ PLL controller clock align control register macros ------------- +#define C66XX_get_pll_alnctl_rg() C66XX_GET_RG_VALUE(C66XX_PLL_ALNCTL_RG_ADDR) +#define C66XX_set_pll_alnctl_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_ALNCTL_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_alnctl_aln() C66XX_GET_FIELD_VALUE(C66XX_PLL_ALNCTL_RG_ADDR, PLL_ALNCTL_ALN) +#define C66XX_set_pll_alnctl_aln(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_ALNCTL_RG_ADDR, PLL_ALNCTL_ALN, v) + + +//------------ PLL controller divider ratio change status register macros ----- +#define C66XX_get_pll_dchange_rg() C66XX_GET_RG_VALUE(C66XX_PLL_DCHANGE_RG_ADDR) +#define C66XX_set_pll_dchange_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_DCHANGE_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_dchange_sys() C66XX_GET_FIELD_VALUE(C66XX_PLL_DCHANGE_RG_ADDR, PLL_DCHANGE_SYS) +#define C66XX_set_pll_dchange_sys(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_DCHANGE_RG_ADDR, PLL_DCHANGE_SYS, v) + + +//------------ SYSCLK status register macros ---------------------------------- +#define C66XX_get_pll_systat_rg() C66XX_GET_RG_VALUE(C66XX_PLL_SYSTAT_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_pll_systat_syson() C66XX_GET_FIELD_VALUE(C66XX_PLL_SYSTAT_RG_ADDR, PLL_SYSTAT_SYSON) + +//============================================================================= + + + +//============================================================================= +//============ Device State Control registers macros ========================== +//============================================================================= + +//------------ Main PLL Control register 0 macros ----------------------------- +#define C66XX_get_bootcfg_mainpllctl0_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR) +#define C66XX_set_bootcfg_mainpllctl0_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_mainpllctl0_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_BWADJ) +#define C66XX_set_bootcfg_mainpllctl0_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_BWADJ, v) +#define C66XX_get_bootcfg_mainpllctl0_pllm() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLM) +#define C66XX_set_bootcfg_mainpllctl0_pllm(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLM, v) +#define C66XX_get_bootcfg_mainpllctl0_plld() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLD) +#define C66XX_set_bootcfg_mainpllctl0_plld(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLD, v) + + +//------------ Main PLL Control register 1 macros ----------------------------- +#define C66XX_get_bootcfg_mainpllctl1_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR) +#define C66XX_set_bootcfg_mainpllctl1_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_mainpllctl1_ensat() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_ENSAT) +#define C66XX_set_bootcfg_mainpllctl1_ensat(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_ENSAT, v) +#define C66XX_get_bootcfg_mainpllctl1_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_BWADJ) +#define C66XX_set_bootcfg_mainpllctl1_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_BWADJ, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_MAINPLLCTL1_ENSAT_ON C66XX_set_bootcfg_mainpllctl1_ensat(C66XX_ON) +#define C66XX_SET_BOOTCFG_MAINPLLCTL1_ENSAT_OFF C66XX_set_bootcfg_mainpllctl1_ensat(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_MAINPLLCTL1_ENSAT_IS_ON (C66XX_get_bootcfg_mainpllctl1_ensat() == C66XX_ON) + + +//------------ DDR3 PLL Control register 0 macros ----------------------------- +#define C66XX_get_bootcfg_ddr3pllctl0_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR) +#define C66XX_set_bootcfg_ddr3pllctl0_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_ddr3pllctl0_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BWADJ) +#define C66XX_set_bootcfg_ddr3pllctl0_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BWADJ, v) +#define C66XX_get_bootcfg_ddr3pllctl0_bypass() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BYPASS) +#define C66XX_set_bootcfg_ddr3pllctl0_bypass(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BYPASS, v) +#define C66XX_get_bootcfg_ddr3pllctl0_pllm() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLM) +#define C66XX_set_bootcfg_ddr3pllctl0_pllm(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLM, v) +#define C66XX_get_bootcfg_ddr3pllctl0_plld() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLD) +#define C66XX_set_bootcfg_ddr3pllctl0_plld(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLD, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_DDR3PLLCTL0_BYPASS_ON C66XX_set_bootcfg_ddr3pllctl0_bypass(C66XX_ON) +#define C66XX_SET_BOOTCFG_DDR3PLLCTL0_BYPASS_OFF C66XX_set_bootcfg_ddr3pllctl0_bypass(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_DDR3PLLCTL0_BYPASS_IS_ON (C66XX_get_bootcfg_ddr3pllctl0_bypass() == C66XX_ON) + + +//------------ DDR3 PLL Control register 1 macros ----------------------------- +#define C66XX_get_bootcfg_ddr3pllctl1_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR) +#define C66XX_set_bootcfg_ddr3pllctl1_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_ddr3pllctl1_pllrst() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_PLLRST) +#define C66XX_set_bootcfg_ddr3pllctl1_pllrst(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_PLLRST, v) +#define C66XX_get_bootcfg_ddr3pllctl1_ensat() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_ENSAT) +#define C66XX_set_bootcfg_ddr3pllctl1_ensat(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_ENSAT, v) +#define C66XX_get_bootcfg_ddr3pllctl1_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_BWADJ) +#define C66XX_set_bootcfg_ddr3pllctl1_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_BWADJ, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_DDR3PLLCTL1_PLLRST_ON C66XX_set_bootcfg_ddr3pllctl1_pllrst(C66XX_ON) +#define C66XX_SET_BOOTCFG_DDR3PLLCTL1_PLLRST_OFF C66XX_set_bootcfg_ddr3pllctl1_pllrst(C66XX_OFF) +#define C66XX_SET_BOOTCFG_DDR3PLLCTL1_ENSAT_ON C66XX_set_bootcfg_ddr3pllctl1_ensat(C66XX_ON) +#define C66XX_SET_BOOTCFG_DDR3PLLCTL1_ENSAT_OFF C66XX_set_bootcfg_ddr3pllctl1_ensat(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_DDR3PLLCTL1_PLLRST_IS_ON (C66XX_get_bootcfg_ddr3pllctl1_pllrst() == C66XX_ON) +#define C66XX_BOOTCFG_DDR3PLLCTL1_ENSAT_IS_ON (C66XX_get_bootcfg_ddr3pllctl1_ensat() == C66XX_ON) + + +//------------ PASS PLL Control register 0 macros ----------------------------- +#define C66XX_get_bootcfg_passpllctl0_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR) +#define C66XX_set_bootcfg_passpllctl0_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_passpllctl0_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BWADJ) +#define C66XX_set_bootcfg_passpllctl0_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BWADJ, v) +#define C66XX_get_bootcfg_passpllctl0_bypass() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BYPASS) +#define C66XX_set_bootcfg_passpllctl0_bypass(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BYPASS, v) +#define C66XX_get_bootcfg_passpllctl0_pllm() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLM) +#define C66XX_set_bootcfg_passpllctl0_pllm(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLM, v) +#define C66XX_get_bootcfg_passpllctl0_plld() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLD) +#define C66XX_set_bootcfg_passpllctl0_plld(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLD, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_PASSPLLCTL0_BYPASS_ON C66XX_set_bootcfg_passpllctl0_bypass(C66XX_ON) +#define C66XX_SET_BOOTCFG_PASSPLLCTL0_BYPASS_OFF C66XX_set_bootcfg_passpllctl0_bypass(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_PASSPLLCTL0_BYPASS_IS_ON (C66XX_get_bootcfg_passpllctl0_bypass() == C66XX_ON) + + +//------------ PASS PLL Control register 1 macros ----------------------------- +#define C66XX_get_bootcfg_passpllctl1_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR) +#define C66XX_set_bootcfg_passpllctl1_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_passpllctl1_pllrst() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLRST) +#define C66XX_set_bootcfg_passpllctl1_pllrst(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLRST, v) +#define C66XX_get_bootcfg_passpllctl1_pllselect() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLSELECT) +#define C66XX_set_bootcfg_passpllctl1_pllselect(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLSELECT, v) +#define C66XX_get_bootcfg_passpllctl1_ensat() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_ENSAT) +#define C66XX_set_bootcfg_passpllctl1_ensat(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_ENSAT, v) +#define C66XX_get_bootcfg_passpllctl1_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_BWADJ) +#define C66XX_set_bootcfg_passpllctl1_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_BWADJ, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLRST_ON C66XX_set_bootcfg_passpllctl1_pllrst(C66XX_ON) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLRST_OFF C66XX_set_bootcfg_passpllctl1_pllrst(C66XX_OFF) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLSELECT_ON C66XX_set_bootcfg_passpllctl1_pllselect(C66XX_ON) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLSELECT_OFF C66XX_set_bootcfg_passpllctl1_pllselect(C66XX_OFF) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_ENSAT_ON C66XX_set_bootcfg_passpllctl1_ensat(C66XX_ON) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_ENSAT_OFF C66XX_set_bootcfg_passpllctl1_ensat(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLRST_IS_ON (C66XX_get_bootcfg_passpllctl1_pllrst() == C66XX_ON) +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLSELECT_IS_ON (C66XX_get_bootcfg_passpllctl1_pllselect() == C66XX_ON) +#define C66XX_BOOTCFG_PASSPLLCTL1_ENSAT_IS_ON (C66XX_get_bootcfg_passpllctl1_ensat() == C66XX_ON) + + +//------------ Device speed register macros ----------------------------------- +#define C66XX_get_bootcfg_devspeed_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_DEVSPEED_RG_ADDR) + // dedicated bit specific macros +#define C66XX_get_bootcfg_devspeed_devspeed() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DEVSPEED_RG_ADDR, BOOTCFG_DEVSPEED_DEVSPEED) + +//============================================================================= + + + +//============================================================================= +//============ I2C registers macros =========================================== +//============================================================================= + +//------------ I2C own address register macros -------------------------------- +#define C66XX_get_i2c_icoar_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICOAR_RG_ADDR) +#define C66XX_set_i2c_icoar_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICOAR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icoar_oaddr() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICOAR_RG_ADDR, I2C_ICOAR_OADDR) +#define C66XX_set_i2c_icoar_oaddr(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICOAR_RG_ADDR, I2C_ICOAR_OADDR, v) + + +//------------ I2C interrupt mask register macros ----------------------------- +#define C66XX_get_i2c_icimr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICIMR_RG_ADDR) +#define C66XX_set_i2c_icimr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICIMR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icimr_aas() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AAS) +#define C66XX_set_i2c_icimr_aas(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AAS, v) +#define C66XX_get_i2c_icimr_scd() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_SCD) +#define C66XX_set_i2c_icimr_scd(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_SCD, v) +#define C66XX_get_i2c_icimr_icxrdy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICXRDY) +#define C66XX_set_i2c_icimr_icxrdy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICXRDY, v) +#define C66XX_get_i2c_icimr_icrdrdy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICRDRDY) +#define C66XX_set_i2c_icimr_icrdrdy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICRDRDY, v) +#define C66XX_get_i2c_icimr_ardy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ARDY) +#define C66XX_set_i2c_icimr_ardy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ARDY, v) +#define C66XX_get_i2c_icimr_nack() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_NACK) +#define C66XX_set_i2c_icimr_nack(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_NACK, v) +#define C66XX_get_i2c_icimr_al() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AL) +#define C66XX_set_i2c_icimr_al(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AL, v) + + // direct bit set macros +#define C66XX_SET_I2C_ICIMR_AAS_ON C66XX_set_i2c_icimr_aas(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_AAS_OFF C66XX_set_i2c_icimr_aas(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_SCD_ON C66XX_set_i2c_icimr_scd(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_SCD_OFF C66XX_set_i2c_icimr_scd(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_ICXRDY_ON C66XX_set_i2c_icimr_icxrdy(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_ICXRDY_OFF C66XX_set_i2c_icimr_icxrdy(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_ICRDRDY_ON C66XX_set_i2c_icimr_icrdrdy(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_ICRDRDY_OFF C66XX_set_i2c_icimr_icrdrdy(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_ARDY_ON C66XX_set_i2c_icimr_ardy(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_ARDY_OFF C66XX_set_i2c_icimr_ardy(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_NACK_ON C66XX_set_i2c_icimr_nack(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_NACK_OFF C66XX_set_i2c_icimr_nack(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_AL_ON C66XX_set_i2c_icimr_al(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_AL_OFF C66XX_set_i2c_icimr_al(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_I2C_ICIMR_AAS_IS_ON (C66XX_get_i2c_icimr_aas() == C66XX_ON) +#define C66XX_I2C_ICIMR_SCD_IS_ON (C66XX_get_i2c_icimr_scd() == C66XX_ON) +#define C66XX_I2C_ICIMR_ICXRDY_IS_ON (C66XX_get_i2c_icimr_icxrdy() == C66XX_ON) +#define C66XX_I2C_ICIMR_ICRDRDY_IS_ON (C66XX_get_i2c_icimr_icrdrdy() == C66XX_ON) +#define C66XX_I2C_ICIMR_ARDY_IS_ON (C66XX_get_i2c_icimr_ardy() == C66XX_ON) +#define C66XX_I2C_ICIMR_NACK_IS_ON (C66XX_get_i2c_icimr_nack() == C66XX_ON) +#define C66XX_I2C_ICIMR_AL_IS_ON (C66XX_get_i2c_icimr_al() == C66XX_ON) + + +//------------ I2C interrupt status register macros --------------------------- +#define C66XX_get_i2c_icstr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICSTR_RG_ADDR) +#define C66XX_set_i2c_icstr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICSTR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icstr_sdir() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SDIR) +#define C66XX_set_i2c_icstr_sdir(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SDIR, v) +#define C66XX_get_i2c_icstr_nacksnt() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACKSNT) +#define C66XX_set_i2c_icstr_nacksnt(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACKSNT, v) +#define C66XX_get_i2c_icstr_bb() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_BB) +#define C66XX_set_i2c_icstr_bb(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_BB, v) +#define C66XX_get_i2c_icstr_rsfull() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_RSFULL) +#define C66XX_get_i2c_icstr_xsmt() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_XSMT) +#define C66XX_get_i2c_icstr_aas() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AAS) +#define C66XX_get_i2c_icstr_ad0() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AD0) +#define C66XX_get_i2c_icstr_scd() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SCD) +#define C66XX_set_i2c_icstr_scd(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SCD, v) +#define C66XX_get_i2c_icstr_icxrdy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICXRDY) +#define C66XX_set_i2c_icstr_icxrdy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICXRDY, v) +#define C66XX_get_i2c_icstr_icrdrdy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICRDRDY) +#define C66XX_set_i2c_icstr_icrdrdy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICRDRDY, v) +#define C66XX_get_i2c_icstr_ardy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ARDY) +#define C66XX_set_i2c_icstr_ardy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ARDY, v) +#define C66XX_get_i2c_icstr_nack() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACK) +#define C66XX_set_i2c_icstr_nack(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACK, v) +#define C66XX_get_i2c_icstr_al() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AL) +#define C66XX_set_i2c_icstr_al(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AL, v) + + // direct bit set macros +#define C66XX_CLEAR_I2C_ICSTR_SDIR C66XX_set_i2c_icstr_sdir(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_NACKSNT C66XX_set_i2c_icstr_nacksnt(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_BB C66XX_set_i2c_icstr_bb(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_SCD C66XX_set_i2c_icstr_scd(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_ICXRDY C66XX_set_i2c_icstr_icxrdy(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_ICRDRDY C66XX_set_i2c_icstr_icrdrdy(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_ARDY C66XX_set_i2c_icstr_ardy(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_NACK C66XX_set_i2c_icstr_nack(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_AL C66XX_set_i2c_icstr_al(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_I2C_ICSTR_SDIR_IS_ON (C66XX_get_i2c_icstr_sdir() == C66XX_ON) +#define C66XX_I2C_ICSTR_NACKSNT_IS_ON (C66XX_get_i2c_icstr_nacksnt() == C66XX_ON) +#define C66XX_I2C_ICSTR_BB_IS_ON (C66XX_get_i2c_icstr_bb() == C66XX_ON) +#define C66XX_I2C_ICSTR_RSFULL_IS_ON (C66XX_get_i2c_icstr_rsfull() == C66XX_ON) +#define C66XX_I2C_ICSTR_XSMT_IS_ON (C66XX_get_i2c_icstr_xsmt() == C66XX_ON) +#define C66XX_I2C_ICSTR_AAS_IS_ON (C66XX_get_i2c_icstr_aas() == C66XX_ON) +#define C66XX_I2C_ICSTR_AD0_IS_ON (C66XX_get_i2c_icstr_ad0() == C66XX_ON) +#define C66XX_I2C_ICSTR_SCD_IS_ON (C66XX_get_i2c_icstr_scd() == C66XX_ON) +#define C66XX_I2C_ICSTR_ICXRDY_IS_ON (C66XX_get_i2c_icstr_icxrdy() == C66XX_ON) +#define C66XX_I2C_ICSTR_ICRDRDY_IS_ON (C66XX_get_i2c_icstr_icrdrdy() == C66XX_ON) +#define C66XX_I2C_ICSTR_ARDY_IS_ON (C66XX_get_i2c_icstr_ardy() == C66XX_ON) +#define C66XX_I2C_ICSTR_NACK_IS_ON (C66XX_get_i2c_icstr_nack() == C66XX_ON) +#define C66XX_I2C_ICSTR_AL_IS_ON (C66XX_get_i2c_icstr_al() == C66XX_ON) + + +//------------ I2C clock low-time divider register macros --------------------- +#define C66XX_get_i2c_icclkl_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICCLKL_RG_ADDR) +#define C66XX_set_i2c_icclkl_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICCLKL_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icclkl_iccl() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICCLKL_RG_ADDR, I2C_ICCLKL_ICCL) +#define C66XX_set_i2c_icclkl_iccl(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICCLKL_RG_ADDR, I2C_ICCLKL_ICCL, v) + + +//------------ I2C clock high-time divider register macros -------------------- +#define C66XX_get_i2c_icclkh_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICCLKH_RG_ADDR) +#define C66XX_set_i2c_icclkh_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICCLKH_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icclkh_icch() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICCLKH_RG_ADDR, I2C_ICCLKH_ICCH) +#define C66XX_set_i2c_icclkh_icch(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICCLKH_RG_ADDR, I2C_ICCLKH_ICCH, v) + + +//------------ I2C data count register macros --------------------------------- +#define C66XX_get_i2c_iccnt_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICCNT_RG_ADDR) +#define C66XX_set_i2c_iccnt_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICCNT_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_iccnt_icdc() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICCNT_RG_ADDR, I2C_ICCNT_ICDC) +#define C66XX_set_i2c_iccnt_icdc(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICCNT_RG_ADDR, I2C_ICCNT_ICDC, v) + + +//------------ I2C data receive register macros ------------------------------- +#define C66XX_get_i2c_icdrr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICDRR_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_i2c_icdrr_d() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICDRR_RG_ADDR, I2C_ICDRR_D) + + +//------------ I2C slave address register macros ------------------------------ +#define C66XX_get_i2c_icsar_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICSAR_RG_ADDR) +#define C66XX_set_i2c_icsar_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICSAR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icsar_saddr() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSAR_RG_ADDR, I2C_ICSAR_SADDR) +#define C66XX_set_i2c_icsar_saddr(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSAR_RG_ADDR, I2C_ICSAR_SADDR, v) + + +//------------ I2C data transmit register macros ------------------------------ +#define C66XX_get_i2c_icdxr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICDXR_RG_ADDR) +#define C66XX_set_i2c_icdxr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICDXR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icdxr_d() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICDXR_RG_ADDR, I2C_ICDXR_D) +#define C66XX_set_i2c_icdxr_d(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICDXR_RG_ADDR, I2C_ICDXR_D, v) + + +//------------ I2C mode register macros --------------------------------------- +#define C66XX_get_i2c_icmdr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICMDR_RG_ADDR) +#define C66XX_set_i2c_icmdr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICMDR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icmdr_nackmod() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_NACKMOD) +#define C66XX_set_i2c_icmdr_nackmod(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_NACKMOD, v) +#define C66XX_get_i2c_icmdr_free() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FREE) +#define C66XX_set_i2c_icmdr_free(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FREE, v) +#define C66XX_get_i2c_icmdr_stt() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STT) +#define C66XX_set_i2c_icmdr_stt(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STT, v) +#define C66XX_get_i2c_icmdr_stp() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STP) +#define C66XX_set_i2c_icmdr_stp(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STP, v) +#define C66XX_get_i2c_icmdr_mst() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_MST) +#define C66XX_set_i2c_icmdr_mst(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_MST, v) +#define C66XX_get_i2c_icmdr_trx() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_TRX) +#define C66XX_set_i2c_icmdr_trx(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_TRX, v) +#define C66XX_get_i2c_icmdr_xa() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_XA) +#define C66XX_set_i2c_icmdr_xa(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_XA, v) +#define C66XX_get_i2c_icmdr_rm() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_RM) +#define C66XX_set_i2c_icmdr_rm(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_RM, v) +#define C66XX_get_i2c_icmdr_dlb() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_DLB) +#define C66XX_set_i2c_icmdr_dlb(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_DLB, v) +#define C66XX_get_i2c_icmdr_irs() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_IRS) +#define C66XX_set_i2c_icmdr_irs(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_IRS, v) +#define C66XX_get_i2c_icmdr_stb() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STB) +#define C66XX_set_i2c_icmdr_stb(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STB, v) +#define C66XX_get_i2c_icmdr_fdf() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FDF) +#define C66XX_set_i2c_icmdr_fdf(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FDF, v) +#define C66XX_get_i2c_icmdr_bc() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_BC) +#define C66XX_set_i2c_icmdr_bc(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_BC, v) + + // direct bit set macros +#define C66XX_SET_I2C_ICMDR_NACKMOD_ON C66XX_set_i2c_icmdr_nackmod(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_NACKMOD_OFF C66XX_set_i2c_icmdr_nackmod(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_FREE_ON C66XX_set_i2c_icmdr_free(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_FREE_OFF C66XX_set_i2c_icmdr_free(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_STT_ON C66XX_set_i2c_icmdr_stt(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_STT_OFF C66XX_set_i2c_icmdr_stt(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_STP_ON C66XX_set_i2c_icmdr_stp(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_STP_OFF C66XX_set_i2c_icmdr_stp(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_MST_ON C66XX_set_i2c_icmdr_mst(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_MST_OFF C66XX_set_i2c_icmdr_mst(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_TRX_ON C66XX_set_i2c_icmdr_trx(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_TRX_OFF C66XX_set_i2c_icmdr_trx(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_XA_OFF C66XX_set_i2c_icmdr_xa(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_XA_ON C66XX_set_i2c_icmdr_xa(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_RM_OFF C66XX_set_i2c_icmdr_rm(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_RM_ON C66XX_set_i2c_icmdr_rm(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_DLB_OFF C66XX_set_i2c_icmdr_dlb(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_DLB_ON C66XX_set_i2c_icmdr_dlb(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_IRS_OFF C66XX_set_i2c_icmdr_irs(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_IRS_ON C66XX_set_i2c_icmdr_irs(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_STB_OFF C66XX_set_i2c_icmdr_stb(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_STB_ON C66XX_set_i2c_icmdr_stb(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_FDF_OFF C66XX_set_i2c_icmdr_fdf(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_FDF_ON C66XX_set_i2c_icmdr_fdf(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_I2C_ICMDR_NACKMOD_IS_ON (C66XX_get_i2c_icmdr_nackmod() == C66XX_ON) +#define C66XX_I2C_ICMDR_FREE_IS_ON (C66XX_get_i2c_icmdr_free() == C66XX_ON) +#define C66XX_I2C_ICMDR_STT_IS_ON (C66XX_get_i2c_icmdr_stt() == C66XX_ON) +#define C66XX_I2C_ICMDR_STP_IS_ON (C66XX_get_i2c_icmdr_stp() == C66XX_ON) +#define C66XX_I2C_ICMDR_MST_IS_ON (C66XX_get_i2c_icmdr_mst() == C66XX_ON) +#define C66XX_I2C_ICMDR_TRX_IS_ON (C66XX_get_i2c_icmdr_trx() == C66XX_ON) +#define C66XX_I2C_ICMDR_XA_IS_ON (C66XX_get_i2c_icmdr_xa() == C66XX_ON) +#define C66XX_I2C_ICMDR_RM_IS_ON (C66XX_get_i2c_icmdr_rm() == C66XX_ON) +#define C66XX_I2C_ICMDR_DLB_IS_ON (C66XX_get_i2c_icmdr_dlb() == C66XX_ON) +#define C66XX_I2C_ICMDR_IRS_IS_ON (C66XX_get_i2c_icmdr_irs() == C66XX_ON) +#define C66XX_I2C_ICMDR_STB_IS_ON (C66XX_get_i2c_icmdr_stb() == C66XX_ON) +#define C66XX_I2C_ICMDR_FDF_IS_ON (C66XX_get_i2c_icmdr_fdf() == C66XX_ON) + + +//------------ I2C interrupt vector register macros --------------------------- +#define C66XX_get_i2c_icivr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICIVR_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_i2c_icivr_intcode() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIVR_RG_ADDR, I2C_ICIVR_INTCODE) + + +//------------ I2C extended mode register macros ------------------------------ +#define C66XX_get_i2c_icemdr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICEMDR_RG_ADDR) +#define C66XX_set_i2c_icemdr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icemdr_ignack() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_IGNACK) +#define C66XX_set_i2c_icemdr_ignack(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_IGNACK, v) +#define C66XX_get_i2c_icemdr_bcm() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_BCM) +#define C66XX_set_i2c_icemdr_bcm(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_BCM, v) + + // direct bit set macros +#define C66XX_SET_I2C_ICEMDR_IGNACK_ON C66XX_set_i2c_icemdr_ignack(C66XX_ON) +#define C66XX_SET_I2C_ICEMDR_IGNACK_OFF C66XX_set_i2c_icemdr_ignack(C66XX_OFF) +#define C66XX_SET_I2C_ICEMDR_BCM_ON C66XX_set_i2c_icemdr_bcm(C66XX_ON) +#define C66XX_SET_I2C_ICEMDR_BCM_OFF C66XX_set_i2c_icemdr_bcm(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_I2C_ICEMDR_IGNACK_IS_ON (C66XX_get_i2c_icemdr_ignack() == C66XX_ON) +#define C66XX_I2C_ICEMDR_BCM_IS_ON (C66XX_get_i2c_icemdr_bcm() == C66XX_ON) + + +//------------ I2C prescaler register macros ---------------------------------- +#define C66XX_get_i2c_icpsc_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICPSC_RG_ADDR) +#define C66XX_set_i2c_icpsc_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICPSC_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icpsc_ipsc() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPSC_RG_ADDR, I2C_ICPSC_IPSC) +#define C66XX_set_i2c_icpsc_ipsc(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPSC_RG_ADDR, I2C_ICPSC_IPSC, v) + + +//------------ I2C peripheral identification 1 register macros ---------------- +#define C66XX_get_i2c_icpid1_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICPID1_RG_ADDR) +#define C66XX_set_i2c_icpid1_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICPID1_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icpid1_class() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_CLASS) +#define C66XX_set_i2c_icpid1_class(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_CLASS, v) +#define C66XX_get_i2c_icpid1_revision() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_REVISION) +#define C66XX_set_i2c_icpid1_revision(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_REVISION, v) + + +//------------ I2C peripheral identification 2 register macros ---------------- +#define C66XX_get_i2c_icpid2_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICPID2_RG_ADDR) +#define C66XX_set_i2c_icpid2_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICPID2_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icpid2_type() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPID2_RG_ADDR, I2C_ICPID2_TYPE) +#define C66XX_set_i2c_icpid2_type(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPID2_RG_ADDR, I2C_ICPID2_TYPE, v) +//============================================================================= + + + +//============================================================================= +//============ EMIF16 configuration macros ==================================== +//============================================================================= + +//------------ Revision code and status register macros ----------------------- +#define C66XX_get_emif16_rcsr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_RCSR_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_emif16_rcsr_be() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_BE) +#define C66XX_get_emif16_rcsr_mod_id() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_MOD_ID) +#define C66XX_get_emif16_rcsr_mj_rev() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_MJ_REV) +#define C66XX_get_emif16_rcsr_min_rev() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_MIN_REV) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_RCSR_BE_IS_ON (C66XX_get_emif16_rcsr_be() == C66XX_ON) +#define C66XX_EMIF16_RCSR_MOD_ID_IS_DEFAULT_VALUE (C66XX_get_emif16_rcsr_mod_id() == C66XX_EMIF16_RCSR_MOD_ID_DEFAULT_VALUE) +#define C66XX_EMIF16_RCSR_MJ_REV_IS_DEFAULT_VALUE (C66XX_get_emif16_rcsr_mj_rev() == C66XX_EMIF16_RCSR_MJ_REV_DEFAULT_VALUE) +#define C66XX_EMIF16_RCSR_MIN_REV_IS_DEFAULT_VALUE (C66XX_get_emif16_rcsr_min_rev() == C66XX_EMIF16_RCSR_MIN_REV_DEFAULT_VALUE) + + +//------------ Async wait cycle config register macros ------------------------ +#define C66XX_get_emif16_awccr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR) +#define C66XX_set_emif16_awccr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_awccr_wp1() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP1) +#define C66XX_set_emif16_awccr_wp1(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP1, v) +#define C66XX_get_emif16_awccr_wp0() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP0) +#define C66XX_set_emif16_awccr_wp0(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP0, v) +#define C66XX_get_emif16_awccr_cs5_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS5_WAIT) +#define C66XX_set_emif16_awccr_cs5_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS5_WAIT, v) +#define C66XX_get_emif16_awccr_cs4_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS4_WAIT) +#define C66XX_set_emif16_awccr_cs4_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS4_WAIT, v) +#define C66XX_get_emif16_awccr_cs3_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS3_WAIT) +#define C66XX_set_emif16_awccr_cs3_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS3_WAIT, v) +#define C66XX_get_emif16_awccr_cs2_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS2_WAIT) +#define C66XX_set_emif16_awccr_cs2_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS2_WAIT, v) +#define C66XX_get_emif16_awccr_max_ext_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_MAX_EXT_WAIT) +#define C66XX_set_emif16_awccr_max_ext_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_MAX_EXT_WAIT, v) + + // direct bit set macros +#define C66XX_SET_EMIF16_AWCCR_WP1_ON C66XX_set_emif16_awccr_wp1(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_WP1_OFF C66XX_set_emif16_awccr_wp1(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_WP0_ON C66XX_set_emif16_awccr_wp0(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_WP0_OFF C66XX_set_emif16_awccr_wp0(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_CS5_WAIT1 C66XX_set_emif16_awccr_cs5_wait(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_CS5_WAIT0 C66XX_set_emif16_awccr_cs5_wait(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_CS4_WAIT1 C66XX_set_emif16_awccr_cs4_wait(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_CS4_WAIT0 C66XX_set_emif16_awccr_cs4_wait(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_CS3_WAIT1 C66XX_set_emif16_awccr_cs3_wait(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_CS3_WAIT0 C66XX_set_emif16_awccr_cs3_wait(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_CS2_WAIT1 C66XX_set_emif16_awccr_cs2_wait(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_CS2_WAIT0 C66XX_set_emif16_awccr_cs2_wait(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_AWCCR_WP1_IS_ON (C66XX_get_emif16_awccr_wp1() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_WP0_IS_ON (C66XX_get_emif16_awccr_wp0() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_CS5_WAIT_IS_WAIT1 (C66XX_get_emif16_awccr_cs5_wait() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_CS4_WAIT_IS_WAIT1 (C66XX_get_emif16_awccr_cs4_wait() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_CS3_WAIT_IS_WAIT1 (C66XX_get_emif16_awccr_cs3_wait() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_CS2_WAIT_IS_WAIT1 (C66XX_get_emif16_awccr_cs2_wait() == C66XX_ON) + + +//------------ Async config registers macros ---------------------------------- +// i index corresonds to Async config registers number +#define C66XX_get_emif16_acr_rg_addr(i) (C66XX_EMIF16_A1CR_RG_ADDR + i * 0x4) +#define C66XX_get_emif16_acr_rg(i) C66XX_GET_RG_VALUE(C66XX_get_emif16_acr_rg_addr(i)) +#define C66XX_set_emif16_acr_rg(i,v) C66XX_SET_RG_VALUE(C66XX_get_emif16_acr_rg_addr(i), v) + + // dedicated bit specific macros +#define C66XX_get_emif16_acr_ss(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_SS) +#define C66XX_set_emif16_acr_ss(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_SS, v) +#define C66XX_get_emif16_acr_ew(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_EW) +#define C66XX_set_emif16_acr_ew(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_EW, v) +#define C66XX_get_emif16_acr_w_setup(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_SETUP) +#define C66XX_set_emif16_acr_w_setup(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_SETUP, v) +#define C66XX_get_emif16_acr_w_strobe(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_STROBE) +#define C66XX_set_emif16_acr_w_strobe(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_STROBE, v) +#define C66XX_get_emif16_acr_w_hold(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_HOLD) +#define C66XX_set_emif16_acr_w_hold(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_HOLD, v) +#define C66XX_get_emif16_acr_r_setup(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_SETUP) +#define C66XX_set_emif16_acr_r_setup(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_SETUP, v) +#define C66XX_get_emif16_acr_r_strobe(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_STROBE) +#define C66XX_set_emif16_acr_r_strobe(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_STROBE, v) +#define C66XX_get_emif16_acr_r_hold(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_HOLD) +#define C66XX_set_emif16_acr_r_hold(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_HOLD, v) +#define C66XX_get_emif16_acr_ta(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_TA) +#define C66XX_set_emif16_acr_ta(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_TA, v) +#define C66XX_get_emif16_acr_asize(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_ASIZE) +#define C66XX_set_emif16_acr_asize(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_ASIZE, v) + + // direct bit set macros +#define C66XX_SET_EMIF16_ACR_SS_ON(i) C66XX_set_emif16_acr_ss(i, C66XX_ON) +#define C66XX_SET_EMIF16_ACR_SS_OFF(i) C66XX_set_emif16_acr_ss(i, C66XX_OFF) +#define C66XX_SET_EMIF16_ACR_EW_ON(i) C66XX_set_emif16_acr_ew(i, C66XX_ON) +#define C66XX_SET_EMIF16_ACR_EW_OFF(i) C66XX_set_emif16_acr_ew(i, C66XX_OFF) +#define C66XX_SET_EMIF16_ACR_ASIZE_16BIT(i) C66XX_set_emif16_acr_asize(i, C66XX_EMIF16_A1CR_ASIZE_16BIT) +#define C66XX_SET_EMIF16_ACR_ASIZE_8BIT(i) C66XX_set_emif16_acr_asize(i, C66XX_EMIF16_A1CR_ASIZE_8BIT) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_ACR_SS_IS_ON(i) (C66XX_get_emif16_acr_ss(i) == C66XX_ON) +#define C66XX_EMIF16_ACR_EW_IS_ON(i) (C66XX_get_emif16_acr_ew(i) == C66XX_ON) +#define C66XX_EMIF16_ACR_ASIZE_IS_16BIT(i) (C66XX_get_emif16_acr_asize(i) == C66XX_EMIF16_A1CR_ASIZE_16BIT) + + +//------------ Interrupt raw register macros ---------------------------------- +#define C66XX_get_emif16_irr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_IRR_RG_ADDR) +#define C66XX_set_emif16_irr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_IRR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_irr_wr() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_WR) +#define C66XX_set_emif16_irr_wr(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_WR, v) +#define C66XX_get_emif16_irr_at() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_AT) +#define C66XX_set_emif16_irr_at(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_AT, v) + + // direct bit set macros +#define C66XX_CLEAR_EMIF16_IRR_AT C66XX_set_emif16_irr_at(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_IRR_AT_IS_ON (C66XX_get_emif16_irr_at() == C66XX_ON) + + +//------------ Interrupt masked register macros ------------------------------- +#define C66XX_get_emif16_imr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_IMR_RG_ADDR) +#define C66XX_set_emif16_imr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_IMR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_imr_wr_masked() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_WR_MASKED) +#define C66XX_set_emif16_imr_wr_masked(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_WR_MASKED, v) +#define C66XX_get_emif16_imr_at_masked() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_AT_MASKED) +#define C66XX_set_emif16_imr_at_masked(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_AT_MASKED, v) + + // direct bit set macros +#define C66XX_CLEAR_EMIF16_IMR_AT_MASKED C66XX_set_emif16_imr_at_masked(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_IMR_AT_MASKED_IS_ON (C66XX_get_emif16_imr_at_masked() == C66XX_ON) + + +//------------ Interrupt mask set register macros ----------------------------- +#define C66XX_get_emif16_imsr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_IMSR_RG_ADDR) +#define C66XX_set_emif16_imsr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_imsr_wr_mask_set() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_WR_MASK_SET) +#define C66XX_set_emif16_imsr_wr_mask_set(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_WR_MASK_SET, v) +#define C66XX_get_emif16_imsr_at_mask_set() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_AT_MASK_SET) +#define C66XX_set_emif16_imsr_at_mask_set(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_AT_MASK_SET, v) + + // direct bit set macros +#define C66XX_SET_EMIF16_IMSR_AT_MASK_SET_ON C66XX_set_emif16_imsr_at_mask_set(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_IMSR_AT_MASK_SET_IS_ON (C66XX_get_emif16_imsr_at_mask_set() == C66XX_ON) + + +//------------ Interrupt mask clear register macros ----------------------------- +#define C66XX_get_emif16_imcr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_IMCR_RG_ADDR) +#define C66XX_set_emif16_imcr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_imcr_wr_mask_clr() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_WR_MASK_CLR) +#define C66XX_set_emif16_imcr_wr_mask_clr(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_WR_MASK_CLR, v) +#define C66XX_get_emif16_imcr_at_mask_clr() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_AT_MASK_CLR) +#define C66XX_set_emif16_imcr_at_mask_clr(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_AT_MASK_CLR, v) + + // direct bit set macros +#define C66XX_SET_EMIF16_IMCR_AT_MASK_CLR_ON C66XX_set_emif16_imcr_at_mask_clr(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_IMCR_AT_MASK_CLR_IS_ON (C66XX_get_emif16_imcr_at_mask_clr() == C66XX_ON) +//============================================================================= + + + +//============================================================================= +//============ Timer registers macros ========================================= +//============================================================================= + +//------------ Emulation Management and Clock Speed register macros ----------- +#define C66XX_get_timer_emumgt_clkspd_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_EMUMGT_CLKSPD_RG_ADDR(timer)) + + // dedicated bit specific macros +#define C66XX_get_timer_emumgt_clkspd_clkdiv(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_EMUMGT_CLKSPD_RG_ADDR(timer), TIMER_EMUMGT_CLKSPD_CLKDIV) + + +//------------ Counter register low register macros --------------------------- +#define C66XX_get_timer_cntlo_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_CNTLO_RG_ADDR(timer)) +#define C66XX_set_timer_cntlo_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_CNTLO_RG_ADDR(timer), v) + + +//------------ Counter register high register macros -------------------------- +#define C66XX_get_timer_cnthi_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_CNTHI_RG_ADDR(timer)) +#define C66XX_set_timer_cnthi_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_CNTHI_RG_ADDR(timer), v) + + +//------------ Period register low register macros ---------------------------- +#define C66XX_get_timer_prdlo_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_PRDLO_RG_ADDR(timer)) +#define C66XX_set_timer_prdlo_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_PRDLO_RG_ADDR(timer), v) + + +//------------ Period register high register macros --------------------------- +#define C66XX_get_timer_prdhi_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_PRDHI_RG_ADDR(timer)) +#define C66XX_set_timer_prdhi_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_PRDHI_RG_ADDR(timer), v) + + +//------------ Timer control register macros ---------------------------------- +#define C66XX_get_timer_tcr_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer)) +#define C66XX_set_timer_tcr_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), v) + + // dedicated bit specific macros +#define C66XX_get_timer_tcr_readrstmode_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_HI) +#define C66XX_set_timer_tcr_readrstmode_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_HI, v) +#define C66XX_get_timer_tcr_enamode_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_HI) +#define C66XX_set_timer_tcr_enamode_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_HI, v) +#define C66XX_get_timer_tcr_pwid_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_HI) +#define C66XX_set_timer_tcr_pwid_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_HI, v) +#define C66XX_get_timer_tcr_cp_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_HI) +#define C66XX_set_timer_tcr_cp_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_HI, v) +#define C66XX_get_timer_tcr_invoutp_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_HI) +#define C66XX_set_timer_tcr_invoutp_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_HI, v) +#define C66XX_get_timer_tcr_tstat_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TSTAT_HI) +#define C66XX_get_timer_tcr_capevtmode_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPEVTMODE_LO) +#define C66XX_set_timer_tcr_capevtmode_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPEVTMODE_LO, v) +#define C66XX_get_timer_tcr_capmode_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPMODE_LO) +#define C66XX_set_timer_tcr_capmode_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPMODE_LO, v) +#define C66XX_get_timer_tcr_readrstmode_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_LO) +#define C66XX_set_timer_tcr_readrstmode_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_LO, v) +#define C66XX_get_timer_tcr_tien_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TIEN_LO) +#define C66XX_set_timer_tcr_tien_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TIEN_LO, v) +#define C66XX_get_timer_tcr_clksrc_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CLKSRC_LO) +#define C66XX_set_timer_tcr_clksrc_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CLKSRC_LO, v) +#define C66XX_get_timer_tcr_enamode_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_LO) +#define C66XX_set_timer_tcr_enamode_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_LO, v) +#define C66XX_get_timer_tcr_pwid_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_LO) +#define C66XX_set_timer_tcr_pwid_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_LO, v) +#define C66XX_get_timer_tcr_cp_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_LO) +#define C66XX_set_timer_tcr_cp_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_LO, v) +#define C66XX_get_timer_tcr_invinp_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVINP_LO) +#define C66XX_set_timer_tcr_invinp_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVINP_LO, v) +#define C66XX_get_timer_tcr_invoutp_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_LO) +#define C66XX_set_timer_tcr_invoutp_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_LO, v) +#define C66XX_get_timer_tcr_tstat_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TSTAT_LO) + + // direct bit set macros +#define C66XX_SET_TIMER_TCR_READRSTMODE_HI_ON(timer) C66XX_set_timer_tcr_readrstmode_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_READRSTMODE_HI_OFF(timer) C66XX_set_timer_tcr_readrstmode_hi(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_ENAMODE_HI_DISABLED(timer) C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_DISABLED) +#define C66XX_SET_TIMER_TCR_ENAMODE_HI_ONE_SHOT(timer) C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_ONE_SHOT) +#define C66XX_SET_TIMER_TCR_ENAMODE_HI_CONT(timer) C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_CONT) +#define C66XX_SET_TIMER_TCR_ENAMODE_HI_CONT_RELOAD(timer) C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD) +#define C66XX_SET_TIMER_TCR_PWID_HI_1_CLK(timer) C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_1_CLK) +#define C66XX_SET_TIMER_TCR_PWID_HI_2_CLK(timer) C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_2_CLK) +#define C66XX_SET_TIMER_TCR_PWID_HI_3_CLK(timer) C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_3_CLK) +#define C66XX_SET_TIMER_TCR_PWID_HI_4_CLK(timer) C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_4_CLK) +#define C66XX_SET_TIMER_TCR_CP_HI_ON(timer) C66XX_set_timer_tcr_cp_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_CP_HI_OFF(timer) C66XX_set_timer_tcr_cp_hi(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_INVOUTP_HI_ON(timer) C66XX_set_timer_tcr_invoutp_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_INVOUTP_HI_OFF(timer) C66XX_set_timer_tcr_invoutp_hi(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_CAPEVTMODE_LO_RISING_EDGE(timer) C66XX_set_timer_tcr_capevtmode_lo(timer, C66XX_TIMER_TCR_CAPEVTMODE_RISING_EDGE) +#define C66XX_SET_TIMER_TCR_CAPEVTMODE_LO_FALLING_EDGE(timer) C66XX_set_timer_tcr_capevtmode_lo(timer, C66XX_TIMER_TCR_CAPEVTMODE_FALLING_EDGE) +#define C66XX_SET_TIMER_TCR_CAPEVTMODE_LO_ANY_EDGE(timer) C66XX_set_timer_tcr_capevtmode_lo(timer, C66XX_TIMER_TCR_CAPEVTMODE_ANY_EDGE) +#define C66XX_SET_TIMER_TCR_CAPMODE_LO_ON(timer) C66XX_set_timer_tcr_capmode_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_CAPMODE_LO_OFF(timer) C66XX_set_timer_tcr_capmode_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_READRSTMODE_LO_ON(timer) C66XX_set_timer_tcr_readrstmode_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_READRSTMODE_LO_OFF(timer) C66XX_set_timer_tcr_readrstmode_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_TIEN_LO_ON(timer) C66XX_set_timer_tcr_tien_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_TIEN_LO_OFF(timer) C66XX_set_timer_tcr_tien_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_CLKSRC_LO_ON(timer) C66XX_set_timer_tcr_clksrc_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_CLKSRC_LO_OFF(timer) C66XX_set_timer_tcr_clksrc_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_ENAMODE_LO_DISABLED(timer) C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_DISABLED) +#define C66XX_SET_TIMER_TCR_ENAMODE_LO_ONE_SHOT(timer) C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_ONE_SHOT) +#define C66XX_SET_TIMER_TCR_ENAMODE_LO_CONT(timer) C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_CONT) +#define C66XX_SET_TIMER_TCR_ENAMODE_LO_CONT_RELOAD(timer) C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD) +#define C66XX_SET_TIMER_TCR_PWID_LO_1_CLK(timer) C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_1_CLK) +#define C66XX_SET_TIMER_TCR_PWID_LO_2_CLK(timer) C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_2_CLK) +#define C66XX_SET_TIMER_TCR_PWID_LO_3_CLK(timer) C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_3_CLK) +#define C66XX_SET_TIMER_TCR_PWID_LO_4_CLK(timer) C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_4_CLK) +#define C66XX_SET_TIMER_TCR_CP_LO_ON(timer) C66XX_set_timer_tcr_cp_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_CP_LO_OFF(timer) C66XX_set_timer_tcr_cp_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_INVINP_LO_ON(timer) C66XX_set_timer_tcr_invinp_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_INVINP_LO_OFF(timer) C66XX_set_timer_tcr_invinp_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_INVOUTP_LO_ON(timer) C66XX_set_timer_tcr_invoutp_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_INVOUTP_LO_OFF(timer) C66XX_set_timer_tcr_invoutp_lo(timer, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_TIMER_TCR_READRSTMODE_HI_IS_ON(timer) (C66XX_get_timer_tcr_readrstmode_hi(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_ENAMODE_HI_IS_DISABLED(timer) (C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_DISABLED) +#define C66XX_TIMER_TCR_ENAMODE_HI_IS_ONE_SHOT(timer) (C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_ONE_SHOT) +#define C66XX_TIMER_TCR_ENAMODE_HI_IS_CONT(timer) (C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_CONT) +#define C66XX_TIMER_TCR_ENAMODE_HI_IS_CONT_RELOAD(timer) (C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD) +#define C66XX_TIMER_TCR_PWI_HI_IS_1_CLK(timer) (C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_1_CLK) +#define C66XX_TIMER_TCR_PWI_HI_IS_2_CLK(timer) (C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_2_CLK) +#define C66XX_TIMER_TCR_PWI_HI_IS_3_CLK(timer) (C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_3_CLK) +#define C66XX_TIMER_TCR_PWI_HI_IS_4_CLK(timer) (C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_4_CLK) +#define C66XX_TIMER_TCR_CP_HI_IS_ON(timer) (C66XX_get_timer_tcr_cp_hi(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_INVOUTP_HI_IS_ON(timer) (C66XX_get_timer_tcr_invoutp_hi(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_TSTAT_HI_IS_ON(timer) (C66XX_get_timer_tcr_tstat_hi(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_IS_RISING_EDGE(timer) (C66XX_get_timer_tcr_capevtmode_lo(timer) == C66XX_TIMER_TCR_CAPEVTMODE_RISING_EDGE) +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_IS_FALLING_EDGE(timer) (C66XX_get_timer_tcr_capevtmode_lo(timer) == C66XX_TIMER_TCR_CAPEVTMODE_FALLING_EDGE) +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_IS_ANY_EDGE(timer) (C66XX_get_timer_tcr_capevtmode_lo(timer) == C66XX_TIMER_TCR_CAPEVTMODE_ANY_EDGE) +#define C66XX_TIMER_TCR_CAPMODE_LO_IS_ON(timer) (C66XX_get_timer_tcr_capmode_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_READRSTMODE_LO_IS_ON(timer) (C66XX_get_timer_tcr_readrstmode_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_TIEN_LO_IS_ON(timer) (C66XX_get_timer_tcr_tien_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_CLKSRC_LO_IS_ON(timer) (C66XX_get_timer_tcr_clksrc_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_ENAMODE_LO_IS_DISABLED(timer) (C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_DISABLED) +#define C66XX_TIMER_TCR_ENAMODE_LO_IS_ONE_SHOT(timer) (C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_ONE_SHOT) +#define C66XX_TIMER_TCR_ENAMODE_LO_IS_CONT(timer) (C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_CONT) +#define C66XX_TIMER_TCR_ENAMODE_LO_IS_CONT_RELOAD(timer) (C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD) +#define C66XX_TIMER_TCR_PWI_LO_IS_1_CLK(timer) (C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_1_CLK) +#define C66XX_TIMER_TCR_PWI_LO_IS_2_CLK(timer) (C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_2_CLK) +#define C66XX_TIMER_TCR_PWI_LO_IS_3_CLK(timer) (C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_3_CLK) +#define C66XX_TIMER_TCR_PWI_LO_IS_4_CLK(timer) (C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_4_CLK) +#define C66XX_TIMER_TCR_CP_LO_IS_ON(timer) (C66XX_get_timer_tcr_cp_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_INVINP_LO_IS_ON(timer) (C66XX_get_timer_tcr_invinp_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_INVOUTP_LO_IS_ON(timer) (C66XX_get_timer_tcr_invoutp_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_TSTAT_LO_IS_ON(timer) (C66XX_get_timer_tcr_tstat_lo(timer) == C66XX_ON) + + +//------------ Timer global control register macros --------------------------- +#define C66XX_get_timer_tgcr_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer)) +#define C66XX_set_timer_tgcr_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), v) + + // dedicated bit specific macros +#define C66XX_get_timer_tgcr_tddrhi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TDDRHI) +#define C66XX_set_timer_tgcr_tddrhi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TDDRHI, v) +#define C66XX_get_timer_tgcr_pschi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PSCHI) +#define C66XX_set_timer_tgcr_pschi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PSCHI, v) +#define C66XX_get_timer_tgcr_plusen(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PLUSEN) +#define C66XX_set_timer_tgcr_plusen(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PLUSEN, v) +#define C66XX_get_timer_tgcr_timmode(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMMODE) +#define C66XX_set_timer_tgcr_timmode(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMMODE, v) +#define C66XX_get_timer_tgcr_timhirs(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMHIRS) +#define C66XX_set_timer_tgcr_timhirs(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMHIRS, v) +#define C66XX_get_timer_tgcr_timlors(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMLORS) +#define C66XX_set_timer_tgcr_timlors(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMLORS, v) + + // direct bit set macros +#define C66XX_SET_TIMER_TGCR_PLUSEN_ON(timer) C66XX_set_timer_tgcr_plusen(timer, C66XX_ON) +#define C66XX_SET_TIMER_TGCR_PLUSEN_OFF(timer) C66XX_set_timer_tgcr_plusen(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TGCR_TIMMODE_64BIT_GPT(timer) C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_64BIT_GPT) +#define C66XX_SET_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED(timer) C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED) +#define C66XX_SET_TIMER_TGCR_TIMMODE_64BIT_WDT(timer) C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_64BIT_WDT) +#define C66XX_SET_TIMER_TGCR_TIMMODE_32BIT_CHAINED(timer) C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_32BIT_CHAINED) +#define C66XX_SET_TIMER_TGCR_TIMHIRS_ON(timer) C66XX_set_timer_tgcr_timhirs(timer, C66XX_ON) +#define C66XX_SET_TIMER_TGCR_TIMHIRS_OFF(timer) C66XX_set_timer_tgcr_timhirs(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TGCR_TIMLORS_ON(timer) C66XX_set_timer_tgcr_timlors(timer, C66XX_ON) +#define C66XX_SET_TIMER_TGCR_TIMLORS_OFF(timer) C66XX_set_timer_tgcr_timlors(timer, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_TIMER_TGCR_PLUSEN_IS_ON(timer) (C66XX_get_timer_tgcr_plusen(timer) == C66XX_ON) +#define C66XX_TIMER_TGCR_TIMMODE_IS_64BIT_GPT(timer) (C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_64BIT_GPT) +#define C66XX_TIMER_TGCR_TIMMODE_IS_32BIT_UNCHAINED(timer) (C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED) +#define C66XX_TIMER_TGCR_TIMMODE_IS_64BIT_WDT(timer) (C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_64BIT_WDT) +#define C66XX_TIMER_TGCR_TIMMODE_IS_32BIT_CHAINED(timer) (C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_32BIT_CHAINED) +#define C66XX_TIMER_TGCR_TIMHIRS_IS_ON(timer) (C66XX_get_timer_tgcr_timhirs(timer) == C66XX_ON) +#define C66XX_TIMER_TGCR_TIMLORS_IS_ON(timer) (C66XX_get_timer_tgcr_timlors(timer) == C66XX_ON) + + +//------------ Watchdog Timer Control Register macros ------------------------- +#define C66XX_get_timer_wdtcr_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer)) +#define C66XX_set_timer_wdtcr_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), v) + + // dedicated bit specific macros +#define C66XX_get_timer_wdtcr_wdkey(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDKEY) +#define C66XX_set_timer_wdtcr_wdkey(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDKEY, v) +#define C66XX_get_timer_wdtcr_wdflag(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDFLAG) +#define C66XX_set_timer_wdtcr_wdflag(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDFLAG, v) +#define C66XX_get_timer_wdtcr_wden(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDEN) +#define C66XX_set_timer_wdtcr_wden(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDEN, v) + + // direct bit set macros +#define C66XX_SET_TIMER_WDTCR_WDKEY_FIRST_KEY(timer) C66XX_set_timer_wdtcr_wdkey(timer, C66XX_TIMER_WDTCR_WDKEY_FIRST_KEY) +#define C66XX_SET_TIMER_WDTCR_WDKEY_SECOND_KEY(timer) C66XX_set_timer_wdtcr_wdkey(timer, C66XX_TIMER_WDTCR_WDKEY_SECOND_KEY) +#define C66XX_SET_TIMER_WDTCR_WDFLAG_ON(timer) C66XX_set_timer_wdtcr_wdflag(timer, C66XX_ON) +#define C66XX_SET_TIMER_WDTCR_WDFLAG_OFF(timer) C66XX_set_timer_wdtcr_wdflag(timer, C66XX_OFF) +#define C66XX_SET_TIMER_WDTCR_WDEN_ON(timer) C66XX_set_timer_wdtcr_wden(timer, C66XX_ON) +#define C66XX_SET_TIMER_WDTCR_WDEN_OFF(timer) C66XX_set_timer_wdtcr_wden(timer, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_TIMER_WDTCR_WDFLAG_IS_ON(timer) (C66XX_get_timer_wdtcr_wdflag(timer) == C66XX_ON) +#define C66XX_TIMER_WDTCR_WDEN_IS_ON(timer) (C66XX_get_timer_wdtcr_wden(timer) == C66XX_ON) + + +//------------ Timer Reload register low register macros ---------------------- +#define C66XX_get_timer_rello_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_RELLO_RG_ADDR(timer)) +#define C66XX_set_timer_rello_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_RELLO_RG_ADDR(timer), v) + + +//------------ Timer Reload register high register macros --------------------- +#define C66XX_get_timer_relhi_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_RELHI_RG_ADDR(timer)) +#define C66XX_set_timer_relhi_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_RELHI_RG_ADDR(timer), v) + + +//------------ Timer Capture register low register macros --------------------- +#define C66XX_get_timer_caplo_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_CAPLO_RG_ADDR(timer)) +#define C66XX_set_timer_caplo_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_CAPLO_RG_ADDR(timer), v) + + +//------------ Timer Capture register high register macros -------------------- +#define C66XX_get_timer_caphi_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_CAPHI_RG_ADDR(timer)) +#define C66XX_set_timer_caphi_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_CAPHI_RG_ADDR(timer), v) + + +//------------ Timer interrupt control and status register macros ------------- +#define C66XX_get_timer_intctlstat_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer)) +#define C66XX_set_timer_intctlstat_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), v) + + // dedicated bit specific macros +#define C66XX_get_timer_intctlstat_evtintstat_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_HI) +#define C66XX_set_timer_intctlstat_evtintstat_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_HI, v) +#define C66XX_get_timer_intctlstat_evtinten_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_HI) +#define C66XX_set_timer_intctlstat_evtinten_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_HI, v) +#define C66XX_get_timer_intctlstat_prdintstat_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_HI) +#define C66XX_set_timer_intctlstat_prdintstat_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_HI, v) +#define C66XX_get_timer_intctlstat_prdinten_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_HI) +#define C66XX_set_timer_intctlstat_prdinten_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_HI, v) +#define C66XX_get_timer_intctlstat_evtintstat_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_LO) +#define C66XX_set_timer_intctlstat_evtintstat_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_LO, v) +#define C66XX_get_timer_intctlstat_evtinten_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_LO) +#define C66XX_set_timer_intctlstat_evtinten_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_LO, v) +#define C66XX_get_timer_intctlstat_prdintstat_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_LO) +#define C66XX_set_timer_intctlstat_prdintstat_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_LO, v) +#define C66XX_get_timer_intctlstat_prdinten_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_LO) +#define C66XX_set_timer_intctlstat_prdinten_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_LO, v) + + // direct bit set macros +#define C66XX_CLEAR_TIMER_INTCTLSTAT_EVTINTSTAT_HI(timer) C66XX_set_timer_intctlstat_evtintstat_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_HI_ON(timer) C66XX_set_timer_intctlstat_evtinten_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_HI_OFF(timer) C66XX_set_timer_intctlstat_evtinten_hi(timer, C66XX_OFF) +#define C66XX_CLEAR_TIMER_INTCTLSTAT_PRDINTSTAT_HI(timer) C66XX_set_timer_intctlstat_prdintstat_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_HI_ON(timer) C66XX_set_timer_intctlstat_prdinten_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_HI_OFF(timer) C66XX_set_timer_intctlstat_prdinten_hi(timer, C66XX_OFF) +#define C66XX_CLEAR_TIMER_INTCTLSTAT_EVTINTSTAT_LO(timer) C66XX_set_timer_intctlstat_evtintstat_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_LO_ON(timer) C66XX_set_timer_intctlstat_evtinten_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_LO_OFF(timer) C66XX_set_timer_intctlstat_evtinten_lo(timer, C66XX_OFF) +#define C66XX_CLEAR_TIMER_INTCTLSTAT_PRDINTSTAT_LO(timer) C66XX_set_timer_intctlstat_prdintstat_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_LO_ON(timer) C66XX_set_timer_intctlstat_prdinten_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_LO_OFF(timer) C66XX_set_timer_intctlstat_prdinten_lo(timer, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_HI_IS_ON(timer) (C66XX_get_timer_intctlstat_evtintstat_hi(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_HI_IS_ON(timer) (C66XX_get_timer_intctlstat_evtinten_hi(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_HI_IS_ON(timer) (C66XX_get_timer_intctlstat_prdintstat_hi(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_HI_IS_ON(timer) (C66XX_get_timer_intctlstat_prdinten_hi(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_LO_IS_ON(timer) (C66XX_get_timer_intctlstat_evtintstat_lo(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_LO_IS_ON(timer) (C66XX_get_timer_intctlstat_evtinten_lo(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_LO_IS_ON(timer) (C66XX_get_timer_intctlstat_prdintstat_lo(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_LO_IS_ON(timer) (C66XX_get_timer_intctlstat_prdinten_lo(timer) == C66XX_ON) + +//============================================================================= + + + +//============================================================================= +#endif /* __C66XX_MACROS_HXX__ */ diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP.h b/ports/c667x/ccs/example_build/include/TA66XX_DSP.h new file mode 100644 index 00000000..04dfc4b7 --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP.h @@ -0,0 +1,251 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 4A. + General definitions and API functions. + (C) MicroLAB Systems, 2015-2017 + + + http://www.mlabsys.com + ftp://ftp.mlabsys.com + email: [email protected] + + + Description: + ------------ + This file contains general definitions and API functions for TORNADO AMC + modules SDK and must be included in the user C-application for + TORNADO AMC modules. + + + Revision history: + ----------------- + rev.2A - 2015, initial release for TORNADO-A6678 board rev.1B; + rev.3A - 2016: + - added support for TORNADO-A6678/FMC board rev.1A; + rev.3B - 2017: + - added support for TORNADO-A6678/FMC board rev.1B; + rev.4A - 2017: + - added support for TORNADO-AZ/FMC board rev.1A; + + + Notes: + ------ + 1. This C-header file is an include file for TI C6xxx C/C++ Code + Generation Tools, which must be invoked to compile for C66xx DSP + platform. + + 2. This file is best viewed with the TAB setting set to '4'. + + + Copyright: + ---------- + This utility is supplied free of charge as it is without any obligation + from MicroLAB Systems. No responsibility is assumed for any use or misuse + of these utilities. + +******************************************************************************/ + + +/** + * @file TA66XX_DSP.h + * + * @brief Main include file + * + * This file contains general definitions and API functions for TORNADO + * AMC modules SDK + * + */ + + +#ifndef __TA66XX_DSP_H__ // check for this file has been already included +#define __TA66XX_DSP_H__ 1 + + +// General defs +#define TA66XX_ON 1 +#define TA66XX_OFF 0 + + +// Include C66xx DSP defs, macros and aux functions +#include "C66XX.h" +// Include TORNADO AMC SDK functions errors +#include "TASDK_ERR.h" + + + +//============================================================================= +/** TORNADO AMC SDK revision ID */ +#define TA66XX_SDK_REVISION_ID "4A" +//============================================================================= + + + +//============================================================================= +//============ TORNADO AMC SDK API functions ID defs ========================== +//============================================================================= +/** @addtogroup TA66XX_FUNCTIONS_ID SDK API functions ID defs + * @{ + */ + + +/**< Function name max size */ +#define TA66XX_FUNCTION_NAME_LEN_MAX 64 + + +enum +{ + TA66XX_GET_ERROR_MESSAGE_FUNCTION_ID = 0, + TA66XX_GET_FUNCTION_NAME_FUNCTION_ID, + TA66XX_BC_SET_I2C_INTERRUPT_NUMBER_FUNCTION_ID, + TA66XX_BC_SET_UART_INTERRUPT_NUMBER_FUNCTION_ID, + TA66XX_BC_INIT_FUNCTION_ID, + TA66XX_BC_MAP_DSP_GPIO_INTERRUPT_FUNCTION_ID, + TA66XX_BC_UNMAP_DSP_GPIO_INTERRUPT_FUNCTION_ID, + TA66XX_BC_INIT_UART_FUNCTION_ID, + TA66XX_BC_WRITE_EEPROM_FUNCTION_ID, + TA66XX_BC_READ_EEPROM_FUNCTION_ID, + TA66XX_BC_ERASE_EEPROM_FUNCTION_ID, + TA66XX_BC_GET_DEVICE_INFO_FUNCTION_ID, + TA66XX_BC_GET_HW_CFG_INFO_FUNCTION_ID, + TA66XX_BC_GET_FMC_INFO_FUNCTION_ID, + TA66XX_BC_GET_TEMP_STATE_FUNCTION_ID, + TA66XX_BC_GET_POWER_STATE_FUNCTION_ID, + TA66XX_BC_GET_FMC_POWER_STATE_FUNCTION_ID, + TA66XX_BC_GET_SFP_INFO_FUNCTION_ID, + TA66XX_BC_SET_FPGA_HIF_CONFIG_FUNCTION_ID, + TA66XX_BC_GET_FPGA_HIF_CONFIG_FUNCTION_ID, + TA66XX_BC_CLEAR_FPGA_CNF_FUNCTION_ID, + TA66XX_BC_LOAD_FPGA_CNF_FUNCTION_ID, + TA66XX_BC_GET_GBE_PORT_INFO_FUNCTION_ID, + TA66XX_BC_INIT_GBE_PORT_FUNCTION_ID, + TA66XX_BC_ERASE_FLASH_FUNCTION_ID, + TA66XX_BC_WRITE_FLASH_FUNCTION_ID, + TA66XX_BC_READ_FLASH_FUNCTION_ID, + TA66XX_SC_INIT_FLASH_RECORD_LIST_FUNCTION_ID, + TA66XX_SC_GET_NUMBER_OF_FLASH_RECORDS_FUNCTION_ID, + TA66XX_SC_GET_FLASH_RECORD_LIST_FUNCTION_ID, + TA66XX_SC_GET_FLASH_RECORD_INFO_FUNCTION_ID, + TA66XX_SC_READ_FLASH_RECORD_DATA_FUNCTION_ID, + TA66XX_SC_CREATE_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_WRITE_FLASH_RECORD_DATA_FUNCTION_ID, + TA66XX_SC_XCLOSE_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_UPDATE_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_DELETE_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_SQUEEZE_FLASH_RECORDS_FUNCTION_ID, + TA66XX_SC_GET_FLASH_FREE_SPACE_FUNCTION_ID, + TA66XX_SC_GET_BOOT_SEQ_FUNCTION_ID, + TA66XX_SC_DELETE_BOOT_SEQ_FUNCTION_ID, + TA66XX_SC_SET_BOOT_SEQ_FUNCTION_ID, + TA66XX_SC_LOAD_DSP_APPL_FROM_MEMORY_FUNCTION_ID, + TA66XX_SC_LOAD_DSP_APPL_FROM_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_LOAD_FPGA_CNF_FROM_FLASH_RECORD_FUNCTION_ID, + TA66XX_NUMBER_OF_FUNCTIONS +}; +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +//============================================================================= +//============ General SDK API functions declarations ========================= +//============================================================================= + +/** @addtogroup TA66XX_GENERAL TORNADO AMC SDK general API functions + * @{ + */ + +/*------------ TA66XX_set_error() function -------------------------------*//** + * @brief Function should be used on exit from SDK API functions in + * order to set error code and function ID of SDK API functions + * + * @param[in] err - error code; + * @param[in] function_id - function ID of SDK API functions; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_set_error(int32_t err, int32_t function_id); + + +/*------------ TA66XX_get_last_error() function --------------------------*//** + * @brief Function returns error code of last executed API function + * + * @return Error code of last executed API function + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_get_last_error(void); + + +/*------------ TA66XX_get_error_flag() function --------------------------*//** + * @brief Function returns status of ERROR_FLAG for API functions + * + * ERROR_FLAG is set by each API function in case error has been detected. + * ERROR_FLAG can be reset by TA66XX_clear_error_flag() API function + * + * @param[out] error_code - pointer to a variable to receive the error code in + * case error has been detected. In case pointer is NULL, then + * no error code is returned; + * @param[out] error_function_id - pointer to a variable to receive ID of the + * first API function, which has returned with error. In case + * pointer is NULL, then no function ID is returned; + * + * @return Status of ERROR_FLAG: ON or OFF + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_get_error_flag(int32_t *error_code, int32_t *error_function_id); + + +/*------------ TA66XX_clear_error_flag() function ------------------------*//** + * @brief Function clear ERROR_FLAG for API functions + * + * @return Always OK + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_clear_error_flag(void); + + +/*------------ TA66XX_get_error_message() function -----------------------*//** + * @brief Function returns the text interpretation of the error code. + * + * @param[in] error - error code to be interpreted; + * @param[out] error_message - pointer to the returned string. In case pointer + * is NULL, then no text is filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_get_error_message(int32_t error, char *error_message); + + +/*------------ TA66XX_get_function_name() function -----------------------*//** + * @brief Function returns the text interpretation of API function. + * + * @param[in] function_id - ID of the API function to be interpreted; + * @param[out] function_name - pointer to the returned string. In case pointer + * is NULL, then no text is filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_get_function_name(int32_t function_id, char *function_name); + + +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +} +#endif + + + +//============================================================================= +#endif /* __TA66XX_DSP_H__ */ + diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h new file mode 100644 index 00000000..dbc748e0 --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h @@ -0,0 +1,121 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 4A. + Definitions, macros and API functions for DSP Environment. + (C) MicroLAB Systems, 2014-2017 + + + http://www.mlabsys.com + ftp://ftp.mlabsys.com + email: [email protected] + + + Description: + ------------ + This file contains definitions, macros and API functions for TORNADO AMC + modules on-board DSP environment and must be included in the user + C-application for TORNADO AMC modules. + + + Revision history: + ----------------- + rev.1A - 2014, initial release for TORNADO-A6678 board rev.1A. + rev.1B - 2015, fixed some bugs. + rev.1C - 2015, added support for TORNADO-A6678 board rev.1B: + - updated DSP external control registers area; + - updated TA66XX_init_dsp() DSP initialization + function; + - added MMC-to-DSP communication functions in DSP + I2C functions. + rev.2A - 2015, totally redesigned SDK for TORNADO-A6678 board rev.1B; + rev.3A - 2016, added support for TORNADO-A6678/FMC board rev.1A; + rev.3B - 2017: + - added support for TORNADO-A6678/FMC board rev.1B; + rev.4A - 2017: + - added support for TORNADO-AZ/FMC board rev.1A; + + + Notes: + ------ + 1. This C-header file is an include file for TI C6xxx C/C++ Code + Generation Tools, which must be invoked to compile for C66xx DSP + platform. + + 2. This file is best viewed with the TAB setting set to '4'. + + 3. This library uses dynamic memory allocation in erase FLASH functions, + so user should provide enough memory area for dynamic memory allocation + (-heap parameter) and place the section (.sysmem) in the corresponding + memory area in linker command file. + The max requested memory allocation block length is up to FLASH memory + sector length in bytes (128 KB). + + 4. This header file is externally controlled from user C-code by run-time + compiler keys definitions in order to apply board-type specific + definitions to refer to particular definitions included for different + board type: + + __TA66XX_BC_USE_BIOS__ + - if defined in user code prior inclusion of this header file, + then TI SYS/BIOS modules(HWI (Hardware Interrupt) and ECM + (Event Combiner Manager)), will be used to support + C66xx CorePac interrupt controller (INTC). + TI INTC Chip Support Library (CSL) should be used in case + NO embedded operating system is used in user application. + DEFAULT is NOT DEFINED, so CSL INTC library will be used + to support C66xx CorePac interrupt controller. + + Copyright: + ---------- + This utility is supplied free of charge as it is without any obligation + from MicroLAB Systems. No responsibility is assumed for any use or misuse + of these utilities. + +******************************************************************************/ + + +/** + * @file TA66XX_DSP_BC.h + * + * @brief Main include file + * + * This file contains definitions, macros and API functions for TORNADO + * AMC modules on-board DSP environment + * + */ + + +#ifndef __TA66XX_DSP_BC_H__ // check for this file has been already included +#define __TA66XX_DSP_BC_H__ 1 + + +#if defined __TA66XX_BC_USE_BIOS__ +// Include this file to prevent compiler errors +// when using SYS/BIOS +#include <xdc/std.h> +#endif /* __TA66XX_BC_USE_BIOS__ */ + + +// Include general TORNADO AMC SDK defs +#include "TA66XX_DSP.h" + + +//============================================================================= +//------------ board-type specific run-time compiler keys processing ---------- +// (this is required in order to exclude key confusions) + +// Default setting is C6678 DSP definitions +#define __C66XX_SELECT_C6678_DSP__ 1 + +// Finally we must define C-code data type for accessing I/O areas +typedef volatile uint16_t __TA66XX_BC_DSP_XCR_RG_DATA_TYPE__; +typedef volatile uint16_t __TA66XX_BC_FLASH_DATA_TYPE__; +//============================================================================= + + +// Include TORNADO AMC SDK functions +#include "TA66XX_DSP_BC_FUNCTIONS.hxx" + + +//============================================================================= +#endif /* __TA66XX_DSP_BC_H__ */ + diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx new file mode 100644 index 00000000..338a01ee --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx @@ -0,0 +1,1732 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 3B. + (C) MicroLAB Systems, 2014-2017 + + File: TORNADO AMC SDK functions for DSP environment declarations + ----- + + Notes: + ------ + 1. This C-header file contains TORNADO AMC modules SDK functions + for DSP environment declarations and is an include file for + TI C6xxx C/C++ Code Generation Tools, which must be invoked to compile + for TORNADO AMC platform. + + 2. This file is best viewed with the TAB setting set to '4'. + +******************************************************************************/ + + +/** + * @file TA66XX_DSP_BC_FUNCTIONS.hxx + * + * @brief Board control (BC) SDK functions declarations + * + * This file contains declarations of TORNADO AMC modules SDK functions for + * board control + * + */ + + +#ifndef __TA66XX_DSP_BC_FUNCTIONS_HXX__ // check for this file has been already included +#define __TA66XX_DSP_BC_FUNCTIONS_HXX__ 1 + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +//============================================================================= +//============ DSP environment functions ====================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_INIT TORNADO AMC DSP environment init functions + * @{ + */ + + +/** Default DSP interrupt vector for DSP I2C interrupt */ +#define TA66XX_BC_I2C_INTERRUPT_NUMBER_USED 4 + + +/*------------ TA66XX_BC_set_i2c_interrupt_number() function -------------*//** + * @brief Function should be called before calling TA66XX_BC_init() function + * and is used to select DSP interrupt vector number for DSP I2C interrupt. + * + * @param[in] dsp_vector_id - DSP interrupt vector number, which will be used + * for DSP I2C interrupt. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_i2c_interrupt_number(uint32_t dsp_vector_id); + + +/*------------ TA66XX_BC_get_i2c_interrupt_number() function -------------*//** + * @brief Function returns current DSP interrupt vector number for DSP I2C + * interrupt. + * + * @return DSP interrupt vector number, which is used for DSP I2C interrupt. + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_i2c_interrupt_number(void); + + +/** Default DSP interrupt vector for DSP UART interrupt */ +#define TA66XX_BC_UART_INTERRUPT_NUMBER_USED 5 + + +/*------------ TA66XX_BC_set_uart_interrupt_number() function ------------*//** + * @brief Function should be called before calling TA66XX_BC_init() function + * and is used to select DSP interrupt vector number for DSP UART interrupt. + * + * @param[in] dsp_vector_id - DSP interrupt vector number, which will be used + * for DSP UART interrupt. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_uart_interrupt_number(uint32_t dsp_vector_id); + + +/*------------ TA66XX_BC_get_uart_interrupt_number() function ------------*//** + * @brief Function returns current DSP interrupt vector number for DSP UART + * interrupt. + * + * @return DSP interrupt vector number, which is used for DSP UART interrupt. + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_uart_interrupt_number(void); + + +/*------------ TA66XX_BC_init() function ---------------------------------*//** + * @brief Function performs initialization of TORNADO AMC modules + * DSP environment in accordance with board type + * + * The function does the following: + * 1. DSP on-chip caches are configured by default: L1P and L1D caches are + * enabled and set to max available size, L2 cache is disabled so L2 memory + * acts as SRAM. + * 2. DSP main PLL, DDR3 PLL and PASS PLL are configured by default: DSP core + * clock is set to TA66XX_BC_DSP_CORE_SPEED_VALUE, DDR3 and PASS controllers + * to default values + * 3. DDR3 memory is configured and ready to use + * 4. All DSP power domains are enabled + * 5. DSP EMIF-16 bus is configured. + * 6. In case external 1GE interface is installed then DSP SGMII port is + * initialized. + * 7. DSP GPIO pins are configured as outputs and cleared. + * 8. DSP LEDs are enabled. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_init(void); + + +/*------------ TA66XX_BC_get_ddr_area_base_addr() function ---------------*//** + * @brief Function returns DDR3 area base address + * + * @return DDR3 area base address + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_ddr_area_base_addr(void); + + +/*------------ TA66XX_BC_get_ddr_area_length() function ------------------*//** + * @brief Function returns DDR3 area length in bytes + * + * @return DDR3 area length in bytes + * +-----------------------------------------------------------------------------*/ +uint64_t TA66XX_BC_get_ddr_area_length(void); + + +//----------------------------------------------------------------------------- +// These functions are used to map either lower 2 GB DDR3 page or high 2 GB +// DDR3 page of 4GB DDR3 memory area to DSP 32-bit logical memory map. + +/** The lower 2GB DDR3 memory page */ +#define TA66XX_BC_DDR3_MEM_PAGE0 0 +/** The high 2GB DDR3 memory page */ +#define TA66XX_BC_DDR3_MEM_PAGE1 1 +//----------------------------------------------------------------------------- + +/*------------ TA66XX_BC_set_ddr_area_page() function --------------------*//** + * @brief Function sets the specified 2 GB DDR3 memory page (0 or 1) to be + * mapped to DSP 32-bit logical memory map. + * + * This function should be used only in case of 4 GB and more DDR3 memory is + * installed otherwise it does nothing. + * + * @param[in] page - 2 GB DDR3 memory page (0 or 1); + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_ddr_area_page(uint32_t page); + + +/*------------ TA66XX_BC_get_ddr_area_page() function --------------------*//** + * @brief Function returns current selected 2 GB DDR3 memory page (0 or 1) + * which is mapped to DSP 32-bit logical memory map. + * + * @return Current selected 2 GB DDR3 memory page (0 or 1) + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_ddr_area_page(void); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ DSP LED functions ============================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_DSP_LED TORNADO AMC DSP LED functions + * @{ + */ + +/** DSP LED definitions */ +enum TA66XX_BC_DSP_LEDS +{ + TA66XX_BC_DSP_LED0 = 0, /**< DSP LED-0 */ + TA66XX_BC_DSP_LED1, /**< DSP LED-1 */ + TA66XX_BC_DSP_LED2, /**< DSP LED-2 */ + TA66XX_BC_DSP_LED3, /**< DSP LED-3 */ + TA66XX_BC_DSP_LED4, /**< DSP LED-4 */ + TA66XX_BC_DSP_LED5, /**< DSP LED-5 */ + TA66XX_BC_DSP_LED6, /**< DSP LED-6 */ + TA66XX_BC_DSP_LED7 /**< DSP LED-7 */ +}; + +/** DSP LED bitmask definitions */ +enum TA66XX_BC_DSP_LED_BITMASKS +{ + TA66XX_BC_DSP_LED0_BITMASK = 0x0001, /**< DSP LED-0 bitmask */ + TA66XX_BC_DSP_LED1_BITMASK = 0x0002, /**< DSP LED-1 bitmask */ + TA66XX_BC_DSP_LED2_BITMASK = 0x0004, /**< DSP LED-2 bitmask */ + TA66XX_BC_DSP_LED3_BITMASK = 0x0008, /**< DSP LED-3 bitmask */ + TA66XX_BC_DSP_LED4_BITMASK = 0x0010, /**< DSP LED-4 bitmask */ + TA66XX_BC_DSP_LED5_BITMASK = 0x0020, /**< DSP LED-5 bitmask */ + TA66XX_BC_DSP_LED6_BITMASK = 0x0040, /**< DSP LED-6 bitmask */ + TA66XX_BC_DSP_LED7_BITMASK = 0x0080, /**< DSP LED-7 bitmask */ + TA66XX_BC_DSP_LEDS_BITMASK = 0x00ff /**< DSP LEDs bitmask */ +}; + +// Definitions for DSP LEDs used for TORNADO-A6678/FMC rev.1A and later boards +/** DSP LED GREEN-0 */ +#define TA66XX_BC_DSP_LED_GREEN0 TA66XX_BC_DSP_LED0 +#define TA66XX_BC_DSP_LED_GREEN0_BITMASK TA66XX_BC_DSP_LED0_BITMASK +/** DSP LED RED-0 */ +#define TA66XX_BC_DSP_LED_RED0 TA66XX_BC_DSP_LED1 +#define TA66XX_BC_DSP_LED_RED0_BITMASK TA66XX_BC_DSP_LED1_BITMASK +/** DSP LED GREEN-1 */ +#define TA66XX_BC_DSP_LED_GREEN1 TA66XX_BC_DSP_LED2 +#define TA66XX_BC_DSP_LED_GREEN1_BITMASK TA66XX_BC_DSP_LED2_BITMASK +/** DSP LED RED-1 */ +#define TA66XX_BC_DSP_LED_RED1 TA66XX_BC_DSP_LED3 +#define TA66XX_BC_DSP_LED_RED1_BITMASK TA66XX_BC_DSP_LED3_BITMASK +/** DSP LED GREEN-2 */ +#define TA66XX_BC_DSP_LED_GREEN2 TA66XX_BC_DSP_LED4 +#define TA66XX_BC_DSP_LED_GREEN2_BITMASK TA66XX_BC_DSP_LED4_BITMASK +/** DSP LED YELLOW-0 */ +#define TA66XX_BC_DSP_LED_YELLOW0 TA66XX_BC_DSP_LED5 +#define TA66XX_BC_DSP_LED_YELLOW0_BITMASK TA66XX_BC_DSP_LED5_BITMASK +/** DSP LED YELLOW-1 */ +#define TA66XX_BC_DSP_LED_YELLOW1 TA66XX_BC_DSP_LED6 +#define TA66XX_BC_DSP_LED_YELLOW1_BITMASK TA66XX_BC_DSP_LED6_BITMASK +/** DSP LED RED-2 */ +#define TA66XX_BC_DSP_LED_RED2 TA66XX_BC_DSP_LED7 +#define TA66XX_BC_DSP_LED_RED2_BITMASK TA66XX_BC_DSP_LED7_BITMASK + +/** DSP LED aliases for compatibility with TORNADO-A6678 rev.1B-1 board definitions */ +#define TA66XX_BC_DSP_LED_RED TA66XX_BC_DSP_LED_RED0 +#define TA66XX_BC_DSP_LED_AMBER TA66XX_BC_DSP_LED_YELLOW0 +#define TA66XX_BC_DSP_LED_BLUE TA66XX_BC_DSP_LED_GREEN2 +#define TA66XX_BC_DSP_LED_WHITE TA66XX_BC_DSP_LED_RED2 + + +// Aliases for DSP LEDs used for TORNADO-A6678 rev.1B-1 board +/** DSP LED GREEN-0 */ +#define TA6678_REV1B_BC_DSP_LED_GREEN0 TA66XX_BC_DSP_LED0 +#define TA6678_REV1B_BC_DSP_LED_GREEN0_BITMASK TA66XX_BC_DSP_LED0_BITMASK +/** DSP LED GREEN-1 */ +#define TA6678_REV1B_BC_DSP_LED_GREEN1 TA66XX_BC_DSP_LED1 +#define TA6678_REV1B_BC_DSP_LED_GREEN1_BITMASK TA66XX_BC_DSP_LED1_BITMASK +/** DSP LED YELLOW-0 */ +#define TA6678_REV1B_BC_DSP_LED_YELLOW0 TA66XX_BC_DSP_LED2 +#define TA6678_REV1B_BC_DSP_LED_YELLOW0_BITMASK TA66XX_BC_DSP_LED2_BITMASK +/** DSP LED YELLOW-1 */ +#define TA6678_REV1B_BC_DSP_LED_YELLOW1 TA66XX_BC_DSP_LED3 +#define TA6678_REV1B_BC_DSP_LED_YELLOW1_BITMASK TA66XX_BC_DSP_LED3_BITMASK +/** DSP LED AMBER */ +#define TA6678_REV1B_BC_DSP_LED_AMBER TA66XX_BC_DSP_LED4 +#define TA6678_REV1B_BC_DSP_LED_AMBER_BITMASK TA66XX_BC_DSP_LED4_BITMASK +/** DSP LED RED */ +#define TA6678_REV1B_BC_DSP_LED_RED TA66XX_BC_DSP_LED5 +#define TA6678_REV1B_BC_DSP_LED_RED_BITMASK TA66XX_BC_DSP_LED5_BITMASK +/** DSP LED BLUE */ +#define TA6678_REV1B_BC_DSP_LED_BLUE TA66XX_BC_DSP_LED6 +#define TA6678_REV1B_BC_DSP_LED_BLUE_BITMASK TA66XX_BC_DSP_LED6_BITMASK +/** DSP LED WHITE */ +#define TA6678_REV1B_BC_DSP_LED_WHITE TA66XX_BC_DSP_LED7 +#define TA6678_REV1B_BC_DSP_LED_WHITE_BITMASK TA66XX_BC_DSP_LED7_BITMASK + + + +/*------------ TA66XX_BC_set_dsp_leds_enable() function ------------------*//** + * @brief Function enables or disables on-board DSP LEDs + * + * @param[in] state - DSP LEDs enable state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_leds_enable(uint32_t enable); + + +/*------------ TA66XX_BC_get_dsp_leds_enable_status() function -----------*//** + * @brief Function returns enable status of on-board DSP LEDs + * + * @return DSP LEDs enable state: TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_leds_enable_status(void); + + +/*------------ TA66XX_BC_set_dsp_led_state() function --------------------*//** + * @brief Function sets selected DSP LED to the desired state: ON or OFF + * + * @param[in] led_number - DSP LED number definition; + * @param[in] state - DSP LED state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_led_state(uint32_t led_number, uint32_t state); + + +/*------------ TA66XX_BC_get_dsp_led_state() function --------------------*//** + * @brief Function returns selected DSP LED state: ON or OFF + * + * @param[in] led_number - DSP LED number definition; + * + * @return DSP LED state: TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_led_state(uint32_t led_number); + + +/*------------ TA66XX_BC_set_dsp_leds() function -------------------------*//** + * @brief Function sets selected DSP LEDs to the desired state: ON or OFF + * + * @param[in] led_bitmask - DSP LEDs (ORed) bitmask; + * @param[in] state - DSP LEDs state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_leds(uint32_t led_bitmask, uint32_t state); + + +/*------------ TA66XX_BC_get_dsp_leds() function -------------------------*//** + * @brief Function returns selected DSP LEDs state: ON or OFF + * + * @param[in] led_bitmask - DSP LEDs (ORed) bitmask; + * + * @return DSP LEDs state + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_leds(uint32_t led_bitmask); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ DSP-to-FPGA GPIO functions ===================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_DSP_FPGA_GPIO TORNADO AMC DSP-to-FPGA GPIO functions + * @{ + */ + +/** DSP-to-FPGA GPIO pins definitions */ +enum TA66XX_BC_DSP_FPGA_GPIO +{ + TA66XX_BC_DSP_FPGA_GPIO0 = 0, /**< DSP-to-FPGA GPIO pin 0 */ + TA66XX_BC_DSP_FPGA_GPIO1, /**< DSP-to-FPGA GPIO pin 1 */ + TA66XX_BC_DSP_FPGA_GPIO2, /**< DSP-to-FPGA GPIO pin 2 */ + TA66XX_BC_DSP_FPGA_GPIO3, /**< DSP-to-FPGA GPIO pin 3 */ + TA66XX_BC_DSP_FPGA_GPIO4, /**< DSP-to-FPGA GPIO pin 4 */ + TA66XX_BC_DSP_FPGA_GPIO5, /**< DSP-to-FPGA GPIO pin 5 */ + TA66XX_BC_DSP_FPGA_GPIO6, /**< DSP-to-FPGA GPIO pin 6 */ + TA66XX_BC_DSP_FPGA_GPIO7 /**< DSP-to-FPGA GPIO pin 7 */ +}; + +/** DSP-to-FPGA GPIO pins bitmask definitions */ +enum TA66XX_BC_DSP_FPGA_GPIO_BITMASKS +{ + TA66XX_BC_DSP_FPGA_GPIO0_BITMASK = 0x0001, /**< DSP-to-FPGA GPIO pin 0 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO1_BITMASK = 0x0002, /**< DSP-to-FPGA GPIO pin 1 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO2_BITMASK = 0x0004, /**< DSP-to-FPGA GPIO pin 2 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO3_BITMASK = 0x0008, /**< DSP-to-FPGA GPIO pin 3 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO4_BITMASK = 0x0010, /**< DSP-to-FPGA GPIO pin 4 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO5_BITMASK = 0x0020, /**< DSP-to-FPGA GPIO pin 5 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO6_BITMASK = 0x0040, /**< DSP-to-FPGA GPIO pin 6 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO7_BITMASK = 0x0080, /**< DSP-to-FPGA GPIO pin 7 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO_BITMASK = 0x00ff /**< DSP-to-FPGA GPIO pins bitmask */ +}; + + +/** DSP-to-FPGA GPIO pins direction definitions */ +#define TA66XX_BC_DSP_FPGA_GPIO_DIR_OUT C66XX_GPIO_DIR_OUT +#define TA66XX_BC_DSP_FPGA_GPIO_DIR_IN C66XX_GPIO_DIR_IN + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_enable() function ----------*//** + * @brief Function enables or disables on-board DSP-to-FPGA GPIO pins + * + * @param[in] state - DSP-to-FPGA GPIO pins enable state: TA66XX_ON or + * TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_enable(uint32_t enable); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_enable_status() function ---*//** + * @brief Function returns enable status of on-board DSP-to-FPGA GPIO pins + * + * @return DSP-to-FPGA GPIO pins enable state: TA66XX_ON or TA66XX_OFF; + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_enable_status(void); + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_pin_dir() function ---------*//** + * @brief Function sets selected DSP-to-FPGA GPIO pin direction: IN or OUT + * + * @param[in] pin - DSP-to-FPGA GPIO pin number; + * @param[in] dir - DSP-to-FPGA GPIO pin direction: IN or OUT + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_pin_dir(uint32_t pin, uint32_t dir); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_pin_dir() function ---------*//** + * @brief Function returns selected DSP-to-FPGA GPIO pin direction: IN or OUT + * + * @param[in] pin - DSP-to-FPGA GPIO pin number; + * + * @return DSP-to-FPGA GPIO pin direction: IN or OUT + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_pin_dir(uint32_t pin); + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_pin_data() function --------*//** + * @brief Function sets selected DSP-to-FPGA GPIO pin to the desired state: ON + * or OFF + * + * @param[in] pin - DSP-to-FPGA GPIO pin number; + * @param[in] data - DSP-to-FPGA GPIO pin state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_pin_data(uint32_t pin, uint32_t data); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_pin_data() function --------*//** + * @brief Function returns selected DSP-to-FPGA GPIO pin state: ON or OFF + * + * @param[in] pin - DSP-to-FPGA GPIO pin number; + * + * @return DSP-to-FPGA GPIO pin state: TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_pin_data(uint32_t pin); + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_dir() function -------------*//** + * @brief Function sets selected DSP-to-FPGA GPIO pins direction: IN or OUT + * + * @param[in] pin_bitmask - DSP-to-FPGA GPIO pins (ORed) bitmask; + * @param[in] dir - DSP-to-FPGA GPIO pin direction: IN or OUT + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_dir(uint32_t pin_bitmask, uint32_t dir); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_dir() function -------------*//** + * @brief Function returns selected DSP-to-FPGA GPIO pins direction: IN or OUT + * + * @param[in] pin - DSP-to-FPGA GPIO pins (ORed) bitmask; + * + * @return DSP-to-FPGA GPIO pins direction: IN or OUT + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_dir(uint32_t pin_bitmask); + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_data() function ------------*//** + * @brief Function sets selected DSP-to-FPGA GPIO pins to the desired state: ON + * or OFF + * + * @param[in] pin_bitmask - DSP-to-FPGA GPIO pins (ORed) bitmask; + * @param[in] data - DSP-to-FPGA GPIO pins state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_data(uint32_t pin_bitmask, uint32_t data); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_data() function ------------*//** + * @brief Function returns selected DSP-to-FPGA GPIO pins state: ON or OFF + * + * @param[in] pin - DSP-to-FPGA GPIO pins (ORed) bitmask; + * + * @return DSP-to-FPGA GPIO pins state + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_data(uint32_t pin_bitmask); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ DSP GPIO IRQ functions ========================================= +//============================================================================= + +/** @addtogroup TA66XX_BC_DSP_GPIO_IRQ TORNADO AMC DSP GPIO IRQ mapping functions + * @{ + */ + +/** DSP GPIO pins IRQ source definitions */ +enum TA66XX_BC_DSP_GPIO_IRQ_SEL_SOURCE +{ + TA66XX_BC_DSP_GPIO_IRQ_SEL_OFF = 0, /**< DSP IRQ is disabled */ + TA66XX_BC_DSP_GPIO_IRQ_SEL_MMC_TO_DSP_PD_ALERT, /**< MMC-to-DSP power-down alert is used to generate DSP IRQ */ + TA66XX_BC_DSP_GPIO_IRQ_SEL_MMC_TO_DSP_COMM_RQ, /**< MMC-to-DSP communication request is used to generate DSP IRQ */ + TA66XX_BC_DSP_GPIO_IRQ_SEL_1GE_PHY_IRQ /**< 1GE PHY IRQ is used to generate DSP IRQ */ +}; + +/** DSP GPIO-6 and GPIO-7 pins definitions for TA6678 rev.1B and TA6678/FMC rev.1A boards */ +#define TA66XX_BC_DSP_GPIO6_PIN 6 +#define TA66XX_BC_DSP_GPIO7_PIN 7 +/** DSP GPIO-8 and GPIO-9 pins definitions for TA6678/FMC rev.1B and later boards */ +#define TA66XX_BC_DSP_GPIO8_PIN 8 +#define TA66XX_BC_DSP_GPIO9_PIN 9 + + +/*------------ TA66XX_BC_map_dsp_gpio_interrupt() function ---------------*//** + * @brief Function maps IRQ source to selected DSP GPIO pin + * + * @param[in] gpio_pin - DSP GPIO pin; + * @param[in] irq_src - IRQ source; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_map_dsp_gpio_interrupt(uint32_t gpio_pin, uint32_t irq_src); + + +/*------------ TA66XX_BC_unmap_dsp_gpio_interrupt() function -------------*//** + * @brief Function unmaps IRQ source from selected DSP GPIO pin + * + * @param[in] gpio_pin - DSP GPIO pin; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_unmap_dsp_gpio_interrupt(uint32_t gpio_pin); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ UART functions ================================================= +//============================================================================= + +/** @addtogroup TA66XX_BC_UART TORNADO AMC UART functions + * @{ + */ + +/** DSP UART printf-like string max length */ +#define TA66XX_BC_UART_PRINTF_LEN_MAX 1023 + + +/*------------ TA66XX_BC_init_uart() function ---------------------------*//** + * @brief Function inits the DSP UART peripheral + * + * @param[in] baud_rate - desired baud rate; + * @param[in] data_bits - number of data bits; + * @param[in] parity - parity bit; + * @param[in] stop_bits - number of stop bits; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_init_uart(uint32_t baud_rate, uint32_t data_bits, uint32_t parity, uint32_t stop_bits); + + +/*------------ TA66XX_BC_uart_receiver_is_ready() function ---------------*//** + * @brief Function checks if a character is received over DSP UART + * + * @return 1 - a character is received over DSP UART, + * 0 - otherwise + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_receiver_is_ready() C66XX_UART_receiver_is_ready() + + +/*------------ TA66XX_BC_uart_receive_char() function --------------------*//** + * @brief Function receives a character over DSP UART + * + * @return Received character + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_receive_char() C66XX_UART_receive_char() + + +/*------------ TA66XX_BC_uart_transmit_char() function -------------------*//** + * @brief Function transmits a character over DSP UART + * + * @param[in] c - A character to transmit + * + * @return None + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_transmit_char(c) C66XX_UART_transmit_char(c) + + +/*------------ TA66XX_BC_uart_transmit_string() function -----------------*//** + * @brief Function transmits a string until '0' charachter + * + * @param[in] s - A pointer to the string to transmit + * + * @return None + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_transmit_string(s) C66XX_UART_transmit_string(s) + + +/*------------ TA66XX_BC_uart_receive_line_string() function -------------*//** + * @brief Function receives a line ended with CR character, and stores + * received characters into string with '\0' symbol. + * + * @param[in] s - Pointer to a string to store received characters + * + * @return Number of received characters without '\0' symbol. + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_receive_line_string(s) C66XX_UART_receive_line_string(s) + + +/*------------ TA66XX_BC_uart_printf() function --------------------------*//** + * @brief Function prints messages to UART + * + * @param[in] format - format string; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_uart_printf(const char *format, ...); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ EEPROM functions =============================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_EEPROM TORNADO AMC EEPROM memory functions + * @{ + */ + +/*------------ TA66XX_BC_get_eeprom_length() function --------------------*//** + * @brief Function returns on-board EEPROM memory length in bytes + * + * @return On-board EEPROM memory length in bytes + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_eeprom_length(void); + + +/*------------ TA66XX_BC_write_eeprom() function -------------------------*//** + * @brief Function writes data[len] to EEPROM memory starting at memory + * address addr + * + * @param[in] addr - memory address within the chip; + * @param[in] data - pointer to data; + * @param[in] len - data len in bytes; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_eeprom(uint32_t addr, uint8_t *data, uint32_t len); + + +/*------------ TA66XX_BC_read_eeprom() function --------------------------*//** + * @brief Function reads data[len] from EEPROM memory starting at memory + * address addr + * + * @param[in] addr - memory address within the chip; + * @param[out] buf - pointer to data buffer to store data; + * @param[in] len - data len in bytes; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_read_eeprom(uint32_t addr, uint8_t *buf, uint32_t len); + + +/*------------ TA66XX_BC_erase_eeprom() function -------------------------*//** + * @brief Function erases len bytes from EEPROM memory starting at memory + * address addr + * + * @param[in] addr - memory address within the chip; + * @param[in] len - number of bytes to erase; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_erase_eeprom(uint32_t addr, uint32_t len); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Board info functions =========================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_BOARD_INFO TORNADO AMC board info functions + * @{ + */ + + +/** Board info data descriptor IDs */ +#define TA66XX_BC_BOARD_INFO_ID_TA6678_REV1B 1 +#define TA66XX_BC_BOARD_INFO_ID_TA6678FMC_REV1A 2 +#define TA66XX_BC_BOARD_INFO_ID_TA6678FMC_REV1B 3 + + +/** Board temperature data descriptor */ +typedef struct +{ + float temp_pcb, /**< PCB current temperature */ + temp_dsp, /**< DSP current temperature */ + temp_fpga; /**< FPGA current temperature */ + + // TEMP zone classification status + // This var is set according to TA6678_MC_TEMP_ZONE_ID_xxxx defs. + uint32_t temp_zone_id; /**< Temperature zone ID */ + + // 8-bit integer thresholds for MMC TEMP zones + // These thresholds are used to classify summary temparature, which MMC derives + // from PCB, DSP and FPGA temperatures. + char overheated_low_zone_threshold, /**< OVERHEATED low threshold (P/S will be switched OFF at this threshold and upper) */ + hot_low_zone_threshold, /**< HOT low threshold (P/S will be not switched ON at this threshold and upper) */ + warm3_low_zone_threshold, /**< WARM3 low threshold */ + warm2_low_zone_threshold, /**< WARM2 low threshold */ + warm1_low_zone_threshold, /**< WARM1 low threshold */ + normal_low_zone_threshold, /**< NORMAL low threshold */ + cold1_low_zone_threshold, /**< COLD1 low threshold */ + cold2_low_zone_threshold, /**< COLD2 low threshold */ + cold3_low_zone_threshold, /**< COLD3 low threshold (P/S will be not switched ON below this threshold) */ + frosty_low_zone_threshold; /**< FROSTY low threshold (P/S will be switched OFF below this threshold) */ + + // 8-bit integer thresholds for AMC TEMP zones for every on-board temp sensor + char amc_pcb_temp_noncritical_threshold, /**< PCB temperature AMC UPPER NON-CRITICAL ASSERTING EVENT threshold */ + amc_pcb_temp_critical_threshold, /**< PCB temperature AMC UPPER CRITICAL ASSERTING EVENT threshold */ + amc_pcb_temp_nonrecoverable_threshold, /**< PCB temperature AMC UPPER NON-RECOVERABLE ASSERTING EVENT threshold */ + amc_pcb_temp_hysteresis, /**< PCB temperature AMC positive going hysteresis */ + + amc_dsp_temp_noncritical_threshold, /**< DSP temperature AMC UPPER NON-CRITICAL ASSERTING EVENT threshold */ + amc_dsp_temp_critical_threshold, /**< DSP temperature AMC UPPER CRITICAL ASSERTING EVENT threshold */ + amc_dsp_temp_nonrecoverable_threshold, /**< DSP temperature AMC UPPER NON-RECOVERABLE ASSERTING EVENT threshold */ + amc_dsp_temp_hysteresis, /**< DSP temperature AMC positive going hysteresis */ + + amc_fpga_temp_noncritical_threshold, /**< FPGA temperature AMC UPPER NON-CRITICAL ASSERTING EVENT threshold */ + amc_fpga_temp_critical_threshold, /**< FPGA temperature AMC UPPER CRITICAL ASSERTING EVENT threshold */ + amc_fpga_temp_nonrecoverable_threshold, /**< FPGA temperature AMC UPPER NON-RECOVERABLE ASSERTING EVENT threshold */ + amc_fpga_temp_hysteresis; /**< FPGA temperature AMC positive going hysteresis */ + +} TA66XX_BC_TEMP_DATA_DD; +// Board temperature data descriptor length +#define TA66XX_BC_TEMP_DATA_DD_LEN sizeof(TA66XX_BC_TEMP_DATA_DD) + + +/** Board current power data descriptor for TA6678 rev.1B-1 board */ +typedef struct +{ + float v_12v, /**< Input +12V power supply voltage value */ + i_12v, /**< Input +12V power supply current value */ + v_3v3_aux, /**< On-board auxiliary +3.3V power supply voltage value */ + i_3v3_aux, /**< On-board auxiliary +3.3V power supply current value */ + v_mc, /**< Module management power supply voltage value */ + i_mc, /**< Module management power supply current value */ + v_3v3, /**< On-board +3.3V power supply voltage value */ + i_3v3, /**< On-board +3.3V power supply current value */ + v_2v5, /**< On-board +2.5V power supply voltage value */ + i_2v5, /**< On-board +2.5V power supply current value */ + v_1v8, /**< On-board +1.8V power supply voltage value */ + i_1v8, /**< On-board +1.8V power supply current value */ + v_1v5, /**< On-board +1.5V power supply voltage value */ + i_1v5, /**< On-board +1.5V power supply current value */ + v_1v0, /**< On-board +1.0V power supply voltage value */ + i_1v0, /**< On-board +1.0V power supply current value */ + v_ddr_vtt, /**< On-board DDR3 VTT power supply voltage value */ + v_dsp_vcore, /**< On-board DSP core power supply voltage value */ + i_dsp_vcore, /**< On-board DSP core power supply current value */ + v_fpga_vcore, /**< On-board FPGA core power supply voltage value */ + i_fpga_vcore, /**< On-board FPGA core power supply current value */ + v_fpga_mgtavcc, /**< On-board FPGA MGTAVCC power supply voltage value */ + v_fpga_mgtavtt; /**< On-board FPGA MGTAVTT power supply voltage value */ + +} TA6678_REV1B_BC_POWER_DATA_DD; +// Board current power data descriptor for TA6678 rev.1B-1 board length +#define TA6678_REV1B_BC_POWER_DATA_DD_LEN sizeof(TA6678_REV1B_BC_POWER_DATA_DD) + + +/** Board current power data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + float power_12v, /**< Input +12V power supply value */ + power_fpga_core, /**< On-board FPGA core power supply value */ + power_dsp_core, /**< On-board DSP core power supply value */ + v_12v, /**< Input +12V power supply voltage value */ + i_12v, /**< Input +12V power supply current value */ + i_fpga_core, /**< On-board FPGA core power supply current value */ + i_dsp_core; /**< On-board DSP core power supply current value */ + +} TA66XX_BC_PRIMARY_POWER_DATA_DD; +// Board current power data descriptor length +#define TA66XX_BC_PRIMARY_POWER_DATA_DD_LEN sizeof(TA66XX_BC_PRIMARY_POWER_DATA_DD) + + +/** Board current power data union */ +typedef union +{ + TA6678_REV1B_BC_POWER_DATA_DD ta6678_rev1b_dd; + TA66XX_BC_PRIMARY_POWER_DATA_DD primary_power_dd; +} POWER_DATA_DD; + + +/** Board current power data descriptor */ +typedef struct +{ + unsigned id; // ID to decode the UNION structure type + POWER_DATA_DD power_data_dd; + +} TA66XX_BC_POWER_DATA_DD; +// Board current power data descriptor length +#define TA66XX_BC_POWER_DATA_DD_LEN sizeof(TA66XX_BC_POWER_DATA_DD) + + +/** FMC interface power data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + float power_fmc_12v, /**< FMC I/F +12V power supply value */ + power_fmc_3v3, /**< FMC I/F +3.3V power supply value */ + power_fmc_vadj, /**< FMC I/F Vadj power supply value */ + v_fmc_12v, /**< FMC I/F +12V power supply voltage value */ + i_fmc_12v, /**< FMC I/F +12V power supply current value */ + v_fmc_3v3, /**< FMC I/F +3.3V power supply voltage value */ + i_fmc_3v3, /**< FMC I/F +3.3V power supply current value */ + v_fmc_vadj, /**< FMC I/F Vadj power supply voltage value */ + i_fmc_vadj, /**< FMC I/F Vadj power supply current value */ + v_fmc_vio_b_m2c, /**< FMC I/F VIO_B_M2C power supply voltage value */ + v_fmc_vref_a_m2c, /**< FMC I/F VREF_A_M2C power supply voltage value */ + v_fmc_vref_b_m2c; /**< FMC I/F VREF_B_M2C power supply voltage value */ + +} TA66XX_BC_FMC_POWER_DATA_DD; +// FMC interface power data descriptor length +#define TA66XX_BC_FMC_POWER_DATA_DD_LEN sizeof(TA66XX_BC_FMC_POWER_DATA_DD) + + +/** Max string length in device info structure */ +#define TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX 32 +#define TA66XX_BC_DEVICE_PN_STRING_LEN_MAX 64 +#define TA66XX_BC_DEVICE_HW_REVISION_STRING_LEN_MAX 16 + + +/** Board info data descriptor for TA6678 rev.1B-1 board */ +typedef struct +{ + uint32_t op_mode; /**< Operation mode: '0' - stand-alone mode, '1' - AMC host mode */ + uint32_t amc_slot_id; /**< AMC slot ID (in case AMC host mode is used) */ + uint8_t manufacturing_date_day_of_month; /**< Manufacturing day: 1..31 */ + uint8_t manufacturing_date_month; /**< Manufacturing month: 1..12 ('1' - January) */ + uint16_t manufacturing_date_year; /**< Manufacturing year: 2015.. */ + char device_sn[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< Device serial number */ + char mmc_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< MMC firmware revision string */ + char tammc_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< TAMMC firmware revision string */ + char mmc_core_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< MMC core firmware revision string */ +} TA6678_REV1B_BC_DEVICE_INFO_DATA_DD; +// Board info data descriptor for TA6678 rev.1B-1 board length +#define TA6678_REV1B_BC_DEVICE_INFO_DATA_DD_LEN sizeof(TA6678_REV1B_BC_DEVICE_INFO_DATA_DD) + + +/** Board info data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + uint32_t op_mode; /**< Operation mode: '0' - stand-alone mode, '1' - AMC host mode */ + uint32_t amc_slot_id; /**< AMC slot ID (in case AMC host mode is used) */ + uint8_t manufacturing_date_day_of_month; /**< Manufacturing day: 1..31 */ + uint8_t manufacturing_date_month; /**< Manufacturing month: 1..12 ('1' - January) */ + uint16_t manufacturing_date_year; /**< Manufacturing year: 2015.. */ + char manufacturer_name[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< Manufacturer name */ + char device_name[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< Device name */ + char device_pn[TA66XX_BC_DEVICE_PN_STRING_LEN_MAX]; /**< Device part number */ + char device_sn[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< Device serial number */ + char device_hw_revision[TA66XX_BC_DEVICE_HW_REVISION_STRING_LEN_MAX]; /**< Device H/W revision */ + char mmc_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< MMC firmware revision string */ + char tammc_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< TAMMC firmware revision string */ + char mmc_core_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< MMC core firmware revision string */ +} TA66XX_BC_FULL_DEVICE_INFO_DATA_DD; +// Board info data descriptor length +#define TA66XX_BC_FULL_DEVICE_INFO_DATA_DD_LEN sizeof(TA66XX_BC_FULL_DEVICE_INFO_DATA_DD) + + +/** Board current power data union */ +typedef union +{ + TA6678_REV1B_BC_DEVICE_INFO_DATA_DD ta6678_rev1b_dd; + TA66XX_BC_FULL_DEVICE_INFO_DATA_DD ta66xx_full_device_info_dd; +} DEVICE_INFO_DATA_DD; + + +/** Board current power data descriptor */ +typedef struct +{ + uint32_t id; // ID to decode the UNION structure type + DEVICE_INFO_DATA_DD device_info_data_dd; + +} TA66XX_BC_DEVICE_INFO_DATA_DD; +// Board current power data descriptor length +#define TA66XX_BC_DEVICE_INFO_DATA_DD_LEN sizeof(TA66XX_BC_DEVICE_INFO_DATA_DD) + + +/** Hardware configuration info data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + uint32_t fpga_ddr0_len; /**< FPGA DDR memory bank #0 length in MB: 0 - not installed */ + uint32_t fpga_ddr1_len; /**< FPGA DDR memory bank #1 length in MB: 0 - not installed */ + uint32_t cpu_ddr_len; /**< CPU DDR memory length in MB: 0 - not installed */ + uint32_t flash_len; /**< FLASH memory length in MB: 0 - not installed */ + uint32_t mram_len; /**< MRAM memory length in KB: 0 - not installed */ + uint32_t i2c_eeprom_len; /**< I2C EEPROM memory length in KB: 0 - not installed */ + uint32_t cpu_clk_freq_id; /**< CPU input clock frequency in MHz: 0 - not available */ + uint32_t x1ge0_phy_installed_id; /**< External 1GE PHY #0 installed ID: 0 - not installed */ + uint32_t x1ge1_phy_installed_id; /**< External 1GE PHY #1 installed ID: 0 - not installed */ + uint32_t sfp0_if_installed_id; /**< SFP interface #0 installed ID: 0 - not installed */ + uint32_t sfp1_if_installed_id; /**< SFP interface #1 installed ID: 0 - not installed */ + uint32_t qsfp_if_installed_id; /**< QSFP interface installed ID: 0 - not installed */ + uint32_t fmc_if_installed_id; /**< FMC interface installed ID: 0 - not installed */ + uint32_t sd_slot_installed_id; /**< uSD slot installed ID: 0 - not installed */ +} TA66XX_BC_HW_CFG_INFO_DATA_DD; +// Hardware configuration info data descriptor length +#define TA66XX_BC_HW_CFG_INFO_DATA_DD_LEN sizeof(TA66XX_BC_HW_CFG_INFO_DATA_DD) + + +/** Max string length in FMC info structure */ +#define TA66XX_BC_FMC_STATUS_STRING_LEN_MAX 48 +#define TA66XX_BC_FMC_INFO_STRING_LEN_MAX 64 +#define TA66XX_BC_MANUFACTURING_TIME_STRING_LEN_MAX 32 + + +/** FMC info data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + char fmc_status_text[TA66XX_BC_FMC_STATUS_STRING_LEN_MAX]; /**< FMC status */ + char manufacturer_name[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Manufacturer name */ + char device_name[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Device name */ + char device_pn[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Device part number */ + char device_sn[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Device serial number */ + char device_version[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Device version */ + char manufacturing_time[TA66XX_BC_MANUFACTURING_TIME_STRING_LEN_MAX]; /**< Manufacturing time */ +} TA66XX_BC_FMC_INFO_DATA_DD; +// FMC info data descriptor length +#define TA66XX_BC_FMC_INFO_DATA_DD_LEN sizeof(TA66XX_BC_FMC_INFO_DATA_DD) + + + +/*------------ TA66XX_BC_get_device_info() function ----------------------*//** + * @brief Function returns AMC module device info: operation mode, serial + * number, manufacturing date, firmware revisions + * + * @param[out] info_dd - pointer to a buffer that receives device info data + * descriptor in case function is completed without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_device_info(TA66XX_BC_DEVICE_INFO_DATA_DD *info_dd); + + +/*------------ TA66XX_BC_get_hw_cfg_info() function ----------------------*//** + * @brief Function returns AMC module hardware configuration info: installed + * memories, interfaces, etc. + * + * @param[out] info_dd - pointer to a buffer that receives hardware + * configuration data descriptor in case function is completed + * without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_hw_cfg_info(TA66XX_BC_HW_CFG_INFO_DATA_DD *info_dd); + + +/*------------ TA66XX_BC_get_fmc_info() function -------------------------*//** + * @brief Function returns FMC module device info: installed status, device + * name, serial number, manufacturing date, firmware revisions, etc. + * + * @param[out] info_dd - pointer to a buffer that receives FMC info data + * descriptor in case function is completed without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_fmc_info(TA66XX_BC_FMC_INFO_DATA_DD *info_dd); + + +/*------------ TA66XX_BC_get_temp_state() function -----------------------*//** + * @brief Function returns AMC module temperature monitor current info + * + * @param[out] temp_data_dd - pointer to a buffer that receives board + * temperature data descriptor in case function is completed + * without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_temp_state(TA66XX_BC_TEMP_DATA_DD *temp_data_dd); + + +/*------------ TA66XX_BC_get_power_state() function ----------------------*//** + * @brief Function returns AMC module power monitor current info + * + * @param[out] power_data_dd - pointer to a buffer that receives board power + * data descriptor in case function is completed without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_power_state(TA66XX_BC_POWER_DATA_DD *power_data_dd); + + +/*------------ TA66XX_BC_get_fmc_power_state() function ------------------*//** + * @brief Function returns FMC module power monitor current info + * + * @param[out] fmc_power_data_dd - pointer to a buffer that receives FMC + * module power data descriptor in case function is completed + * without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_fmc_power_state(TA66XX_BC_FMC_POWER_DATA_DD *fmc_power_data_dd); + + +/*------------ TA66XX_BC_set_mmc_to_dsp_rq() function --------------------*//** + * @brief Function sets MMC-to-DSP request from DSP (for test purposes) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_mmc_to_dsp_rq(void); + + +/*------------ TA66XX_BC_set_mmc_power_down_notification() function ------*//** + * @brief Function sets MMC-to-DSP power down notification from DSP + * (for test purposes) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_mmc_power_down_notification(void); + + +/*------------ TA66XX_BC_get_sfp_info() function -------------------------*//** + * @brief Function returns identification info about installed SFP + * transceiver: 256-byte array read from address 0x50 (identification info + * according to SFF-8472) and 256-byte array read from address 0x51 (digital + * diagnostic monitoring interface (DDMI) data) + * + * @param[out] id_data - pointer to a buffer that receives 256-byte array read + * from address 0x50 (identification info according to SFF-8472). + * In case pointer is NULL, then no data are filled in; + * @param[out] ddmi_data - pointer to a buffer that receives 256-byte array + * read from address 0x51 (DDMI data). In case pointer is NULL, + * then no data are filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_sfp_info(uint8_t *id_data, uint8_t *ddmi_data); + + +/** @}*/ + +//============================================================================= + + + +//============================================================================= +//============ FPGA functions ================================================= +//============================================================================= + +/** @addtogroup TA66XX_BC_FPGA TORNADO AMC FPGA functions + * @{ + */ + +/** FPGA host interface (HIF) configuration data descriptor */ +typedef struct +{ + uint32_t w_setup; /**< Write strobe setup EMIF-16 cycles */ + uint32_t w_strobe; /**< Write strobe duration EMIF-16 cycles */ + uint32_t w_hold; /**< Write strobe hold EMIF-16 cycles */ + uint32_t r_setup; /**< Read strobe setup EMIF-16 cycles */ + uint32_t r_strobe; /**< Read strobe duration EMIF-16 cycles */ + uint32_t r_hold; /**< Read strobe hold EMIF-16 cycles */ + uint32_t turn_around; /**< Turn around EMIF-16 cycles */ +} TA66XX_BC_FPGA_HIF_CNF_DD; +// FPGA HIF configuration data descriptor length in bytes +#define TA66XX_BC_FPGA_HIF_CNF_DD_LEN sizeof(TA66XX_BC_FPGA_HIF_CNF_DD) + + +/*------------ TA66XX_BC_set_fpga_hif_cnf() function ---------------------*//** + * @brief Function sets new configuration to FPGA host interface according to + * supplied parameters + * + * @param[in] cfg_dd - pointer to new FPGA HIF configuration data descriptor; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_fpga_hif_cnf(TA66XX_BC_FPGA_HIF_CNF_DD *cfg_dd); + + +/*------------ TA66XX_BC_get_fpga_hif_cnf() function ---------------------*//** + * @brief Function returns current configuration of FPGA host interface + * + * @param[in] cfg_dd - pointer to buffer to receive current FPGA HIF + * configuration data descriptor; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_fpga_hif_cnf(TA66XX_BC_FPGA_HIF_CNF_DD *cfg_dd); + + +/*------------ TA66XX_BC_get_fpga_hif_base_addr() function ---------------*//** + * @brief Function returns FPGA host interface base address + * + * @return FPGA host interface base address + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_fpga_hif_base_addr(void); + + +/*------------ TA66XX_BC_get_fpga_hif_length() function ------------------*//** + * @brief Function returns FPGA host interface length in bytes + * + * @return FPGA host interface length in bytes + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_fpga_hif_length(void); + + +/*------------ TA66XX_BC_set_fpga_hif_reset() function -------------------*//** + * @brief Function sets or releases FPGA host interface reset + * + * @param[in] state - FPGA host interface reset state: ON or OFF + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_fpga_hif_reset(uint32_t state); + + +/*------------ TA66XX_BC_get_fpga_hif_reset_state() function -------------*//** + * @brief Function returns FPGA host interface reset state + * + * @return FPGA host interface reset state: ON or OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_fpga_hif_reset_state(void); + + +/*------------ TA66XX_BC_read_fpga_hif_byte() function -------------------*//** + * @brief Function reads a byte from FPGA host interface at address addr. + * + * @param[in] addr - FPGA address to read from + * + * @return A byte read from FPGA host interface + * +-----------------------------------------------------------------------------*/ +uint8_t TA66XX_BC_read_fpga_hif_byte(uint32_t addr); + + +/*------------ TA66XX_BC_write_fpga_hif_byte() function ------------------*//** + * @brief Function writes a byte to FPGA host interface at address addr. + * + * @param[in] addr - FPGA address to write to + * @param[in] v - A byte to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_fpga_hif_byte(uint32_t addr, uint8_t v); + + +/*------------ TA66XX_BC_read_fpga_hif_w16() function --------------------*//** + * @brief Function reads a 16-bit word from FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to read from + * + * @return A 16-bit word read from FPGA host interface + * +-----------------------------------------------------------------------------*/ +uint16_t TA66XX_BC_read_fpga_hif_w16(uint32_t addr); + + +/*------------ TA66XX_BC_write_fpga_hif_w16() function -------------------*//** + * @brief Function writes a 16-bit word to FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to write to + * @param[in] v - A 16-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_fpga_hif_w16(uint32_t addr, uint16_t v); + + +/*------------ TA66XX_BC_read_fpga_hif_w32() function --------------------*//** + * @brief Function reads a 32-bit word from FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to read from + * + * @return A 32-bit word read from FPGA host interface + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_read_fpga_hif_w32(uint32_t addr); + + +/*------------ TA66XX_BC_write_fpga_hif_w32() function -------------------*//** + * @brief Function writes a 32-bit word to FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to write to + * @param[in] v - A 32-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_fpga_hif_w32(uint32_t addr, uint32_t v); + + +/*------------ TA66XX_BC_read_fpga_hif_w64() function --------------------*//** + * @brief Function reads a 64-bit word from FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to read from + * + * @return A 64-bit word read from FPGA host interface + * +-----------------------------------------------------------------------------*/ +uint64_t TA66XX_BC_read_fpga_hif_w64(uint32_t addr); + + +/*------------ TA66XX_BC_write_fpga_hif_w64() function -------------------*//** + * @brief Function writes a 64-bit word to FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to write to + * @param[in] v - A 64-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_fpga_hif_w64(uint32_t addr, uint64_t v); + + +/*------------ TA66XX_BC_clear_fpga_cnf() function -----------------------*//** + * @brief Function clears FPGA configuration memory + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_clear_fpga_cnf(void); + + +/*------------ TA66XX_BC_load_fpga_cnf() function ------------------------*//** + * @brief Function loads FPGA firmware file using the supported configuration + * interfaces (serial or parallel) + * + * @param[in] addr - address where FPGA firmware file data were saved; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_load_fpga_cnf(uint32_t addr); + + +/*------------ TA66XX_BC_get_fpga_cnf_status() function ------------------*//** + * @brief Function returns FPGA configuration memory status: either + * loaded by FPGA firmware file or not + * + * @return TA66XX_OK - FPGA configuration memory is loaded, + * TA66XX_FPGA_CNF_LOAD_ERR - FPGA configuration memory is cleared. + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_fpga_cnf_status(void); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ FLASH functions ================================================ +//============================================================================= + +/** @addtogroup TA66XX_BC_FLASH TORNADO AMC FLASH API functions + * @{ + */ + + +/** FLASH memory sector is protected for write/erase operations */ +#define TA66XX_BC_FLASH_SECTOR_PROTECTED 1 +/** FLASH memory sector is unprotected for write/erase operations */ +#define TA66XX_BC_FLASH_SECTOR_UNPROTECTED 0 + + +/*------------ TA66XX_BC_get_flash_area_base_addr() function -------------*//** + * @brief Function returns FLASH area base address + * + * @return FLASH area base address + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_flash_area_base_addr(void); + + +/*------------ TA66XX_BC_get_flash_length() function ---------------------*//** + * @brief Function returns on-board FLASH memory length in bytes + * + * @return On-board FLASH memory length in bytes + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_flash_length(void); + + +/*------------ TA66XX_BC_get_flash_hw_wp_enable_status() function --------*//** + * @brief Function returns enable status of on-board FLASH memory hardware + * (via on-board switch) write-protection + * + * @return On-board FLASH memory hardware write-protection enable state: + * TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_flash_hw_wp_enable_status(void); + + +/*------------ TA66XX_BC_get_flash_sw_wp_enable_status() function --------*//** + * @brief Function returns enable status of on-board FLASH memory software + * write-protection + * + * @return On-board FLASH memory software write-protection enable state: + * TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_flash_sw_wp_enable_status(void); + + +/*------------ TA66XX_BC_set_flash_sw_wp_enable() function ---------------*//** + * @brief Function enables or disables on-board FLASH memory software + * write-protection + * + * @param[in] enable - on-board FLASH memory software write-protection enable + * state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_flash_sw_wp_enable(uint32_t enable); + + +/*------------ TA66XX_BC_erase_flash() function --------------------------*//** + * @brief Function erases FLASH block, which starts from address a + * and of size len (in bytes) + * + * @param[in] addr - Block start address (in bytes) + * @param[in] len - block length (in bytes) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_erase_flash(uint32_t addr, uint32_t len); + + +/** Flag to disable FLASH memory erasing before write operation */ +#define TA66XX_BC_FLASH_ERASE_IS_DISABLED 0 +/** Flag to enable FLASH memory erasing before write operation */ +#define TA66XX_BC_FLASH_ERASE_IS_ENABLED 1 + + +/*------------ TA66XX_BC_write_flash() function --------------------------*//** + * @brief Function writes data block of size len to FLASH address a + * The function erases FLASH before writing data to FLASH if erase input + * parameter is set. + * + * @param[in] a - FLASH address (in bytes) + * @param[in] ptr - data block to write + * @param[in] len - data block length (in bytes) + * @param[in] erase - flag to enable FLASH erasing before write operation + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_flash(uint32_t a, void *ptr, uint32_t len, uint32_t erase); + + +/*------------ TA66XX_BC_write_flash_byte() function ---------------------*//** + * @brief Function writes data byte d to FLASH address a + * + * @param[in] a - FLASH address (in bytes) + * @param[in] d - data byte to write + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_flash_byte(uint32_t addr, uint8_t d); + + +/*------------ TA66XX_BC_write_flash_w16() function ----------------------*//** + * @brief Function writes 16-bit data word d to FLASH address a + * + * @param[in] addr - FLASH address (in bytes) + * @param[in] d - 16-bit data word to write + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_flash_w16(uint32_t addr, uint16_t d); + + +/*------------ TA66XX_BC_write_flash_w32() function ----------------------*//** + * @brief Function writes 32-bit data word d to FLASH address a + * + * @param[in] addr - FLASH address (in bytes) + * @param[in] d - 32-bit data word to write + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_flash_w32(uint32_t addr, uint32_t d); + + +/*------------ TA66XX_BC_read_flash() function ---------------------------*//** + * @brief Function reads data block of size len from FLASH address a + * + * @param[in] addr - FLASH address (in bytes) + * @param[in] ptr - pointer to data buffer to store data block + * @param[in] len - data block length (in bytes) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_read_flash(uint32_t addr, void *ptr, uint32_t len); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ MRAM functions ================================================= +//============================================================================= + +/** @addtogroup TA66XX_BC_MRAM TORNADO AMC MRAM API functions + * @{ + */ + + +/*------------ TA66XX_BC_get_mram_area_base_addr() function --------------*//** + * @brief Function returns MRAM area base address + * + * @return MRAM area base address + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_mram_area_base_addr(void); + + +/*------------ TA66XX_BC_get_mram_length() function ----------------------*//** + * @brief Function returns on-board MRAM memory length in bytes + * + * @return On-board MRAM memory length in bytes + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_mram_length(void); + + +/*------------ TA66XX_BC_get_mram_sw_wp_enable_status() function ---------*//** + * @brief Function returns enable status of on-board MRAM memory software + * write-protection + * + * @return On-board MRAM memory software write-protection enable state: + * TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_mram_sw_wp_enable_status(void); + + +/*------------ TA66XX_BC_set_mram_sw_wp_enable() function ----------------*//** + * @brief Function enables or disables on-board MRAM memory software + * write-protection + * + * @param[in] enable - on-board MRAM memory software write-protection enable + * state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_mram_sw_wp_enable(uint32_t enable); + + +/*------------ TA66XX_BC_read_mram_byte() function -----------------------*//** + * @brief Function reads a byte from MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to read from + * + * @return A byte read from MRAM memory + * +-----------------------------------------------------------------------------*/ +uint8_t TA66XX_BC_read_mram_byte(uint32_t addr); + + +/*------------ TA66XX_BC_write_mram_byte() function ----------------------*//** + * @brief Function writes a byte to MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to write to + * @param[in] v - A byte to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_mram_byte(uint32_t addr, uint8_t v); + + +/*------------ TA66XX_BC_read_mram_w16() function ------------------------*//** + * @brief Function reads a 16-bit word from MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to read from + * + * @return A 16-bit word read from MRAM memory + * +-----------------------------------------------------------------------------*/ +uint16_t TA66XX_BC_read_mram_w16(uint32_t addr); + + +/*------------ TA66XX_BC_write_mram_w16() function -----------------------*//** + * @brief Function writes a 16-bit word to MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to write to + * @param[in] v - A 16-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_mram_w16(uint32_t addr, uint16_t v); + + +/*------------ TA66XX_BC_read_mram_w32() function ------------------------*//** + * @brief Function reads a 32-bit word from MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to read from + * + * @return A 32-bit word read from MRAM memory + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_read_mram_w32(uint32_t addr); + + +/*------------ TA66XX_BC_write_mram_w32() function -----------------------*//** + * @brief Function writes a 32-bit word to MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to write to + * @param[in] v - A 32-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_mram_w32(uint32_t addr, uint32_t v); + + +/*------------ TA66XX_BC_read_mram_w64() function ------------------------*//** + * @brief Function reads a 64-bit word from MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to read from + * + * @return A 64-bit word read from MRAM memory + * +-----------------------------------------------------------------------------*/ +uint64_t TA66XX_BC_read_mram_w64(uint32_t addr); + + +/*------------ TA66XX_BC_write_mram_w64() function -----------------------*//** + * @brief Function writes a 64-bit word to MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to write to + * @param[in] v - A 64-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_mram_w64(uint32_t addr, uint64_t v); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Gigabit Ethernet (GbE) Switch functions ======================== +//============================================================================= + +/** @addtogroup TA66XX_BC_GBE TORNADO AMC Gigabit Ethernet Switch functions + * @{ + */ + +/** Gigabit Ethernet ports count available at the board */ +#define TA66XX_BC_GBE_PORT_COUNT 2 + +/** DSP SGMII port number which is routed to AMC connector */ +#define TA66XX_BC_GBE_PORT_AMC_PORT_NUMBER 0 +/** Alias for DSP SGMII port-0 number */ +#define TA66XX_BC_GBE_PORT_AMC0_PORT_NUMBER TA66XX_BC_GBE_PORT_AMC_PORT_NUMBER +/** DSP SGMII port number which is routed to external PHY */ +#define TA66XX_BC_GBE_PORT_X1GE_PORT_NUMBER 1 +/** Alias for DSP SGMII port-1 number */ +#define TA66XX_BC_GBE_PORT_AMC1_PORT_NUMBER TA66XX_BC_GBE_PORT_X1GE_PORT_NUMBER + + +/** Gigabit Ethernet port type */ +typedef enum +{ + TA66XX_BC_GBE_PORT_TYPE_NONE = 0, /**< Gigabit Ethernet port is not used */ + TA66XX_BC_GBE_PORT_TYPE_PHY, /**< Gigabit Ethernet port is connected to on-board PHY */ + TA66XX_BC_GBE_PORT_TYPE_AMC, /**< Gigabit Ethernet port is connected to the backplane AMC chassis */ + TA66XX_BC_GBE_PORT_TYPE_MAX /**< End of port type */ +} TA66XX_BC_GBE_PORT_TYPE; + + +/** Gigabit Ethernet port link status */ +typedef enum +{ + TA66XX_BC_GBE_PORT_LINK_STATUS_DOWN = 0, /**< Gigabit Ethernet port link is down */ + TA66XX_BC_GBE_PORT_LINK_STATUS_UP, /**< Gigabit Ethernet port link is up */ + TA66XX_BC_GBE_PORT_LINK_STATUS_MAX /**< End of link status */ +} TA66XX_BC_GBE_PORT_LINK_STATUS; + + +/** T-AMC Gigabit Ethernet port data descriptor */ +typedef struct +{ + uint32_t number; /**< Port number */ + TA66XX_BC_GBE_PORT_TYPE type; /**< Gigabit Ethernet port type */ + TA66XX_BC_GBE_PORT_LINK_STATUS link_status; /**< Gigabit Ethernet port link status */ + uint8_t mac_address[6]; /**< MAC (physical) address of the port */ +} TA66XX_BC_GBE_PORT_DD; +// T-AMC Gigabit Ethernet port data descriptor length in bytes +#define TA66XX_BC_GBE_PORT_DD_LEN sizeof(TA66XX_BC_GBE_PORT_DD) + + +/** IP address string max size in bytes*/ +#define TA66XX_BC_IP_ADDRESS_LEN_MAX 16 +/** Host name max size in bytes*/ +#define TA66XX_BC_HOSTNAME_LEN_MAX 256 + + +/** Static IP configuration */ +#define TA66XX_BC_IP_CFG_TYPE_STATIC 0 +/** Dynamic (DHCP) IP configuration */ +#define TA66XX_BC_IP_CFG_TYPE_DYNAMIC 1 + + +/*------------ TA66XX_BC_init_gbe_port() function ------------------------*//** + * @brief Function initializes selected DSP Gigabit Ethernet port + * + * @param[in] port - DSP Gigabit Ethernet port number + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_init_gbe_port(uint32_t port); + + +/*------------ TA66XX_BC_get_gbe_port_info() function --------------------*//** + * @brief Function returns Gigabit Ethernet port info: port mode, MAC address, + * link status + * + * @param[in] port - Gigabit Ethernet port number for which port info should + * be returned + * @param[out] port_dd - pointer to a buffer to which Gigabit Ethernet port + * data descriptor should be returned + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_gbe_port_info(uint32_t port, TA66XX_BC_GBE_PORT_DD *port_dd); + + +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +} +#endif + + + +//============================================================================= +#endif /* __TA66XX_BC_DSP_BC_FUNCTIONS_HXX__ */ diff --git a/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h b/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h new file mode 100644 index 00000000..d61af0e9 --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h @@ -0,0 +1,649 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 3A. + TI SYS/BIOS RTOS abstraction layer for TORNADO AMC embedded controllers. + (C) MicroLAB Systems, 2014-2015 + + + File: This file contains TI SYS/BIOS RTOS abstraction layer definitions + ----- for TORNADO AMC embedded controllers, which is used for various + low-level drivers (LLD) and libraries that the application use. + + + Revision history: + ----------------- + rev.1A - 2014, initial release for TORNADO-A6678 board + rev.2A - 2015, totally redesigned SDK; + rev.3A - 2016, added support for TORNADO-A6678/FMC board rev.1A; + +******************************************************************************/ + + +/** + * @file TA66XX_OSAL.h + * + * @brief RTOS abstraction layer definitions + * + * This file contains TI SYS/BIOS RTOS abstraction layer (OSAL) definitions for + * TORNADO AMC embedded controllers, which is used for various + * low-level drivers (LLD) and libraries that the application use. + * + */ + + +#ifndef __TA66XX_OSAL_H__ // check for this file has been already included +#define __TA66XX_OSAL_H__ 1 + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +//============================================================================= +//------------ Definitions ---------------------------------------------------- +//============================================================================= +/** @addtogroup TA66XX_OSAL_GENERAL OS abstraction layer (OSAL) general definitions + * @{ + */ + +// Hardware semaphore defs +#define TA66XX_OSAL_CPPI_HW_SEM 1 /**< CPPI LLD hardware semaphore */ +#define TA66XX_OSAL_QMSS_HW_SEM 2 /**< QMSS LLD hardware semaphore */ +#define TA66XX_OSAL_SRIO_HW_SEM 3 /**< SRIO LLD hardware semaphore */ +#define TA66XX_OSAL_SPI_HW_SEM 4 /**< SPI driver hardware semaphore */ + +/** Macro to define high-priority QMSS queue for accumulator (depends on DSP event ID and core number) */ +#define TA66XX_OSAL_set_qmss_queue_acc(eventid, core) (704 + (eventid - 48) * 8 + core) + +// Interrupts and event IDs used by NIMU library (DSP core 0 is assumed to be used) +#define TA66XX_OSAL_ETHERNET_AMC_EVENTID 48 /**< Ethernet AMC port event - used by NIMU library */ +#define TA66XX_OSAL_ETHERNET_AMC_INTERRUPT 7 /**< Ethernet AMC port interrupt - used by NIMU library */ +/** QMSS queue for AMC Ethernet port accumulator (depends on TA66XX_OSAL_ETHERNET_AMC_EVENTID) */ +#define TA66XX_OSAL_ETHERNET_AMC_QMSS_QUEUE_ACC TA66XX_OSAL_set_qmss_queue_acc(TA66XX_OSAL_ETHERNET_AMC_EVENTID, 0) +#define TA66XX_OSAL_ETHERNET_PHY_EVENTID 49 /**< Ethernet PHY port event - used by NIMU library */ +#define TA66XX_OSAL_ETHERNET_PHY_INTERRUPT 8 /**< Ethernet PHY port interrupt - used by NIMU library */ +/** QMSS queue for PHY Ethernet port accumulator (depends on TA66XX_OSAL_ETHERNET_PHY_EVENTID) */ +#define TA66XX_OSAL_ETHERNET_PHY_QMSS_QUEUE_ACC TA66XX_OSAL_set_qmss_queue_acc(TA66XX_OSAL_ETHERNET_PHY_EVENTID, 0) + +// Interrupts and event IDs used by SRIO (DSP core 0 is assumed to be used) +#define TA66XX_OSAL_SRIO_MESSAGES_EVENTID 50 /**< SRIO event ID used by messages (Type 9 and Type 11) */ +#define TA66XX_OSAL_SRIO_INTERRUPT 9 /**< SRIO interrupt */ +/** QMSS queue for SRIO accumulator (depends on TA66XX_OSAL_SRIO_MESSAGES_EVENTID) */ +#define TA66XX_OSAL_SRIO_QMSS_QUEUE_ACC TA66XX_OSAL_set_qmss_queue_acc(TA66XX_OSAL_SRIO_MESSAGES_EVENTID, 0) +#define TA66XX_OSAL_SRIO_DIO_EVENTID 20 /**< SRIO event ID used by DirectIO (INTDST(n + 16), n - core number) */ +/** @}*/ +//============================================================================= + + + +//============================================================================= +//------------ Global variables ----------------------------------------------- +//============================================================================= +extern uint32_t qmssMallocCounter; +extern uint32_t qmssFreeCounter; +extern uint32_t cppiMallocCounter; +extern uint32_t cppiFreeCounter; +extern uint32_t srioMallocCounter; +extern uint32_t srioFreeCounter; +extern uint32_t srioDataBufferMallocCounter; +extern uint32_t srioDataBufferFreeCounter; +//============================================================================= + + + +//============================================================================= +//============ T-AMC controllers OSAL functions declarations ================== +//============================================================================= +/** @addtogroup TA66XX_OSAL_FUNCTIONS TORNADO AMC OSAL functions + * @{ + */ + + +//============================================================================= +//============ QMSS LLD OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_qmssBeginMemAccess() function ------------------------*//** + * @brief Function is used to indicate that a block of memory is about to be + * accessed + * + * If the memory block is cached then this indicates that the application + * would need to ensure that the cache is updated with the data from the actual + * memory + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_qmssBeginMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_qmssEndMemAccess() function --------------------------*//** + * @brief Function is used to indicate that the block of memory has finished + * being accessed + * + * If the memory block is cached then the application would need to ensure that + * the contents of the cache are updated immediately to the actual memory. + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_qmssEndMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_qmssMalloc() function --------------------------------*//** + * @brief Function implements the memory allocation library function + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +Ptr Osal_qmssMalloc(uint32_t num_bytes); + + +/*------------ Osal_qmssFree() function ----------------------------------*//** + * @brief Function implements the memory free library function + * + * This function frees up memory allocated using Osal_qmssMalloc() + * function call. + * + * @param[in] dataPtr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_qmssFree(Ptr dataPtr, uint32_t num_bytes); + + +/*------------ Osal_qmssCsEnter() function -------------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @return Handle used to lock critical section + * +-----------------------------------------------------------------------------*/ +void *Osal_qmssCsEnter(void); + + +/*------------ Osal_qmssCsExit() function --------------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_qmssCsEnter() API. + * + * @param[in] CsHandle - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_qmssCsExit(void *CsHandle); + +//============================================================================= + + + +//============================================================================= +//============ CPPI LLD OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_cppiBeginMemAccess() function ------------------------*//** + * @brief Function is used to indicate that a block of memory is about to be + * accessed + * + * If the memory block is cached then this indicates that the application + * would need to ensure that the cache is updated with the data from the actual + * memory + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_cppiBeginMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_cppiEndMemAccess() function --------------------------*//** + * @brief Function is used to indicate that the block of memory has finished + * being accessed + * + * If the memory block is cached then the application would need to ensure that + * the contents of the cache are updated immediately to the actual memory. + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_cppiEndMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_cppiMalloc() function --------------------------------*//** + * @brief Function implements the memory allocation library function + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +Ptr Osal_cppiMalloc(uint32_t num_bytes); + + +/*------------ Osal_cppiFree() function ----------------------------------*//** + * @brief Function implements the memory free library function + * + * This function frees up memory allocated using Osal_cppiMalloc() + * function call. + * + * @param[in] dataPtr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_cppiFree(Ptr dataPtr, uint32_t num_bytes); + + +/*------------ Osal_cppiCsEnter() function -------------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @return Handle used to lock critical section + * +-----------------------------------------------------------------------------*/ +void *Osal_cppiCsEnter(void); + + +/*------------ Osal_cppiCsExit() function --------------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_cppiCsEnter() API. + * + * @param[in] CsHandle - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_cppiCsExit(void *CsHandle); + +//============================================================================= + + +#ifdef __TA66XX_FUNCTIONS_INCLUDE_SRIO__ + + +//============================================================================= +//============ SRIO LLD OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_srioBeginMemAccess() function ------------------------*//** + * @brief Function is used to indicate that a block of memory is about to be + * accessed + * + * If the memory block is cached then this indicates that the application + * would need to ensure that the cache is updated with the data from the actual + * memory + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioBeginMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_srioEndMemAccess() function --------------------------*//** + * @brief Function is used to indicate that the block of memory has finished + * being accessed + * + * If the memory block is cached then the application would need to ensure that + * the contents of the cache are updated immediately to the actual memory. + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioEndMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_srioBeginDescriptorAccess() function -----------------*//** + * @brief Function is invoked by the SRIO LLD to indicate that a descriptor is + * being accessed. + * + * @param[in] drvHandle - driver instance for which descriptor is being + * accessed + * @param[in] ptr - pointer to the descriptor being accessed + * @param[in] descSize - size of the descriptor (valid only for driver managed + * configuration) + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioBeginDescriptorAccess(Srio_DrvHandle drvHandle, void *ptr, uint32_t descSize); + + +/*------------ Osal_srioEndDescriptorAccess() function -------------------*//** + * @brief Function is invoked by the SRIO LLD to indicate that a descriptor is + * finished being accessed. + * + * @param[in] drvHandle - driver instance for which descriptor is being + * accessed + * @param[in] ptr - pointer to the descriptor being accessed + * @param[in] descSize - size of the descriptor (valid only for driver managed + * configuration) + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioEndDescriptorAccess(Srio_DrvHandle drvHandle, void *ptr, uint32_t descSize); + + +/*------------ Osal_srioMalloc() function --------------------------------*//** + * @brief Function implements the memory allocation library function + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +Ptr Osal_srioMalloc(uint32_t num_bytes); + + +/*------------ Osal_srioFree() function ----------------------------------*//** + * @brief Function implements the memory free library function + * + * This function frees up memory allocated using Osal_srioMalloc() + * function call. + * + * @param[in] dataPtr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioFree(Ptr dataPtr, uint32_t num_bytes); + + +/*------------ Osal_dataBufferInitMemory() function ----------------------*//** + * @brief Function is used to allocate a block of memory for all the data + * buffer operations. This function is called by the application. + * + * @param[in] dataBufferSize - size of each data buffer + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize); + + +/*------------ Osal_srioDataBufferMalloc() function ----------------------*//** + * @brief Function is used to allocate a data buffer of the specified size. + * Data buffers should always be allocated from the global address space. + * + * @param[in] numBytes - number of bytes to be allocated + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +void *Osal_srioDataBufferMalloc(uint32_t numBytes); + + +/*------------ Osal_srioDataBufferFree() function ------------------------*//** + * @brief Function is used to clean up a previously allocated data buffer + * block. All data buffers are in the global address space. + * + * @param[in] ptr - pointer to the memory block to be cleaned up + * @param[in] numBytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioDataBufferFree(void *ptr, uint32_t numBytes); + + +/*------------ Osal_srioLog() function -----------------------------------*//** + * @brief Function is used to log the messages from SRIO LLD on the console. + * + * @param[in] fmt - formatted string + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioLog(String fmt, ... ); + + +/*------------ Osal_srioCreateSem() function -----------------------------*//** + * @brief Function is used to create a critical section. + * + * @return Semaphore handle created + * +-----------------------------------------------------------------------------*/ +void *Osal_srioCreateSem(void); + + +/*------------ Osal_srioDeleteSem() function -----------------------------*//** + * @brief Function is used to delete a critical section. + * + * @param[in] semHandle - semaphore handle to be deleted + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioDeleteSem(void *semHandle); + + +/*------------ Osal_srioPendSem() function -------------------------------*//** + * @brief Function is used to pend on a semaphore + * + * @param[in] semHandle - semaphore handle on which the API will pend + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioPendSem(void *semHandle); + + +/*------------ Osal_srioPostSem() function -------------------------------*//** + * @brief Function is used to post a semaphore + * + * @param[in] semHandle - semaphore handle which will be posted + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioPostSem(void *semHandle); + + +/*------------ Osal_srioEnterMultipleCoreCriticalSection() function ------*//** + * @brief Function is used to protect the driver shared resources across + * multiple cores. + * + * @return Handle used to lock critical section + * +-----------------------------------------------------------------------------*/ +void *Osal_srioEnterMultipleCoreCriticalSection(void); + + +/*------------ Osal_srioExitMultipleCoreCriticalSection() function -------*//** + * @brief Function is called to end the critical section which was protecting + * shared resources from access across multiple cores. + * + * @param[in] critSectHandle - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioExitMultipleCoreCriticalSection(void *critSectHandle); + + +/*------------ Osal_srioEnterSingleCoreCriticalSection() function --------*//** + * @brief Function is used to provide critical section to prevent access of + * shared resources from single core and multiple threads. + * + * @param[in] drvHandle - driver handle which needs critical section to + * protect its resources + * + * @return Handle used to lock critical section + * +-----------------------------------------------------------------------------*/ +void *Osal_srioEnterSingleCoreCriticalSection(Srio_DrvHandle drvHandle); + + +/*------------ Osal_srioExitSingleCoreCriticalSection() function ---------*//** + * @brief Function is called to end the critical section access of shared + * resources from single cores. + * + * @param[in] drvHandle - driver handle which needs critical section to + * protect its resources + * @param[in] critSectHandle - critical handle retreived by + * Osal_srioEnterSingleCoreCriticalSection() function call + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioExitSingleCoreCriticalSection(Srio_DrvHandle drvHandle, void *critSectHandle); + +//============================================================================= + + +#endif /* __TA66XX_FUNCTIONS_INCLUDE_SRIO__ */ + + +//============================================================================= +//============ NIMU LLD OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_nimuMalloc() function --------------------------------*//** + * @brief Function implements the memory allocate function for the NIMU + * library. + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * @param[in] alignment - alignment of allocated memory block in bytes + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +Ptr Osal_nimuMalloc(uint32_t num_bytes, uint32_t alignment); + + +/*------------ Osal_nimuFree() function ----------------------------------*//** + * @brief Function implements the memory free function for the NIMU library. + * + * This function frees up memory allocated using Osal_nimuMalloc() + * function call. + * + * @param[in] dataPtr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_nimuFree(Ptr dataPtr, uint32_t num_bytes); + +//============================================================================= + + + +//============================================================================= +//============ PASS LLD OSAL functions ======================================== +//============================================================================= + + +/*------------ Osal_paBeginMemAccess() function --------------------------*//** + * @brief Function is used to indicate that a block of memory is about to be + * accessed + * + * If the memory block is cached then this indicates that the application + * would need to ensure that the cache is updated with the data from the actual + * memory + * + * @param[in] addr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_paBeginMemAccess(Ptr addr, uint32_t size); + + +/*------------ Osal_paEndMemAccess() function ----------------------------*//** + * @brief Function is used to indicate that the block of memory has finished + * being accessed + * + * If the memory block is cached then the application would need to ensure that + * the contents of the cache are updated immediately to the actual memory. + * + * @param[in] addr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_paEndMemAccess(Ptr addr, uint32_t size); + + +/*------------ Osal_paMtCsEnter() function -------------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @param[out] key - pointer to a variable to receive a handle for unlocking + * critical section + + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_paMtCsEnter(uint32_t *key); + + +/*------------ Osal_paMtCsExit() function --------------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_paMtCsEnter() API. + * + * @param[in] key - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_paMtCsExit(uint32_t key); + +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +} +#endif + + + +//============================================================================= +#endif /* __TA66XX_OSAL_H__ */ diff --git a/ports/c667x/ccs/example_build/include/TASDK_ERR.h b/ports/c667x/ccs/example_build/include/TASDK_ERR.h new file mode 100644 index 00000000..8245e95b --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TASDK_ERR.h @@ -0,0 +1,87 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 4A. + (C) MicroLAB Systems, 2015-2017 + + + File: TORNADO AMC SDK functions errors + ----- + +******************************************************************************/ + + +/** + * @file TASDK_ERR.h + * + * @brief SDK functions errors + * + * This file contains TORNADO AMC SDK functions errors + * + */ + + +#ifndef __TASDK_ERR_H__ // check for this file has been already included +#define __TASDK_ERR_H__ 1 + + +//============================================================================= +//============ Returned error codes =========================================== +//============================================================================= +/** @addtogroup TASDK_ERRORS SDK API functions returned error codes + * @{ + */ +#define TASDK_OK 0 /**< No errors */ +#define TASDK_PARAM_ERR -100 /**< Erroneous function parameter */ +#define TASDK_INVALID_HW_ERR -101 /**< Invalid H/W error (invalid board, etc.) */ +#define TASDK_HW_ERR -102 /**< H/W error (error writing to the DSP control registers, etc) */ +#define TASDK_SYS_CALL_ERR -103 /**< system API call error */ +#define TASDK_INVALID_DSP_CORE_ERR -104 /**< Only DSP core 0 may call the function */ +#define TASDK_INVALID_DSP_CORE_BOOT_ADDR_ERR -105 /**< Invalid DSP core boot address */ +#define TASDK_API_OPEN_ERR -106 /**< API has not been open */ +#define TASDK_MMC_TO_CPU_COMM_CHECKSUM_ERR -150 /**< Invalid data frame checksum */ +#define TASDK_MMC_TO_CPU_COMM_DATA_BUF_LEN_ERR -151 /**< Data buffer is not large enough to store received data frame */ +#define TASDK_MMC_TO_CPU_COMM_INV_CMD_ERR -152 /**< Invalid command */ +#define TASDK_MMC_TO_CPU_COMM_RECV_DATA_LEN_ERR -153 /**< Invalid received data length */ +#define TASDK_MMC_TO_CPU_COMM_RECV_DATA_INV_ERR -154 /**< Received data is invalid */ +#define TASDK_MMC_TO_CPU_COMM_TIMEOUT_ERR -155 /**< MMC-to-DSP communication timeout error */ +#define TASDK_SFP_NOT_INSTALLED_ERR -156 /**< SFP module is not installed */ +#define TASDK_FMC_NOT_INSTALLED_ERR -157 /**< FMC module is not installed */ +#define TASDK_FMC_INFO_INVALID_ERR -158 /**< FMC module info is invalid */ +#define TASDK_FLASH_INV_DEV_ERR -200 /**< unsupported FLASH device */ +#define TASDK_FLASH_ERASE_ERR -201 /**< FLASH erase error */ +#define TASDK_FLASH_WR_ERR -202 /**< FLASH write error */ +#define TASDK_FLASH_CANNOT_WR_ERR -203 /**< FLASH contents does not allow to write this data */ +#define TASDK_FLASH_INV_RD_ERR -204 /**< invalid FLASH read data during AUTO-SELECT */ +#define TASDK_FLASH_INFO_NOT_MATCH_ERR -205 /**< FLASH info from the FLASH chip does not match FLASH_LEN_ID from System Configuration register */ +#define TASDK_FLASH_SECTOR_WRPROT_ERR -206 /**< FLASH sector is write-protected */ +#define TASDK_FLASH_WR_BUF_ABORT_ERR -207 /**< FLASH write-to-buffer program is aborted */ +#define TASDK_FLASH_HW_WP_ERR -208 /**< FLASH writes are disabled by on-board switch */ +#define TASDK_FLASH_WR_DISABLED_ERR -209 /**< FLASH writes are disabled by application */ +#define TASDK_FPGA_CNF_BITFILE_HD_FORMAT_ERR -500 /**< invalid FPGA bitfile header format */ +#define TASDK_FPGA_CNF_LOAD_ERR -501 /**< error during FPGA configuration */ +#define TASDK_FPGA_CNF_CRC_ERR -502 /**< CRC check failed during FPGA configuration */ +#define TASDK_FPGA_CNF_LOAD_LEN_ERR -503 /**< not all the data has been loaded */ +#define TASDK_FPGA_CNF_BITFILE_INV_PART_ERR -504 /**< invalid FPGA bitfile header part name */ +#define TASDK_FPGA_CNF_INV_IF_ERR -505 /**< invalid FPGA configuration interface selected */ +#define TASDK_FLASH_RECORD_GLOBAL_HD_NOT_VALID_ERR -600 /**< FLASH record global header is invalid */ +#define TASDK_FLASH_RECORD_HD_NOT_VALID_ERR -601 /**< FLASH record header is invalid */ +#define TASDK_FLASH_RECORD_HD_LIST_NOT_VALID_ERR -602 /**< FLASH record header list is invalid */ +#define TASDK_FLASH_RECORD_FREE_SPACE_ERR -603 /**< not available free space in FLASH */ +#define TASDK_FLASH_RECORD_CHECKSUM_ERR -604 /**< FLASH record checksum mismatch */ +#define TASDK_FLASH_RECORD_ALREADY_OPENED_ERR -605 /**< another FLASH record is opened for writing */ +#define TASDK_FLASH_RECORD_INVALID_LOAD_ADDR_ERR -606 /**< invalid FLASH record load address */ +#define TASDK_FLASH_RECORD_INV_NUMBER_ERR -607 /**< invalid FLASH record number */ +#define TASDK_FLASH_BOOT_SEQ_NOT_VALID_ERR -608 /**< FLASH boot sequence is invalid */ +#define ELF_LOADER_BASE_ERR -1000 /**< ELF file loader base error */ +#define ELF_LOADER_PARAM_ERR (ELF_LOADER_BASE_ERR) /**< erroneous function parameter */ +#define ELF_LOADER_INV_ELF_HEADER_ERR (ELF_LOADER_BASE_ERR - 1) /**< invalid ELF header */ +#define ELF_LOADER_INV_FILE_TYPE_ERR (ELF_LOADER_BASE_ERR - 2) /**< invalid file type (non-executable) */ +#define ELF_LOADER_INV_ENTRY_POINT_ERR (ELF_LOADER_BASE_ERR - 3) /**< invalid entry-point address */ +#define ELF_LOADER_INV_SEGMENT_ERR (ELF_LOADER_BASE_ERR - 4) /**< invalid or missing segment data */ +/** @}*/ +//============================================================================= + + + +//============================================================================= +#endif /* __TASDK_ERR_H__ */ + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.ccsproject b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.ccsproject new file mode 100644 index 00000000..9c03abfb --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.ccsproject @@ -0,0 +1,14 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<?ccsproject version="1.0"?> +<projectOptions> + <deviceVariant value="TMS320C66XX.TMS320C6678"/> + <deviceFamily value="C6000"/> + <deviceEndianness value="little"/> + <codegenToolVersion value="7.4.20"/> + <isElfFormat value="true"/> + <connection value="common/targetdb/connections/TIXDS100usb_Connection.xml"/> + <rts value="libc.a"/> + <templateProperties value="id=com.ti.common.project.core.emptyProjectWithMainTemplate,"/> + <isTargetManual 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+ </sourceEntries> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> + </cconfiguration> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <project id="sample_threadx.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.869979204" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType"/> + </storageModule> + <storageModule moduleId="refreshScope"/> + <storageModule moduleId="scannerConfiguration"/> + <storageModule moduleId="org.eclipse.cdt.core.language.mapping"> + <project-mappings> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/> + </project-mappings> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> +</cproject> diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.project b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.project new file mode 100644 index 00000000..b18fc136 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.project @@ -0,0 +1,89 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>sample_threadx_c6678evm</name> + <comment></comment> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <arguments> + <dictionary> + <key>?name?</key> + <value></value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.append_environment</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.autoBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildArguments</key> + <value>-k</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildCommand</key> + <value>${CCS_UTILS_DIR}/bin/gmake</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildLocation</key> + <value>${BuildDirectory}</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.cleanBuildTarget</key> + <value>clean</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.contents</key> + <value>org.eclipse.cdt.make.core.activeConfigSettings</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableAutoBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableCleanBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableFullBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.fullBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.stopOnError</key> + <value>false</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key> + <value>true</value> + </dictionary> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>com.ti.ccstudio.core.ccsNature</nature> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.core.ccnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <variableList> + <variable> + <name>ORIGINAL_PROJECT_ROOT</name> + <value>file:/C:/release/threadx/sample_threadx_c6678evm</value> + </variable> + </variableList> +</projectDescription> diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.codan.core.prefs b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..f653028c --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.debug.core.prefs b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..2adc7b1d --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.core.resources.prefs b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..093dbb95 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,6 @@ +eclipse.preferences.version=1 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c new file mode 100644 index 00000000..31e8056b --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c @@ -0,0 +1,441 @@ +/* + * board_setup.c + * + */ + + +#include "board_setup.h" +#include "C66XX.h" +#include <string.h> + + +//============================================================================= +//============ General definitions ============================================ +//============================================================================= +// DSP Timer-8 definition +#define C66XX_DSP_TIMER C66XX_TIMER_8 +// DSP Timer-8 output frequency in Hz +#define C66XX_DSP_TIMER_FREQ 100 +/* DSP Timer-8 interrupt event ID */ +#define C66XX_DSP_TIMER_EVENT_ID 67 +//============================================================================= + + +//============================================================================= +//============ Global functions =============================================== +//============================================================================= +void _tx_nmi_vector(void); +void _tx_int4_vector(void); +void _tx_int5_vector(void); +void _tx_int6_vector(void); +void _tx_int7_vector(void); +void _tx_int8_vector(void); +void _tx_int9_vector(void); +void _tx_int10_vector(void); +void _tx_int11_vector(void); +void _tx_int12_vector(void); +void _tx_int13_vector(void); +void _tx_int14_vector(void); +void _tx_int15_vector(void); +//============================================================================= + + +//============================================================================= +//============ Static functions =============================================== +//============================================================================= +static int32_t tx_timer_init(C66XX_TIMER timer, uint32_t frequency); +static int32_t tx_interrupt_init(void); +//============================================================================= + + +/*------------ init_output_timer() function ----------------------------------- + * DESCRIPTION: Function initializes Timer64 module + * ARGUMENTS: + * None + * RETURNED VALUE: Error code +-----------------------------------------------------------------------------*/ +static int32_t tx_timer_init(C66XX_TIMER timer, uint32_t frequency) +{ + int32_t r; + C66XX_TIMER_CFG_DD cfg_dd; + + // Reset 64-bit timer + if ((r = C66XX_TIMER_reset(timer, C66XX_TIMER_HW_CFG_64BIT)) != C66XX_OK) + goto exit; + + // Fill configuration data descriptor + memset(&cfg_dd, 0, C66XX_TIMER_CFG_DD_LEN); + cfg_dd.timer_mode = C66XX_TIMER_MODE_32BIT_UNCHAINED; + cfg_dd.timer_high.clk_src_output_mode = C66XX_TIMER_CLK_OUTPUT_MODE_CLK; + // Init DSP Timer64 module + if ((r = C66XX_TIMER_init(timer, frequency, &cfg_dd)) != C66XX_OK) + goto exit; + + // Enable timer interrupt + if ((r = C66XX_TIMER_enable_interrupts(timer, C66XX_TIMER_HW_CFG_32BIT_HIGH)) != C66XX_OK) + goto exit; + + // Start 32-bit timer high to enable continuously + if ((r = C66XX_TIMER_start(timer, C66XX_TIMER_HW_CFG_32BIT_HIGH, C66XX_TIMER_COUNT_MODE_CONTINUOUSLY)) != C66XX_OK) + goto exit; + + // TIMER module configuration is completed + printf("Timer #%u configuration is completed\n", timer); + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ tx_interrupt_init() function ----------------------------------- + * DESCRIPTION: Function initializes CorePack interrupt module + * ARGUMENTS: + * None + * RETURNED VALUE: Error code +-----------------------------------------------------------------------------*/ +static int32_t tx_interrupt_init(void) +{ + int32_t r; + + // Set DSP interrupt handlers to the ones defined in tx_initialize_low_level.asm + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_NMI, _tx_nmi_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_4, _tx_int4_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_5, _tx_int5_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_6, _tx_int6_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_7, _tx_int7_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_8, _tx_int8_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_9, _tx_int9_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_10, _tx_int10_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_11, _tx_int11_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_12, _tx_int12_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_13, _tx_int13_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_14, _tx_int14_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_15, _tx_int15_vector)) != C66XX_OK) + goto exit; + + /* CorePack interrupt module configuration is completed */ + printf("INTC configuration is completed\n"); + // Exit without errors + r = C66XX_OK; + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ hardware_setup() function -------------------------------------- + * DESCRIPTION: Function intializes board hardware + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +int hardware_setup() +{ + platform_init_flags init_flags; + platform_init_config init_config; + platform_info p_info; + int32_t r; + + /* + * Initialize all platform peripherals with default values: + * PLL, DDR, TCSL, PHY, ECC + */ + init_flags.pll = 1; + init_flags.ddr = 1; + init_flags.tcsl = 1; + init_flags.phy = 1; + init_flags.ecc = 0; + memset(&init_config, 0, sizeof(platform_init_config)); + if ((r = platform_init(&init_flags, &init_config)) != Platform_EOK) + goto exit; + + /* Initialize platform UART */ + if ((r = platform_uart_init()) != Platform_EOK) + goto exit; + if ((r = platform_uart_set_baudrate(115200)) != Platform_EOK) + goto exit; + + /* Get platform info */ + platform_get_info(&p_info); + /* Write data to the UART */ + platform_write("Platform library version is %s\n", p_info.version); + platform_write("Board name is %s\n", p_info.board_name); + platform_write("Board serial number is %s\n", p_info.serial_nbr); + platform_write("Board revision ID is %u\n", p_info.board_rev); + platform_write("CPU name is %s\n", p_info.cpu.name); + platform_write("CPU revision ID is %u\n", p_info.cpu.revision_id); + platform_write("Number of CPU cores is %u\n", p_info.cpu.core_count); + platform_write("CPU frequency is %u MHz\n", p_info.frequency); + + // Init CorePac INTC + if ((r = C66XX_INT_init_core()) != C66XX_OK) + goto exit; + + // Init DSP Timer + if ((r = tx_timer_init(C66XX_DSP_TIMER, C66XX_DSP_TIMER_FREQ)) != C66XX_OK) + goto exit; + + // Init DSP interrupt controller + if ((r = tx_interrupt_init()) != C66XX_OK) + goto exit; + + printf("Board is initialized\n"); + /* Exit with no errors */ + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ tx_nmi_handler() function -------------------------------------- + * DESCRIPTION: Function handles NMI interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_nmi_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int4_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT4 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int4_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int5_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT5 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int5_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int6_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT6 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int6_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int7_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT7 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int7_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int8_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT8 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int8_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int9_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT9 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int9_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int10_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT10 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int10_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int11_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT11 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int11_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int12_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT12 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int12_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int13_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT13 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int13_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int14_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT14 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int14_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int15_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT15 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int15_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +//============================================================================= +//============ Platform OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_platformMalloc() function ----------------------------*//** + * @brief Function implements the memory allocate function for the platform + * library. + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * @param[in] alignment - alignment of allocated memory block in bytes + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +uint8_t *Osal_platformMalloc(uint32_t num_bytes, uint32_t alignment) +{ + // Allocate memory from default system heap + return (NULL); +} +//----------------------------------------------------------------------------- + + +/*------------ Osal_platformFree() function ------------------------------*//** + * @brief Function implements the memory free function for the platform + * library. + * + * This function frees up memory allocated using Osal_platformMalloc() + * function call. + * + * @param[in] mem_ptr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformFree(uint8_t *mem_ptr, uint32_t num_bytes) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ Osal_platformSpiCsEnter() function ------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @param[out] key - pointer to a variable to receive a handle for unlocking + * critical section + + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformSpiCsEnter(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ Osal_platformSpiCsExit() function -------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_paMtCsEnter() API. + * + * @param[in] key - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformSpiCsExit(void) +{ +} +//----------------------------------------------------------------------------- + + +//============================================================================= + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h new file mode 100644 index 00000000..9e252dcd --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h @@ -0,0 +1,209 @@ +/* + * board_setup.h + * + */ + + +#ifndef BOARD_SETUP_H /* check for this file has been already included */ +#define BOARD_SETUP_H 1 + + +#include "ti\platform\platform.h" + + +/*===========================================================================*/ +/*============ Printf output definitions ====================================*/ +/*===========================================================================*/ +#define printf platform_write +/*===========================================================================*/ + + +/*------------ hardware_setup() function -------------------------------------- + * DESCRIPTION: Function intializes board hardware + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +int hardware_setup(); + + +/*------------ tx_nmi_handler() function -------------------------------------- + * DESCRIPTION: Function handles NMI interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_nmi_handler(void); + + +/*------------ tx_int4_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT4 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int4_handler(void); + + +/*------------ tx_int5_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT5 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int5_handler(void); + + +/*------------ tx_int6_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT6 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int6_handler(void); + + +/*------------ tx_int7_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT7 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int7_handler(void); + + +/*------------ tx_int8_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT8 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int8_handler(void); + + +/*------------ tx_int9_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT9 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int9_handler(void); + + +/*------------ tx_int10_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT10 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int10_handler(void); + + +/*------------ tx_int11_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT11 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int11_handler(void); + + +/*------------ tx_int12_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT12 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int12_handler(void); + + +/*------------ tx_int13_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT13 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int13_handler(void); + + +/*------------ tx_int14_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT14 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int14_handler(void); + + +/*------------ tx_int15_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT15 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int15_handler(void); + + +/*------------ Osal_platformMalloc() function ----------------------------*//** + * @brief Function implements the memory allocate function for the platform + * library. + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * @param[in] alignment - alignment of allocated memory block in bytes + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +uint8_t *Osal_platformMalloc(uint32_t num_bytes, uint32_t alignment); + + +/*------------ Osal_platformFree() function ------------------------------*//** + * @brief Function implements the memory free function for the platform + * library. + * + * This function frees up memory allocated using Osal_platformMalloc() + * function call. + * + * @param[in] mem_ptr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformFree(uint8_t *mem_ptr, uint32_t num_bytes); + + +/*------------ Osal_platformSpiCsEnter() function ------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @param[out] key - pointer to a variable to receive a handle for unlocking + * critical section + + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformSpiCsEnter(void); + + +/*------------ Osal_platformSpiCsExit() function -------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_paMtCsEnter() API. + * + * @param[in] key - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformSpiCsExit(void); + + +/*===========================================================================*/ +#endif /* BOARD_SETUP_H */ + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c new file mode 100644 index 00000000..18bad8de --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c @@ -0,0 +1,528 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include "board_setup.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define TraceX trace oblects */ +#define TRACE_BUFFER_SIZE (4 * 1024) +#define TRACE_OBJECTS_COUNT 20 +/* Define TraceX trace buffer */ +UCHAR tx_trace_buffer[TRACE_BUFFER_SIZE]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define demo timer */ +#define DEMO_TIMER_PERIOD 10 +#define DEMO_TIMER_VALUE 0xaaaaaaaa +TX_TIMER timer_0; +ULONG timer_0_counter; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); +void my_stack_error_handler(TX_THREAD *thread_ptr); +void my_timer_function(ULONG timer_input); + + +/* Define main entry point. */ + +void main() +{ + /* Setup the hardware. */ + hardware_setup(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; +UINT status; + + /* Enable event tracing using the global �trace_buffer� memory and supporting + a maximum of TRACE_OBJECTS_COUNT ThreadX objects in the registry. */ + if ((status = tx_trace_enable(tx_trace_buffer, TRACE_BUFFER_SIZE, TRACE_OBJECTS_COUNT)) != TX_SUCCESS) + { + while (1); + } + + /* Register thread stack error notification callback */ + if ((status = tx_thread_stack_error_notify(my_stack_error_handler)) != TX_SUCCESS) + { + while (1); + } + + /* Create a byte memory pool from which to allocate the thread stacks. */ + status = tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the main thread. */ + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 1. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 2. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 3. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + status = tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 4. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 5. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 6. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + status = tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 7. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the message queue. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the message queue shared by threads 1 and 2. */ + status = tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the semaphore used by threads 3 and 4. */ + status = tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the event flags group used by threads 1 and 5. */ + status = tx_event_flags_create(&event_flags_0, "event flags 0"); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + status = tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the memory for a small block pool. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create a block memory pool to allocate a message buffer from. */ + status = tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate a block and release the block memory. */ + status = tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Release the block back to the pool. */ + status = tx_block_release(pointer); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the periodic timer. */ + status = tx_timer_create(&timer_0, "timer 0", my_timer_function, (ULONG) DEMO_TIMER_VALUE, DEMO_TIMER_PERIOD, DEMO_TIMER_PERIOD, TX_AUTO_ACTIVATE); + if (status != TX_SUCCESS) + { + while (1); + } +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void my_stack_error_handler(TX_THREAD *thread_ptr) +{ + while(1); +} + + +void my_timer_function(ULONG timer_input) +{ + /* Increment the thread counter. */ + timer_0_counter++; + + if (timer_input != DEMO_TIMER_VALUE) + while(1); +} + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd new file mode 100644 index 00000000..a2267231 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd @@ -0,0 +1,55 @@ +-c +-heap 0x400 +-stack 0x1000 +-l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.ae66 +-l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.intc.ae66 +-l c:\ti\pdk_C6678_1_1_2_6\packages\ti\platform\evmc6678l\platform_lib\lib\release\ti.platform.evm6678l.ae66 + +/* Memory Map */ +MEMORY +{ + L1PSRAM (RWX) : org = 0x00E00000, len = 0x00008000 + L1DSRAM (RWX) : org = 0x00F00000, len = 0x00008000 + CODE_RAM (RWX) : org = 0x00800000, len = 0x00020000 + DATA_RAM (RWX) : org = 0x00820000, len = 0x00060000 + MSMCSRAM (RWX) : org = 0x0c000000, len = 0x00400000 + DDR3 (RWX) : org = 0x80000000, len = 0x80000000 +} + +SECTIONS +{ + .text > CODE_RAM + .stack > CODE_RAM + .cio > CODE_RAM + .const > CODE_RAM + .data > CODE_RAM + .switch > CODE_RAM + .sysmem > CODE_RAM + .far > CODE_RAM + .args > CODE_RAM + .ppinfo > CODE_RAM + .ppdata > CODE_RAM + .csl_vect > CODE_RAM + platform_lib > CODE_RAM + + GROUP + { + .neardata + .rodata + .bss + } > CODE_RAM + + /* COFF sections */ + .pinit > CODE_RAM + .cinit > CODE_RAM + + /* EABI sections */ + .binit > CODE_RAM + .init_array > CODE_RAM + .fardata > CODE_RAM + .c6xabi.exidx > CODE_RAM + .c6xabi.extab > CODE_RAM + + /* ThreadX section which should be the last RAM section loaded */ + .zend > DATA_RAM +} diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml new file mode 100644 index 00000000..b7147d7f --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml @@ -0,0 +1,17 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<configurations XML_version="1.2" id="configurations_0"> + +<configuration XML_version="1.2" id="Texas Instruments XDS100v1 USB Debug Probe_0"> + <instance XML_version="1.2" desc="Texas Instruments XDS100v1 USB Debug Probe_0" href="connections/TIXDS100usb_Connection.xml" id="Texas Instruments XDS100v1 USB Debug Probe_0" xml="TIXDS100usb_Connection.xml" xmlpath="connections"/> + <connection XML_version="1.2" id="Texas Instruments XDS100v1 USB Debug Probe_0"> + <instance XML_version="1.2" href="drivers/tixds100icepick_d.xml" id="drivers" xml="tixds100icepick_d.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds100c66xx.xml" id="drivers" xml="tixds100c66xx.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds100cs_dap.xml" id="drivers" xml="tixds100cs_dap.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds100csstm.xml" id="drivers" xml="tixds100csstm.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds100etbcs.xml" id="drivers" xml="tixds100etbcs.xml" xmlpath="drivers"/> + <platform XML_version="1.2" id="platform_0"> + <instance XML_version="1.2" desc="TMS320C6678_0" href="devices/C6678.xml" id="TMS320C6678_0" xml="C6678.xml" xmlpath="devices"/> + </platform> + </connection> + </configuration> +</configurations> diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/readme.txt b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/readme.txt new file mode 100644 index 00000000..d783fef4 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page.
\ No newline at end of file diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm new file mode 100644 index 00000000..cdc14f20 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm @@ -0,0 +1,405 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + +SP .set B15 +ADDRESS_MSK .set 0xFFFFFFF0 ; Ensure 16-byte alignment + +; Use Timer 8 as it's available for all DSP cores at C6678 +; Timer 8 interrupt high event (TINT8H) ID is 67 +; Assume DSP core clock 1000 MHz +; Timer is clocked at DSP core clock / 6 = 167 MHz +; Timer frequency will set to 100 Hz +TMR8_INTCTLSTAT_ADDR .set 0x02280044 ; Timer 8 Interrupt Control and Status Register +INTCTLSTAT_VAL .set 0x00010000 ; Enable TIMHI interrupt + +EVTCLR2_ADDR .set 0x01800048 ; Event Clear register 2 address +EVTCLR2_TMR8_VAL .set 0x00000008 ; Clear event 67 - TINT8H + +EVTMASK2_ADDR .set 0x01800088 ; Event Mask register 2 address +EVTMASK2_TMR8_VAL .set 0x00000008 ; Mask event 67 - TINT8H + +INTMUX1_ADDR .set 0x01800104 ; Interrupt Mux Register 1 address +INTMUX1_TMR8_VAL .set 0x43 ; Tie in Event 67 (TINT8H) to INT4 +; +; + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + + +; External interrupt handlers - should be defined by user + .global tx_nmi_handler + .global tx_int5_handler + .global tx_int6_handler + .global tx_int7_handler + .global tx_int8_handler + .global tx_int9_handler + .global tx_int10_handler + .global tx_int11_handler + .global tx_int12_handler + .global tx_int13_handler + .global tx_int14_handler + .global tx_int15_handler + +; +; +;/* Define the first available address in memory, which is typically just the last +; RAM section loaded. */ + .sect ".zend" + .space 20 + .global _tx_first_free_memory + .align 16 +_tx_first_free_memory: + .space 4 + +; Useful macro definitions +; Load 32-bit integer into register +MVK_LH .macro val,reg + MVKL val,reg + MVKH val,reg + .endm +; Interrupt entry - allocate stack space, save A0-A4 and B3 registers to stack, +; build return address in B3 register for context save function and +; call context save function +TX_INTERRUPT_ENTRY .macro + ADDK.S2 -288,SP + STW B3,*+SP(96) + STW A0,*+SP(20) + STW A1,*+SP(24) + STW A2,*+SP(28) + STW A3,*+SP(32) + STW A4,*+SP(36) + B _tx_thread_context_save + .endm +; Interrupt exit - jump to context restore function +TX_INTERRUPT_EXIT .macro + B _tx_thread_context_restore + NOP 5 + .endm + + + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level C667x/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + .global _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (SP); +; + MVK_LH _tx_thread_system_stack_ptr,A0 ; Build address of system stack + STW SP,*A0 ; Save system stack address +; +; /* Pickup the first available memory address. */ +; + MVK_LH ADDRESS_MSK,A0 ; Build address mask + MVK_LH _tx_first_free_memory,A1 ; Build address of free memory + AND A0,A1,A1 ; Ensure alignment +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) end; +; + MVK_LH _tx_initialize_unused_memory,A0 ; Build address of variable + STW A1,*A0 ; Save free memory address +; +; /* Setup Timer 8 HIGH interrupt event */ +; + MVK_LH INTMUX1_ADDR,A0 ; Select event 67 to send through INT4 + MVK_LH INTMUX1_TMR8_VAL,A1 + STW A1,*A0 + + MVK_LH EVTMASK2_ADDR,A0 ; Build address of Event Mask 2 Register + MVK_LH EVTMASK2_TMR8_VAL,A1 ; Build value of Event Mask 2 Register + STW A1,*A0 +; +; /* Done, return to caller. */ +; + B B3 ; Return to caller + NOP 5 ; Delay slots +;} +; + + + .global _tx_nmi_vector + .global _tx_nmi_vector_processing +_tx_nmi_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_nmi_vector_processing,B3 + MVKH _tx_nmi_vector_processing,B3 + NOP 3 +_tx_nmi_vector_processing: + CALLP tx_nmi_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int4_vector +_tx_int4_vector: + ADDK.S2 -288,SP ; Allocate stack space + STW B3,*+SP(96) ; Save B3 + STW A0,*+SP(20) ; Save A0 + STW A1,*+SP(24) ; Save A1 + STW A2,*+SP(28) ; Save A2 + STW A3,*+SP(32) ; Save A3 + STW A4,*+SP(36) ; Save A4 + NOP + +;_tx_timer_interrupt_preamble: + + MVK_LH TMR8_INTCTLSTAT_ADDR,A0 ; Build address of Timer Interrupt Control Register + MVK_LH INTCTLSTAT_VAL,A1 ; Build value of Timer Interrupt Control Register + STW A1,*A0 ; Clear Timer Interrupts + +; Clear DSP Event flag - DSP events are not self-cleared + MVK_LH EVTCLR2_ADDR,A0 ; Build address of Event Clear 2 Register + MVK_LH EVTCLR2_TMR8_VAL,A1 ; Build value of Event Clear 2 Register + STW A1,*A0 ; Clear Timer Event + + MVK_LH _tx_timer_interrupt,A0 + B A0 ; Branch ThreadX timer ISR routine + NOP 5 ; Delay slots + NOP + + + + .global _tx_int5_vector + .global _tx_int5_vector_processing +_tx_int5_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int5_vector_processing,B3 + MVKH _tx_int5_vector_processing,B3 + NOP 3 +_tx_int5_vector_processing: + CALLP tx_int5_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int6_vector + .global _tx_int6_vector_processing +_tx_int6_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int6_vector_processing,B3 + MVKH _tx_int6_vector_processing,B3 + NOP 3 +_tx_int6_vector_processing: + CALLP tx_int6_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int7_vector + .global _tx_int7_vector_processing +_tx_int7_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int7_vector_processing,B3 + MVKH _tx_int7_vector_processing,B3 + NOP 3 +_tx_int7_vector_processing: + CALLP tx_int7_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int8_vector + .global _tx_int8_vector_processing +_tx_int8_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int8_vector_processing,B3 + MVKH _tx_int8_vector_processing,B3 + NOP 3 +_tx_int8_vector_processing: + CALLP tx_int8_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int9_vector + .global _tx_int9_vector_processing +_tx_int9_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int9_vector_processing,B3 + MVKH _tx_int9_vector_processing,B3 + NOP 3 +_tx_int9_vector_processing: + CALLP tx_int9_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int10_vector + .global _tx_int10_vector_processing +_tx_int10_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int10_vector_processing,B3 + MVKH _tx_int10_vector_processing,B3 + NOP 3 +_tx_int10_vector_processing: + CALLP tx_int10_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int11_vector + .global _tx_int11_vector_processing +_tx_int11_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int11_vector_processing,B3 + MVKH _tx_int11_vector_processing,B3 + NOP 3 +_tx_int11_vector_processing: + CALLP tx_int11_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int12_vector + .global _tx_int12_vector_processing +_tx_int12_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int12_vector_processing,B3 + MVKH _tx_int12_vector_processing,B3 + NOP 3 +_tx_int12_vector_processing: + CALLP tx_int12_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int13_vector + .global _tx_int13_vector_processing +_tx_int13_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int13_vector_processing,B3 + MVKH _tx_int13_vector_processing,B3 + NOP 3 +_tx_int13_vector_processing: + CALLP tx_int13_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int14_vector + .global _tx_int14_vector_processing +_tx_int14_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int14_vector_processing,B3 + MVKH _tx_int14_vector_processing,B3 + NOP 3 +_tx_int14_vector_processing: + CALLP tx_int14_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int15_vector + .global _tx_int15_vector_processing +_tx_int15_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int15_vector_processing,B3 + MVKH _tx_int15_vector_processing,B3 + NOP 3 +_tx_int15_vector_processing: + CALLP tx_int15_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.ccsproject b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.ccsproject new file mode 100644 index 00000000..d9b816a4 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.ccsproject @@ -0,0 +1,14 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<?ccsproject version="1.0"?> +<projectOptions> + <deviceVariant value="TMS320C66XX.TMS320C6678"/> + <deviceFamily value="C6000"/> + <deviceEndianness value="little"/> + <codegenToolVersion value="7.4.20"/> + <isElfFormat value="true"/> + <connection value="common/targetdb/connections/TIXDS100usb_Connection.xml"/> + <rts value="libc.a"/> + <templateProperties value="id=com.ti.common.project.core.emptyProjectWithMainTemplate,"/> + <isTargetManual value="false"/> + <origin value="C:/release/threadx/sample_threadx_ta6678fmc"/> +</projectOptions> diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.cproject b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.cproject new file mode 100644 index 00000000..ee74925b --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.cproject @@ -0,0 +1,168 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="com.ti.ccstudio.buildDefinitions.C6000.Debug.846961876"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.846961876" moduleId="org.eclipse.cdt.core.settings" name="Debug"> + <externalSettings/> + <extensions> + <extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/> + <extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + </extensions> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.846961876" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug"> + <folderInfo id="com.ti.ccstudio.buildDefinitions.C6000.Debug.846961876." name="/" resourcePath=""> + <toolChain id="com.ti.ccstudio.buildDefinitions.C6000_8.2.exe.DebugToolchain.1016787538" name="TI Build Tools" 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(--xml_link_info, -xml_link_info)" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.3.linkerID.XML_LINK_INFO" value=""${ProjName}_linkInfo.xml"" valueType="string"/> + <inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.3.exeLinker.inputType__CMD_SRCS.1613219748" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.3.exeLinker.inputType__CMD_SRCS"/> + <inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.3.exeLinker.inputType__CMD2_SRCS.1041720846" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.3.exeLinker.inputType__CMD2_SRCS"/> + <inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.3.exeLinker.inputType__GEN_CMDS.1908930597" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.3.exeLinker.inputType__GEN_CMDS"/> + </tool> + </toolChain> + </folderInfo> + <sourceEntries> + <entry excluding="sample_threadx.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> + </sourceEntries> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> + </cconfiguration> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <project id="sample_threadx.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.869979204" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType"/> + </storageModule> + <storageModule moduleId="refreshScope"/> + <storageModule moduleId="scannerConfiguration"/> + <storageModule moduleId="org.eclipse.cdt.core.language.mapping"> + <project-mappings> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/> + </project-mappings> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> +</cproject> diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.project b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.project new file mode 100644 index 00000000..cbdff31c --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.project @@ -0,0 +1,89 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>sample_threadx_ta6678fmc</name> + <comment></comment> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <arguments> + <dictionary> + <key>?name?</key> + <value></value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.append_environment</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.autoBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildArguments</key> + <value>-k</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildCommand</key> + <value>${CCS_UTILS_DIR}/bin/gmake</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildLocation</key> + <value>${BuildDirectory}</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.cleanBuildTarget</key> + <value>clean</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.contents</key> + <value>org.eclipse.cdt.make.core.activeConfigSettings</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableAutoBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableCleanBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableFullBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.fullBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.stopOnError</key> + <value>false</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key> + <value>true</value> + </dictionary> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>com.ti.ccstudio.core.ccsNature</nature> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.core.ccnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <variableList> + <variable> + <name>ORIGINAL_PROJECT_ROOT</name> + <value>file:/C:/release/threadx/sample_threadx_ta6678fmc</value> + </variable> + </variableList> +</projectDescription> diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.codan.core.prefs b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..f653028c --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.debug.core.prefs b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..2adc7b1d --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.core.resources.prefs b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..093dbb95 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,6 @@ +eclipse.preferences.version=1 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c new file mode 100644 index 00000000..e5b8a0bf --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c @@ -0,0 +1,329 @@ +/* + * board_setup.c + * + */ + + +#include "board_setup.h" +#include <string.h> + + +//============================================================================= +//============ General definitions ============================================ +//============================================================================= +// DSP Timer-8 definition +#define C66XX_DSP_TIMER C66XX_TIMER_8 +// DSP Timer-8 output frequency in Hz +#define C66XX_DSP_TIMER_FREQ 100 +/* DSP Timer-8 interrupt event ID */ +#define C66XX_DSP_TIMER_EVENT_ID 67 +//============================================================================= + + +//============================================================================= +//============ Global functions =============================================== +//============================================================================= +void _tx_nmi_vector(void); +void _tx_int4_vector(void); +void _tx_int5_vector(void); +void _tx_int6_vector(void); +void _tx_int7_vector(void); +void _tx_int8_vector(void); +void _tx_int9_vector(void); +void _tx_int10_vector(void); +void _tx_int11_vector(void); +void _tx_int12_vector(void); +void _tx_int13_vector(void); +void _tx_int14_vector(void); +void _tx_int15_vector(void); +//============================================================================= + + +//============================================================================= +//============ Static functions =============================================== +//============================================================================= +static int32_t tx_timer_init(C66XX_TIMER timer, uint32_t frequency); +static int32_t tx_interrupt_init(void); +//============================================================================= + + +/*------------ init_output_timer() function ----------------------------------- + * DESCRIPTION: Function initializes Timer64 module + * ARGUMENTS: + * None + * RETURNED VALUE: Error code +-----------------------------------------------------------------------------*/ +static int32_t tx_timer_init(C66XX_TIMER timer, uint32_t frequency) +{ + int32_t r; + C66XX_TIMER_CFG_DD cfg_dd; + + // Reset 64-bit timer + if ((r = C66XX_TIMER_reset(timer, C66XX_TIMER_HW_CFG_64BIT)) != C66XX_OK) + goto exit; + + // Fill configuration data descriptor + memset(&cfg_dd, 0, C66XX_TIMER_CFG_DD_LEN); + cfg_dd.timer_mode = C66XX_TIMER_MODE_32BIT_UNCHAINED; + cfg_dd.timer_high.clk_src_output_mode = C66XX_TIMER_CLK_OUTPUT_MODE_CLK; + // Init DSP Timer64 module + if ((r = C66XX_TIMER_init(timer, frequency, &cfg_dd)) != C66XX_OK) + goto exit; + + // Enable timer interrupt + if ((r = C66XX_TIMER_enable_interrupts(timer, C66XX_TIMER_HW_CFG_32BIT_HIGH)) != C66XX_OK) + goto exit; + + // Start 32-bit timer high to enable continuously + if ((r = C66XX_TIMER_start(timer, C66XX_TIMER_HW_CFG_32BIT_HIGH, C66XX_TIMER_COUNT_MODE_CONTINUOUSLY)) != C66XX_OK) + goto exit; + + // TIMER module configuration is completed + printf("Timer #%u configuration is completed\n", timer); + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ tx_interrupt_init() function ----------------------------------- + * DESCRIPTION: Function initializes CorePack interrupt module + * ARGUMENTS: + * None + * RETURNED VALUE: Error code +-----------------------------------------------------------------------------*/ +static int32_t tx_interrupt_init(void) +{ + int32_t r; + + // Set DSP interrupt handlers to the ones defined in tx_initialize_low_level.asm + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_NMI, _tx_nmi_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_4, _tx_int4_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_5, _tx_int5_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_6, _tx_int6_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_7, _tx_int7_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_8, _tx_int8_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_9, _tx_int9_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_10, _tx_int10_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_11, _tx_int11_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_12, _tx_int12_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_13, _tx_int13_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_14, _tx_int14_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_15, _tx_int15_vector)) != C66XX_OK) + goto exit; + + /* CorePack interrupt module configuration is completed */ + printf("INTC configuration is completed\n"); + // Exit without errors + r = TASDK_OK; + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ hardware_setup() function -------------------------------------- + * DESCRIPTION: Function intializes board hardware + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +int hardware_setup() +{ + int r; + + /* Init DSP */ + if ((r = TA66XX_BC_init()) != TASDK_OK) + goto exit; + + // Initialize UART + if ((r = TA66XX_BC_init_uart(C66XX_UART_BAUD_RATE_115200, C66XX_UART_DATA_BITS_8BITS, C66XX_UART_PARITY_NONE, C66XX_UART_STOP_BITS_1BIT)) != TASDK_OK) + goto exit; + + // Init DSP Timer + if ((r = tx_timer_init(C66XX_DSP_TIMER, C66XX_DSP_TIMER_FREQ)) != TASDK_OK) + goto exit; + + // Init DSP interrupt controller + if ((r = tx_interrupt_init()) != TASDK_OK) + goto exit; + + printf("Board is initialized\n"); + /* Exit with no errors */ + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ tx_nmi_handler() function -------------------------------------- + * DESCRIPTION: Function handles NMI interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_nmi_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int4_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT4 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int4_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int5_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT5 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int5_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int6_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT6 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int6_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int7_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT7 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int7_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int8_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT8 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int8_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int9_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT9 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int9_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int10_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT10 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int10_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int11_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT11 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int11_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int12_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT12 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int12_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int13_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT13 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int13_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int14_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT14 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int14_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int15_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT15 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int15_handler(void) +{ +} +//----------------------------------------------------------------------------- + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h new file mode 100644 index 00000000..a65e3b9d --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h @@ -0,0 +1,151 @@ +/* + * board_setup.h + * + */ + + +#ifndef BOARD_SETUP_H // check for this file has been already included +#define BOARD_SETUP_H 1 + + +/* Include T-AMC DSP API */ +#include "TA66XX_DSP_BC.h" + + +//============================================================================= +//============ Printf output definitions ====================================== +//============================================================================= +#define printf TA66XX_BC_uart_printf +//============================================================================= + + +/*------------ hardware_setup() function -------------------------------------- + * DESCRIPTION: Function intializes board hardware + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +int hardware_setup(); + + +/*------------ tx_nmi_handler() function -------------------------------------- + * DESCRIPTION: Function handles NMI interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_nmi_handler(void); + + +/*------------ tx_int4_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT4 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int4_handler(void); + + +/*------------ tx_int5_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT5 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int5_handler(void); + + +/*------------ tx_int6_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT6 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int6_handler(void); + + +/*------------ tx_int7_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT7 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int7_handler(void); + + +/*------------ tx_int8_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT8 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int8_handler(void); + + +/*------------ tx_int9_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT9 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int9_handler(void); + + +/*------------ tx_int10_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT10 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int10_handler(void); + + +/*------------ tx_int11_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT11 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int11_handler(void); + + +/*------------ tx_int12_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT12 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int12_handler(void); + + +/*------------ tx_int13_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT13 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int13_handler(void); + + +/*------------ tx_int14_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT14 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int14_handler(void); + + +/*------------ tx_int15_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT15 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int15_handler(void); + + +//============================================================================= +#endif /* BOARD_SETUP_H */ + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c new file mode 100644 index 00000000..18bad8de --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c @@ -0,0 +1,528 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include "board_setup.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define TraceX trace oblects */ +#define TRACE_BUFFER_SIZE (4 * 1024) +#define TRACE_OBJECTS_COUNT 20 +/* Define TraceX trace buffer */ +UCHAR tx_trace_buffer[TRACE_BUFFER_SIZE]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define demo timer */ +#define DEMO_TIMER_PERIOD 10 +#define DEMO_TIMER_VALUE 0xaaaaaaaa +TX_TIMER timer_0; +ULONG timer_0_counter; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); +void my_stack_error_handler(TX_THREAD *thread_ptr); +void my_timer_function(ULONG timer_input); + + +/* Define main entry point. */ + +void main() +{ + /* Setup the hardware. */ + hardware_setup(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; +UINT status; + + /* Enable event tracing using the global �trace_buffer� memory and supporting + a maximum of TRACE_OBJECTS_COUNT ThreadX objects in the registry. */ + if ((status = tx_trace_enable(tx_trace_buffer, TRACE_BUFFER_SIZE, TRACE_OBJECTS_COUNT)) != TX_SUCCESS) + { + while (1); + } + + /* Register thread stack error notification callback */ + if ((status = tx_thread_stack_error_notify(my_stack_error_handler)) != TX_SUCCESS) + { + while (1); + } + + /* Create a byte memory pool from which to allocate the thread stacks. */ + status = tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the main thread. */ + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 1. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 2. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 3. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + status = tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 4. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 5. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 6. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + status = tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 7. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the message queue. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the message queue shared by threads 1 and 2. */ + status = tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the semaphore used by threads 3 and 4. */ + status = tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the event flags group used by threads 1 and 5. */ + status = tx_event_flags_create(&event_flags_0, "event flags 0"); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + status = tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the memory for a small block pool. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create a block memory pool to allocate a message buffer from. */ + status = tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate a block and release the block memory. */ + status = tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Release the block back to the pool. */ + status = tx_block_release(pointer); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the periodic timer. */ + status = tx_timer_create(&timer_0, "timer 0", my_timer_function, (ULONG) DEMO_TIMER_VALUE, DEMO_TIMER_PERIOD, DEMO_TIMER_PERIOD, TX_AUTO_ACTIVATE); + if (status != TX_SUCCESS) + { + while (1); + } +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void my_stack_error_handler(TX_THREAD *thread_ptr) +{ + while(1); +} + + +void my_timer_function(ULONG timer_input) +{ + /* Increment the thread counter. */ + timer_0_counter++; + + if (timer_input != DEMO_TIMER_VALUE) + while(1); +} + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd new file mode 100644 index 00000000..b03e87b5 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd @@ -0,0 +1,53 @@ +-c +-heap 0x400 +-stack 0x1000 +-l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.ae66 +-l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.intc.ae66 + +/* Memory Map */ +MEMORY +{ + L1PSRAM (RWX) : org = 0x00E00000, len = 0x00008000 + L1DSRAM (RWX) : org = 0x00F00000, len = 0x00008000 + CODE_RAM (RWX) : org = 0x00800000, len = 0x00020000 + DATA_RAM (RWX) : org = 0x00820000, len = 0x00060000 + MSMCSRAM (RWX) : org = 0x0c000000, len = 0x00400000 + DDR3 (RWX) : org = 0x80000000, len = 0x80000000 +} + +SECTIONS +{ + .text > CODE_RAM + .stack > CODE_RAM + .cio > CODE_RAM + .const > CODE_RAM + .data > CODE_RAM + .switch > CODE_RAM + .sysmem > CODE_RAM + .far > CODE_RAM + .args > CODE_RAM + .ppinfo > CODE_RAM + .ppdata > CODE_RAM + .csl_vect > CODE_RAM + + GROUP + { + .neardata + .rodata + .bss + } > CODE_RAM + + /* COFF sections */ + .pinit > CODE_RAM + .cinit > CODE_RAM + + /* EABI sections */ + .binit > CODE_RAM + .init_array > CODE_RAM + .fardata > CODE_RAM + .c6xabi.exidx > CODE_RAM + .c6xabi.extab > CODE_RAM + + /* ThreadX section which should be the last RAM section loaded */ + .zend > DATA_RAM +} diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml new file mode 100644 index 00000000..b7147d7f --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml @@ -0,0 +1,17 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<configurations XML_version="1.2" id="configurations_0"> + +<configuration XML_version="1.2" id="Texas Instruments XDS100v1 USB Debug Probe_0"> + <instance XML_version="1.2" desc="Texas Instruments XDS100v1 USB Debug Probe_0" href="connections/TIXDS100usb_Connection.xml" id="Texas Instruments XDS100v1 USB Debug Probe_0" xml="TIXDS100usb_Connection.xml" xmlpath="connections"/> + <connection XML_version="1.2" id="Texas Instruments XDS100v1 USB Debug Probe_0"> + <instance XML_version="1.2" href="drivers/tixds100icepick_d.xml" id="drivers" xml="tixds100icepick_d.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds100c66xx.xml" id="drivers" xml="tixds100c66xx.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds100cs_dap.xml" id="drivers" xml="tixds100cs_dap.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds100csstm.xml" id="drivers" xml="tixds100csstm.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds100etbcs.xml" id="drivers" xml="tixds100etbcs.xml" xmlpath="drivers"/> + <platform XML_version="1.2" id="platform_0"> + <instance XML_version="1.2" desc="TMS320C6678_0" href="devices/C6678.xml" id="TMS320C6678_0" xml="C6678.xml" xmlpath="devices"/> + </platform> + </connection> + </configuration> +</configurations> diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/readme.txt b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/readme.txt new file mode 100644 index 00000000..d783fef4 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page.
\ No newline at end of file diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm new file mode 100644 index 00000000..de902350 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm @@ -0,0 +1,406 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + +SP .set B15 +ADDRESS_MSK .set 0xFFFFFFF0 ; Ensure 16-byte alignment + +; Use Timer 8 as it's available for all DSP cores at C6678 +; Timer 8 interrupt high event (TINT8H) ID is 67 +; Assume DSP core clock 1250 MHz +; Timer is clocked at DSP core clock / 6 = 208 MHz +; Timer frequency will set to 100 Hz +TMR8_INTCTLSTAT_ADDR .set 0x02280044 ; Timer 8 Interrupt Control and Status Register +INTCTLSTAT_VAL .set 0x00010000 ; Enable TIMHI interrupt + +EVTCLR2_ADDR .set 0x01800048 ; Event Clear register 2 address +EVTCLR2_TMR8_VAL .set 0x00000008 ; Clear event 67 - TINT8H + +EVTMASK2_ADDR .set 0x01800088 ; Event Mask register 2 address +EVTMASK2_TMR8_VAL .set 0x00000008 ; Mask event 67 - TINT8H + +INTMUX1_ADDR .set 0x01800104 ; Interrupt Mux Register 1 address +INTMUX1_TMR8_VAL .set 0x43 ; Tie in Event 67 (TINT8H) to INT4 +; +; + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + + +; External interrupt handlers - should be defined by user + .global tx_nmi_handler + .global tx_int5_handler + .global tx_int6_handler + .global tx_int7_handler + .global tx_int8_handler + .global tx_int9_handler + .global tx_int10_handler + .global tx_int11_handler + .global tx_int12_handler + .global tx_int13_handler + .global tx_int14_handler + .global tx_int15_handler + +; +; +;/* Define the first available address in memory, which is typically just the last +; RAM section loaded. */ + .sect ".zend" + .space 20 + .global _tx_first_free_memory + .align 16 +_tx_first_free_memory: + .space 4 + +; Useful macro definitions +; Load 32-bit integer into register +MVK_LH .macro val,reg + MVKL val,reg + MVKH val,reg + .endm +; Interrupt entry - allocate stack space, save A0-A4 and B3 registers to stack, +; build return address in B3 register for context save function and +; call context save function +TX_INTERRUPT_ENTRY .macro + ADDK.S2 -288,SP + STW B3,*+SP(96) + STW A0,*+SP(20) + STW A1,*+SP(24) + STW A2,*+SP(28) + STW A3,*+SP(32) + STW A4,*+SP(36) + B _tx_thread_context_save + .endm +; Interrupt exit - jump to context restore function +TX_INTERRUPT_EXIT .macro + B _tx_thread_context_restore + NOP 5 + .endm + + + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level C667x+/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + .global _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (SP); +; + MVK_LH _tx_thread_system_stack_ptr,A0 ; Build address of system stack + STW SP,*A0 ; Save system stack address +; +; /* Pickup the first available memory address. */ +; + MVK_LH ADDRESS_MSK,A0 ; Build address mask + MVK_LH _tx_first_free_memory,A1 ; Build address of free memory + AND A0,A1,A1 ; Ensure alignment +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) end; +; + MVK_LH _tx_initialize_unused_memory,A0 ; Build address of variable + STW A1,*A0 ; Save free memory address +; +; /* Setup Timer 8 HIGH interrupt event */ +; + MVK_LH INTMUX1_ADDR,A0 ; Select event 67 to send through INT4 + MVK_LH INTMUX1_TMR8_VAL,A1 + STW A1,*A0 + + MVK_LH EVTMASK2_ADDR,A0 ; Build address of Event Mask 2 Register + MVK_LH EVTMASK2_TMR8_VAL,A1 ; Build value of Event Mask 2 Register + STW A1,*A0 +; +; /* Done, return to caller. */ +; + B B3 ; Return to caller + NOP 5 ; Delay slots +;} +; + + + .global _tx_nmi_vector + .global _tx_nmi_vector_processing +_tx_nmi_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_nmi_vector_processing,B3 + MVKH _tx_nmi_vector_processing,B3 + NOP 3 +_tx_nmi_vector_processing: + CALLP tx_nmi_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int4_vector +_tx_int4_vector: + ADDK.S2 -288,SP ; Allocate stack space + STW B3,*+SP(96) ; Save B3 + STW A0,*+SP(20) ; Save A0 + STW A1,*+SP(24) ; Save A1 + STW A2,*+SP(28) ; Save A2 + STW A3,*+SP(32) ; Save A3 + STW A4,*+SP(36) ; Save A4 + NOP + +;_tx_timer_interrupt_preamble: + + MVK_LH TMR8_INTCTLSTAT_ADDR,A0 ; Build address of Timer Interrupt Control Register + MVK_LH INTCTLSTAT_VAL,A1 ; Build value of Timer Interrupt Control Register + STW A1,*A0 ; Clear Timer Interrupts + +; Clear DSP Event flag - DSP events are not self-cleared + MVK_LH EVTCLR2_ADDR,A0 ; Build address of Event Clear 2 Register + MVK_LH EVTCLR2_TMR8_VAL,A1 ; Build value of Event Clear 2 Register + STW A1,*A0 ; Clear Timer Event + + + MVK_LH _tx_timer_interrupt,A0 + B A0 ; Branch ThreadX timer ISR routine + NOP 5 ; Delay slots + NOP + + + + .global _tx_int5_vector + .global _tx_int5_vector_processing +_tx_int5_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int5_vector_processing,B3 + MVKH _tx_int5_vector_processing,B3 + NOP 3 +_tx_int5_vector_processing: + CALLP tx_int5_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int6_vector + .global _tx_int6_vector_processing +_tx_int6_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int6_vector_processing,B3 + MVKH _tx_int6_vector_processing,B3 + NOP 3 +_tx_int6_vector_processing: + CALLP tx_int6_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int7_vector + .global _tx_int7_vector_processing +_tx_int7_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int7_vector_processing,B3 + MVKH _tx_int7_vector_processing,B3 + NOP 3 +_tx_int7_vector_processing: + CALLP tx_int7_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int8_vector + .global _tx_int8_vector_processing +_tx_int8_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int8_vector_processing,B3 + MVKH _tx_int8_vector_processing,B3 + NOP 3 +_tx_int8_vector_processing: + CALLP tx_int8_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int9_vector + .global _tx_int9_vector_processing +_tx_int9_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int9_vector_processing,B3 + MVKH _tx_int9_vector_processing,B3 + NOP 3 +_tx_int9_vector_processing: + CALLP tx_int9_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int10_vector + .global _tx_int10_vector_processing +_tx_int10_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int10_vector_processing,B3 + MVKH _tx_int10_vector_processing,B3 + NOP 3 +_tx_int10_vector_processing: + CALLP tx_int10_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int11_vector + .global _tx_int11_vector_processing +_tx_int11_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int11_vector_processing,B3 + MVKH _tx_int11_vector_processing,B3 + NOP 3 +_tx_int11_vector_processing: + CALLP tx_int11_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int12_vector + .global _tx_int12_vector_processing +_tx_int12_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int12_vector_processing,B3 + MVKH _tx_int12_vector_processing,B3 + NOP 3 +_tx_int12_vector_processing: + CALLP tx_int12_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int13_vector + .global _tx_int13_vector_processing +_tx_int13_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int13_vector_processing,B3 + MVKH _tx_int13_vector_processing,B3 + NOP 3 +_tx_int13_vector_processing: + CALLP tx_int13_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int14_vector + .global _tx_int14_vector_processing +_tx_int14_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int14_vector_processing,B3 + MVKH _tx_int14_vector_processing,B3 + NOP 3 +_tx_int14_vector_processing: + CALLP tx_int14_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int15_vector + .global _tx_int15_vector_processing +_tx_int15_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int15_vector_processing,B3 + MVKH _tx_int15_vector_processing,B3 + NOP 3 +_tx_int15_vector_processing: + CALLP tx_int15_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + diff --git a/ports/c667x/ccs/example_build/tx/.ccsproject b/ports/c667x/ccs/example_build/tx/.ccsproject new file mode 100644 index 00000000..bed925d4 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.ccsproject @@ -0,0 +1,12 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<?ccsproject version="1.0"?> +<projectOptions> + <deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC62xxDevice"/> + <deviceFamily value="C6000"/> + <deviceEndianness value="little"/> + <codegenToolVersion value="7.3.4"/> + <isElfFormat value="false"/> + <connection value=""/> + <templateProperties value="id=com.ti.common.project.core.emptyProjectTemplate,"/> + <isTargetManual value="false"/> +</projectOptions> diff --git a/ports/c667x/ccs/example_build/tx/.cproject b/ports/c667x/ccs/example_build/tx/.cproject new file mode 100644 index 00000000..6fb6150d --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.cproject @@ -0,0 +1,126 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="com.ti.ccstudio.buildDefinitions.C6000.Debug.832256006"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.832256006" moduleId="org.eclipse.cdt.core.settings" name="Debug"> + <externalSettings/> + <extensions> + <extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/> + <extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + </extensions> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <configuration artifactExtension="lib" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.832256006" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug"> + <folderInfo id="com.ti.ccstudio.buildDefinitions.C6000.Debug.832256006." name="/" resourcePath=""> + <toolChain id="com.ti.ccstudio.buildDefinitions.C6000_8.2.libraryDebugToolchain.1327787266" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_8.2.libraryDebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_8.2.library.librarianDebug.1999522240"> + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.595213316" 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</tool> + <tool id="com.ti.ccstudio.buildDefinitions.C6000_8.2.library.librarianRelease.1477572467" name="C6000 Archiver" superClass="com.ti.ccstudio.buildDefinitions.C6000_8.2.library.librarianRelease"> + <option id="com.ti.ccstudio.buildDefinitions.C6000_8.2.archiverID.OUTPUT_FILE.256691019" superClass="com.ti.ccstudio.buildDefinitions.C6000_8.2.archiverID.OUTPUT_FILE" value="${ProjName}.lib" valueType="string"/> + </tool> + </toolChain> + </folderInfo> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> + </cconfiguration> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <project id="tx.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.1433968872" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType"/> + </storageModule> + <storageModule moduleId="scannerConfiguration"/> + <storageModule moduleId="org.eclipse.cdt.core.language.mapping"> + <project-mappings> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/> + <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/> + </project-mappings> + </storageModule> + <storageModule moduleId="refreshScope"/> + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> +</cproject> diff --git a/ports/c667x/ccs/example_build/tx/.project b/ports/c667x/ccs/example_build/tx/.project new file mode 100644 index 00000000..23e7d5ff --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.project @@ -0,0 +1,105 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>tx</name> + <comment></comment> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <arguments> + <dictionary> + <key>?name?</key> + <value></value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.append_environment</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.autoBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildArguments</key> + <value>-k</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildCommand</key> + <value>${CCS_UTILS_DIR}/bin/gmake</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildLocation</key> + <value>${BuildDirectory}</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.cleanBuildTarget</key> + <value>clean</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.contents</key> + <value>org.eclipse.cdt.make.core.activeConfigSettings</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableAutoBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableCleanBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableFullBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.fullBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.stopOnError</key> + <value>false</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key> + <value>true</value> + </dictionary> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>com.ti.ccstudio.core.ccsNature</nature> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.core.ccnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <linkedResources> + <link> + <name>inc_generic</name> + <type>2</type> + <locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/inc</locationURI> + </link> + <link> + <name>inc_port</name> + <type>2</type> + <locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI> + </link> + <link> + <name>src_generic</name> + <type>2</type> + <locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/src</locationURI> + </link> + <link> + <name>src_port</name> + <type>2</type> + <locationURI>$%7BPARENT-2-PROJECT_LOC%7D/src</locationURI> + </link> + </linkedResources> +</projectDescription> diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.codan.core.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..f653028c --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.core.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000..d9be20e1 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.832256006/append=true +environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.832256006/appendContributed=true +environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.758214915/append=true +environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.758214915/appendContributed=true diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.debug.core.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..2adc7b1d --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 00000000..71fde590 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,6 @@ +#Fri Aug 03 15:02:35 PDT 2012 +com.ti.ccstudio.buildDefinitions.C6000.Debug.2070078368/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Debug.2070078368/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Release.664540310/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Release.664540310/internalBuilder/ignoreErr=true +eclipse.preferences.version=1 diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.core.resources.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..094412e7 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,15 @@ +eclipse.preferences.version=1 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/src_generic/subdir_rules.mk=UTF-8 +encoding//Debug/src_generic/subdir_vars.mk=UTF-8 +encoding//Debug/src_port/subdir_rules.mk=UTF-8 +encoding//Debug/src_port/subdir_vars.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 +encoding//Release/makefile=UTF-8 +encoding//Release/objects.mk=UTF-8 +encoding//Release/sources.mk=UTF-8 +encoding//Release/subdir_rules.mk=UTF-8 +encoding//Release/subdir_vars.mk=UTF-8 diff --git a/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt b/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt new file mode 100644 index 00000000..e954d96e --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt @@ -0,0 +1 @@ +"./tx_block_allocate.obj" "./tx_block_pool_cleanup.obj" "./tx_block_pool_create.obj" "./tx_block_pool_delete.obj" "./tx_block_pool_info_get.obj" "./tx_block_pool_initialize.obj" "./tx_block_pool_performance_info_get.obj" "./tx_block_pool_performance_system_info_get.obj" "./tx_block_pool_prioritize.obj" "./tx_block_release.obj" "./tx_byte_allocate.obj" "./tx_byte_pool_cleanup.obj" "./tx_byte_pool_create.obj" "./tx_byte_pool_delete.obj" "./tx_byte_pool_info_get.obj" "./tx_byte_pool_initialize.obj" "./tx_byte_pool_performance_info_get.obj" "./tx_byte_pool_performance_system_info_get.obj" "./tx_byte_pool_prioritize.obj" "./tx_byte_pool_search.obj" "./tx_byte_release.obj" "./tx_event_flags_cleanup.obj" "./tx_event_flags_create.obj" "./tx_event_flags_delete.obj" "./tx_event_flags_get.obj" "./tx_event_flags_info_get.obj" "./tx_event_flags_initialize.obj" "./tx_event_flags_performance_info_get.obj" "./tx_event_flags_performance_system_info_get.obj" "./tx_event_flags_set.obj" "./tx_event_flags_set_notify.obj" "./tx_initialize_high_level.obj" "./tx_initialize_kernel_enter.obj" "./tx_initialize_kernel_setup.obj" "./tx_mutex_cleanup.obj" "./tx_mutex_create.obj" "./tx_mutex_delete.obj" "./tx_mutex_get.obj" "./tx_mutex_info_get.obj" "./tx_mutex_initialize.obj" "./tx_mutex_performance_info_get.obj" "./tx_mutex_performance_system_info_get.obj" "./tx_mutex_prioritize.obj" "./tx_mutex_priority_change.obj" "./tx_mutex_put.obj" "./tx_queue_cleanup.obj" "./tx_queue_create.obj" "./tx_queue_delete.obj" "./tx_queue_flush.obj" "./tx_queue_front_send.obj" "./tx_queue_info_get.obj" "./tx_queue_initialize.obj" "./tx_queue_performance_info_get.obj" "./tx_queue_performance_system_info_get.obj" "./tx_queue_prioritize.obj" "./tx_queue_receive.obj" "./tx_queue_send.obj" "./tx_queue_send_notify.obj" "./tx_semaphore_ceiling_put.obj" "./tx_semaphore_cleanup.obj" "./tx_semaphore_create.obj" "./tx_semaphore_delete.obj" "./tx_semaphore_get.obj" "./tx_semaphore_info_get.obj" "./tx_semaphore_initialize.obj" "./tx_semaphore_performance_info_get.obj" "./tx_semaphore_performance_system_info_get.obj" "./tx_semaphore_prioritize.obj" "./tx_semaphore_put.obj" "./tx_semaphore_put_notify.obj" "./tx_thread_context_restore.obj" "./tx_thread_context_save.obj" "./tx_thread_create.obj" "./tx_thread_delete.obj" "./tx_thread_entry_exit_notify.obj" "./tx_thread_identify.obj" "./tx_thread_info_get.obj" "./tx_thread_initialize.obj" "./tx_thread_interrupt_control.obj" "./tx_thread_performance_info_get.obj" "./tx_thread_performance_system_info_get.obj" "./tx_thread_preemption_change.obj" "./tx_thread_priority_change.obj" "./tx_thread_relinquish.obj" "./tx_thread_reset.obj" "./tx_thread_resume.obj" "./tx_thread_schedule.obj" "./tx_thread_shell_entry.obj" "./tx_thread_sleep.obj" "./tx_thread_stack_analyze.obj" "./tx_thread_stack_build.obj" "./tx_thread_stack_error_handler.obj" "./tx_thread_stack_error_notify.obj" "./tx_thread_suspend.obj" "./tx_thread_system_preempt_check.obj" "./tx_thread_system_resume.obj" "./tx_thread_system_return.obj" "./tx_thread_system_suspend.obj" "./tx_thread_terminate.obj" "./tx_thread_time_slice.obj" "./tx_thread_time_slice_change.obj" "./tx_thread_timeout.obj" "./tx_thread_wait_abort.obj" "./tx_time_get.obj" "./tx_time_set.obj" "./tx_timer_activate.obj" "./tx_timer_change.obj" "./tx_timer_create.obj" "./tx_timer_deactivate.obj" "./tx_timer_delete.obj" "./tx_timer_expiration_process.obj" "./tx_timer_info_get.obj" "./tx_timer_initialize.obj" "./tx_timer_interrupt.obj" "./tx_timer_performance_info_get.obj" "./tx_timer_performance_system_info_get.obj" "./tx_timer_system_activate.obj" "./tx_timer_system_deactivate.obj" "./tx_timer_thread_entry.obj" "./tx_trace_buffer_full_notify.obj" "./tx_trace_disable.obj" "./tx_trace_enable.obj" "./tx_trace_event_filter.obj" "./tx_trace_event_unfilter.obj" "./tx_trace_initialize.obj" "./tx_trace_interrupt_control.obj" "./tx_trace_isr_enter_insert.obj" "./tx_trace_isr_exit_insert.obj" "./tx_trace_object_register.obj" "./tx_trace_object_unregister.obj" "./tx_trace_user_event_insert.obj" "./txe_block_allocate.obj" "./txe_block_pool_create.obj" "./txe_block_pool_delete.obj" "./txe_block_pool_info_get.obj" "./txe_block_pool_prioritize.obj" "./txe_block_release.obj" "./txe_byte_allocate.obj" "./txe_byte_pool_create.obj" "./txe_byte_pool_delete.obj" "./txe_byte_pool_info_get.obj" "./txe_byte_pool_prioritize.obj" "./txe_byte_release.obj" "./txe_event_flags_create.obj" "./txe_event_flags_delete.obj" "./txe_event_flags_get.obj" "./txe_event_flags_info_get.obj" "./txe_event_flags_set.obj" "./txe_event_flags_set_notify.obj" "./txe_mutex_create.obj" "./txe_mutex_delete.obj" "./txe_mutex_get.obj" "./txe_mutex_info_get.obj" "./txe_mutex_prioritize.obj" "./txe_mutex_put.obj" "./txe_queue_create.obj" "./txe_queue_delete.obj" "./txe_queue_flush.obj" "./txe_queue_front_send.obj" "./txe_queue_info_get.obj" "./txe_queue_prioritize.obj" "./txe_queue_receive.obj" "./txe_queue_send.obj" "./txe_queue_send_notify.obj" "./txe_semaphore_ceiling_put.obj" "./txe_semaphore_create.obj" "./txe_semaphore_delete.obj" "./txe_semaphore_get.obj" "./txe_semaphore_info_get.obj" "./txe_semaphore_prioritize.obj" "./txe_semaphore_put.obj" "./txe_semaphore_put_notify.obj" "./txe_thread_create.obj" "./txe_thread_delete.obj" "./txe_thread_entry_exit_notify.obj" "./txe_thread_info_get.obj" "./txe_thread_preemption_change.obj" "./txe_thread_priority_change.obj" "./txe_thread_relinquish.obj" "./txe_thread_reset.obj" "./txe_thread_resume.obj" "./txe_thread_suspend.obj" "./txe_thread_terminate.obj" "./txe_thread_time_slice_change.obj" "./txe_thread_wait_abort.obj" "./txe_timer_activate.obj" "./txe_timer_change.obj" "./txe_timer_create.obj" "./txe_timer_deactivate.obj" "./txe_timer_delete.obj" "./txe_timer_info_get.obj"
\ No newline at end of file diff --git a/ports/c667x/ccs/example_build/tx/Release/objects.mk b/ports/c667x/ccs/example_build/tx/Release/objects.mk new file mode 100644 index 00000000..742c2da0 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/ports/c667x/ccs/example_build/tx/Release/sources.mk b/ports/c667x/ccs/example_build/tx/Release/sources.mk new file mode 100644 index 00000000..9cbc2a26 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/sources.mk @@ -0,0 +1,110 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +LIB_OUTPUTS := +CC_DEPS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +LIB_OUTPUTS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/ports/c667x/ccs/example_build/tx/Release/subdir_rules.mk b/ports/c667x/ccs/example_build/tx/Release/subdir_rules.mk new file mode 100644 index 00000000..6ceea2dd --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/subdir_rules.mk @@ -0,0 +1,22 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: C6000 Compiler' + "C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4/bin/cl6x" -mv6600 --abi=eabi -O2 --include_path="C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4/include" --display_error_number --diag_warning=225 --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<" + @echo 'Finished building: "$<"' + @echo ' ' + +%.obj: ../%.asm $(GEN_OPTS) | $(GEN_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: C6000 Compiler' + "C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4/bin/cl6x" -mv6600 --abi=eabi -O2 --include_path="C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4/include" --display_error_number --diag_warning=225 --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<" + @echo 'Finished building: "$<"' + @echo ' ' + + diff --git a/ports/c667x/ccs/example_build/tx/Release/subdir_vars.mk b/ports/c667x/ccs/example_build/tx/Release/subdir_vars.mk new file mode 100644 index 00000000..6a6a3ffd --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/subdir_vars.mk @@ -0,0 +1,1174 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Add inputs and outputs from these tool invocations to the build variables +ASM_SRCS += \ +../tx_thread_context_restore.asm \ +../tx_thread_context_save.asm \ +../tx_thread_interrupt_control.asm \ +../tx_thread_schedule.asm \ +../tx_thread_stack_build.asm \ +../tx_thread_system_return.asm \ +../tx_timer_interrupt.asm + +C_SRCS += \ +../tx_block_allocate.c \ +../tx_block_pool_cleanup.c \ +../tx_block_pool_create.c \ +../tx_block_pool_delete.c \ +../tx_block_pool_info_get.c \ +../tx_block_pool_initialize.c \ +../tx_block_pool_performance_info_get.c \ +../tx_block_pool_performance_system_info_get.c \ +../tx_block_pool_prioritize.c \ +../tx_block_release.c \ +../tx_byte_allocate.c \ +../tx_byte_pool_cleanup.c \ +../tx_byte_pool_create.c \ +../tx_byte_pool_delete.c \ +../tx_byte_pool_info_get.c \ +../tx_byte_pool_initialize.c \ +../tx_byte_pool_performance_info_get.c \ +../tx_byte_pool_performance_system_info_get.c \ +../tx_byte_pool_prioritize.c \ +../tx_byte_pool_search.c \ +../tx_byte_release.c \ +../tx_event_flags_cleanup.c \ +../tx_event_flags_create.c \ +../tx_event_flags_delete.c \ +../tx_event_flags_get.c \ +../tx_event_flags_info_get.c \ +../tx_event_flags_initialize.c \ +../tx_event_flags_performance_info_get.c \ +../tx_event_flags_performance_system_info_get.c \ +../tx_event_flags_set.c \ +../tx_event_flags_set_notify.c \ +../tx_initialize_high_level.c \ +../tx_initialize_kernel_enter.c \ +../tx_initialize_kernel_setup.c \ +../tx_mutex_cleanup.c \ +../tx_mutex_create.c \ +../tx_mutex_delete.c \ +../tx_mutex_get.c \ +../tx_mutex_info_get.c \ +../tx_mutex_initialize.c \ +../tx_mutex_performance_info_get.c \ +../tx_mutex_performance_system_info_get.c \ +../tx_mutex_prioritize.c \ +../tx_mutex_priority_change.c \ +../tx_mutex_put.c \ +../tx_queue_cleanup.c \ +../tx_queue_create.c \ +../tx_queue_delete.c \ +../tx_queue_flush.c \ +../tx_queue_front_send.c \ +../tx_queue_info_get.c \ +../tx_queue_initialize.c \ +../tx_queue_performance_info_get.c \ +../tx_queue_performance_system_info_get.c \ +../tx_queue_prioritize.c \ +../tx_queue_receive.c \ +../tx_queue_send.c \ +../tx_queue_send_notify.c \ +../tx_semaphore_ceiling_put.c \ +../tx_semaphore_cleanup.c \ +../tx_semaphore_create.c \ +../tx_semaphore_delete.c \ +../tx_semaphore_get.c \ +../tx_semaphore_info_get.c \ +../tx_semaphore_initialize.c \ +../tx_semaphore_performance_info_get.c \ +../tx_semaphore_performance_system_info_get.c \ +../tx_semaphore_prioritize.c \ +../tx_semaphore_put.c \ +../tx_semaphore_put_notify.c \ +../tx_thread_create.c \ +../tx_thread_delete.c \ +../tx_thread_entry_exit_notify.c \ +../tx_thread_identify.c \ +../tx_thread_info_get.c \ +../tx_thread_initialize.c \ +../tx_thread_performance_info_get.c \ +../tx_thread_performance_system_info_get.c \ +../tx_thread_preemption_change.c \ +../tx_thread_priority_change.c \ +../tx_thread_relinquish.c \ +../tx_thread_reset.c \ +../tx_thread_resume.c \ +../tx_thread_shell_entry.c \ +../tx_thread_sleep.c \ +../tx_thread_stack_analyze.c \ +../tx_thread_stack_error_handler.c \ +../tx_thread_stack_error_notify.c \ +../tx_thread_suspend.c \ +../tx_thread_system_preempt_check.c \ +../tx_thread_system_resume.c \ +../tx_thread_system_suspend.c \ +../tx_thread_terminate.c \ +../tx_thread_time_slice.c \ +../tx_thread_time_slice_change.c \ +../tx_thread_timeout.c \ +../tx_thread_wait_abort.c \ +../tx_time_get.c \ +../tx_time_set.c \ +../tx_timer_activate.c \ +../tx_timer_change.c \ +../tx_timer_create.c \ +../tx_timer_deactivate.c \ +../tx_timer_delete.c \ +../tx_timer_expiration_process.c \ +../tx_timer_info_get.c \ +../tx_timer_initialize.c \ +../tx_timer_performance_info_get.c \ +../tx_timer_performance_system_info_get.c \ +../tx_timer_system_activate.c \ +../tx_timer_system_deactivate.c \ +../tx_timer_thread_entry.c \ +../tx_trace_buffer_full_notify.c \ +../tx_trace_disable.c \ +../tx_trace_enable.c \ +../tx_trace_event_filter.c \ +../tx_trace_event_unfilter.c \ +../tx_trace_initialize.c \ +../tx_trace_interrupt_control.c \ +../tx_trace_isr_enter_insert.c \ +../tx_trace_isr_exit_insert.c \ +../tx_trace_object_register.c \ +../tx_trace_object_unregister.c \ +../tx_trace_user_event_insert.c \ +../txe_block_allocate.c \ +../txe_block_pool_create.c \ +../txe_block_pool_delete.c \ +../txe_block_pool_info_get.c \ +../txe_block_pool_prioritize.c \ +../txe_block_release.c \ +../txe_byte_allocate.c \ +../txe_byte_pool_create.c \ +../txe_byte_pool_delete.c \ +../txe_byte_pool_info_get.c \ +../txe_byte_pool_prioritize.c \ +../txe_byte_release.c \ +../txe_event_flags_create.c \ +../txe_event_flags_delete.c \ +../txe_event_flags_get.c \ +../txe_event_flags_info_get.c \ +../txe_event_flags_set.c \ +../txe_event_flags_set_notify.c \ +../txe_mutex_create.c \ +../txe_mutex_delete.c \ +../txe_mutex_get.c \ +../txe_mutex_info_get.c \ +../txe_mutex_prioritize.c \ +../txe_mutex_put.c \ +../txe_queue_create.c \ +../txe_queue_delete.c \ +../txe_queue_flush.c \ +../txe_queue_front_send.c \ +../txe_queue_info_get.c \ +../txe_queue_prioritize.c \ +../txe_queue_receive.c \ +../txe_queue_send.c \ +../txe_queue_send_notify.c \ +../txe_semaphore_ceiling_put.c \ +../txe_semaphore_create.c \ +../txe_semaphore_delete.c \ +../txe_semaphore_get.c \ +../txe_semaphore_info_get.c \ +../txe_semaphore_prioritize.c \ +../txe_semaphore_put.c \ +../txe_semaphore_put_notify.c \ +../txe_thread_create.c \ +../txe_thread_delete.c \ +../txe_thread_entry_exit_notify.c \ +../txe_thread_info_get.c \ +../txe_thread_preemption_change.c \ +../txe_thread_priority_change.c \ +../txe_thread_relinquish.c \ +../txe_thread_reset.c \ +../txe_thread_resume.c \ +../txe_thread_suspend.c \ +../txe_thread_terminate.c \ +../txe_thread_time_slice_change.c \ +../txe_thread_wait_abort.c \ +../txe_timer_activate.c \ +../txe_timer_change.c \ +../txe_timer_create.c \ +../txe_timer_deactivate.c \ +../txe_timer_delete.c \ +../txe_timer_info_get.c + +C_DEPS += \ +./tx_block_allocate.d \ +./tx_block_pool_cleanup.d \ +./tx_block_pool_create.d \ +./tx_block_pool_delete.d \ +./tx_block_pool_info_get.d \ +./tx_block_pool_initialize.d \ +./tx_block_pool_performance_info_get.d \ +./tx_block_pool_performance_system_info_get.d \ +./tx_block_pool_prioritize.d \ +./tx_block_release.d \ +./tx_byte_allocate.d \ +./tx_byte_pool_cleanup.d \ +./tx_byte_pool_create.d \ +./tx_byte_pool_delete.d \ +./tx_byte_pool_info_get.d \ +./tx_byte_pool_initialize.d \ +./tx_byte_pool_performance_info_get.d \ +./tx_byte_pool_performance_system_info_get.d \ +./tx_byte_pool_prioritize.d \ +./tx_byte_pool_search.d \ +./tx_byte_release.d \ +./tx_event_flags_cleanup.d \ +./tx_event_flags_create.d \ +./tx_event_flags_delete.d \ +./tx_event_flags_get.d \ +./tx_event_flags_info_get.d \ +./tx_event_flags_initialize.d \ +./tx_event_flags_performance_info_get.d \ +./tx_event_flags_performance_system_info_get.d \ +./tx_event_flags_set.d \ +./tx_event_flags_set_notify.d \ +./tx_initialize_high_level.d \ +./tx_initialize_kernel_enter.d \ +./tx_initialize_kernel_setup.d \ +./tx_mutex_cleanup.d \ +./tx_mutex_create.d \ +./tx_mutex_delete.d \ +./tx_mutex_get.d \ +./tx_mutex_info_get.d \ +./tx_mutex_initialize.d \ +./tx_mutex_performance_info_get.d \ +./tx_mutex_performance_system_info_get.d \ +./tx_mutex_prioritize.d \ +./tx_mutex_priority_change.d \ +./tx_mutex_put.d \ +./tx_queue_cleanup.d \ +./tx_queue_create.d \ +./tx_queue_delete.d \ +./tx_queue_flush.d \ +./tx_queue_front_send.d \ +./tx_queue_info_get.d \ +./tx_queue_initialize.d \ +./tx_queue_performance_info_get.d \ +./tx_queue_performance_system_info_get.d \ +./tx_queue_prioritize.d \ +./tx_queue_receive.d \ +./tx_queue_send.d \ +./tx_queue_send_notify.d \ +./tx_semaphore_ceiling_put.d \ +./tx_semaphore_cleanup.d \ +./tx_semaphore_create.d \ +./tx_semaphore_delete.d \ +./tx_semaphore_get.d \ +./tx_semaphore_info_get.d \ +./tx_semaphore_initialize.d \ +./tx_semaphore_performance_info_get.d \ +./tx_semaphore_performance_system_info_get.d \ +./tx_semaphore_prioritize.d \ +./tx_semaphore_put.d \ +./tx_semaphore_put_notify.d \ +./tx_thread_create.d \ +./tx_thread_delete.d \ +./tx_thread_entry_exit_notify.d \ +./tx_thread_identify.d \ +./tx_thread_info_get.d \ +./tx_thread_initialize.d \ +./tx_thread_performance_info_get.d \ +./tx_thread_performance_system_info_get.d \ +./tx_thread_preemption_change.d \ +./tx_thread_priority_change.d \ +./tx_thread_relinquish.d \ +./tx_thread_reset.d \ +./tx_thread_resume.d \ +./tx_thread_shell_entry.d \ +./tx_thread_sleep.d \ +./tx_thread_stack_analyze.d \ +./tx_thread_stack_error_handler.d \ +./tx_thread_stack_error_notify.d \ +./tx_thread_suspend.d \ +./tx_thread_system_preempt_check.d \ +./tx_thread_system_resume.d \ +./tx_thread_system_suspend.d \ +./tx_thread_terminate.d \ +./tx_thread_time_slice.d \ +./tx_thread_time_slice_change.d \ +./tx_thread_timeout.d \ +./tx_thread_wait_abort.d \ +./tx_time_get.d \ +./tx_time_set.d \ +./tx_timer_activate.d \ +./tx_timer_change.d \ +./tx_timer_create.d \ +./tx_timer_deactivate.d \ +./tx_timer_delete.d \ +./tx_timer_expiration_process.d \ +./tx_timer_info_get.d \ +./tx_timer_initialize.d \ +./tx_timer_performance_info_get.d \ +./tx_timer_performance_system_info_get.d \ +./tx_timer_system_activate.d \ +./tx_timer_system_deactivate.d \ +./tx_timer_thread_entry.d \ +./tx_trace_buffer_full_notify.d \ +./tx_trace_disable.d \ +./tx_trace_enable.d \ +./tx_trace_event_filter.d \ +./tx_trace_event_unfilter.d \ +./tx_trace_initialize.d \ +./tx_trace_interrupt_control.d \ +./tx_trace_isr_enter_insert.d \ +./tx_trace_isr_exit_insert.d \ +./tx_trace_object_register.d \ +./tx_trace_object_unregister.d \ +./tx_trace_user_event_insert.d \ +./txe_block_allocate.d \ +./txe_block_pool_create.d \ +./txe_block_pool_delete.d \ +./txe_block_pool_info_get.d \ +./txe_block_pool_prioritize.d \ +./txe_block_release.d \ +./txe_byte_allocate.d \ +./txe_byte_pool_create.d \ +./txe_byte_pool_delete.d \ +./txe_byte_pool_info_get.d \ +./txe_byte_pool_prioritize.d \ +./txe_byte_release.d \ +./txe_event_flags_create.d \ +./txe_event_flags_delete.d \ +./txe_event_flags_get.d \ +./txe_event_flags_info_get.d \ +./txe_event_flags_set.d \ +./txe_event_flags_set_notify.d \ +./txe_mutex_create.d \ +./txe_mutex_delete.d \ +./txe_mutex_get.d \ +./txe_mutex_info_get.d \ +./txe_mutex_prioritize.d \ +./txe_mutex_put.d \ +./txe_queue_create.d \ +./txe_queue_delete.d \ +./txe_queue_flush.d \ +./txe_queue_front_send.d \ +./txe_queue_info_get.d \ +./txe_queue_prioritize.d \ +./txe_queue_receive.d \ +./txe_queue_send.d \ +./txe_queue_send_notify.d \ +./txe_semaphore_ceiling_put.d \ +./txe_semaphore_create.d \ +./txe_semaphore_delete.d \ +./txe_semaphore_get.d \ +./txe_semaphore_info_get.d \ +./txe_semaphore_prioritize.d \ +./txe_semaphore_put.d \ +./txe_semaphore_put_notify.d \ +./txe_thread_create.d \ +./txe_thread_delete.d \ +./txe_thread_entry_exit_notify.d \ +./txe_thread_info_get.d \ +./txe_thread_preemption_change.d \ +./txe_thread_priority_change.d \ +./txe_thread_relinquish.d \ +./txe_thread_reset.d \ +./txe_thread_resume.d \ +./txe_thread_suspend.d \ +./txe_thread_terminate.d \ +./txe_thread_time_slice_change.d \ +./txe_thread_wait_abort.d \ +./txe_timer_activate.d \ +./txe_timer_change.d \ +./txe_timer_create.d \ +./txe_timer_deactivate.d \ +./txe_timer_delete.d \ +./txe_timer_info_get.d + +OBJS += \ +./tx_block_allocate.obj \ +./tx_block_pool_cleanup.obj \ +./tx_block_pool_create.obj \ +./tx_block_pool_delete.obj \ +./tx_block_pool_info_get.obj \ +./tx_block_pool_initialize.obj \ +./tx_block_pool_performance_info_get.obj \ +./tx_block_pool_performance_system_info_get.obj \ +./tx_block_pool_prioritize.obj \ +./tx_block_release.obj \ +./tx_byte_allocate.obj \ +./tx_byte_pool_cleanup.obj \ +./tx_byte_pool_create.obj \ +./tx_byte_pool_delete.obj \ +./tx_byte_pool_info_get.obj \ +./tx_byte_pool_initialize.obj \ +./tx_byte_pool_performance_info_get.obj \ +./tx_byte_pool_performance_system_info_get.obj \ +./tx_byte_pool_prioritize.obj \ +./tx_byte_pool_search.obj \ +./tx_byte_release.obj \ +./tx_event_flags_cleanup.obj \ +./tx_event_flags_create.obj \ +./tx_event_flags_delete.obj \ +./tx_event_flags_get.obj \ +./tx_event_flags_info_get.obj \ +./tx_event_flags_initialize.obj \ +./tx_event_flags_performance_info_get.obj \ +./tx_event_flags_performance_system_info_get.obj \ +./tx_event_flags_set.obj \ +./tx_event_flags_set_notify.obj \ +./tx_initialize_high_level.obj \ +./tx_initialize_kernel_enter.obj \ +./tx_initialize_kernel_setup.obj \ +./tx_mutex_cleanup.obj \ +./tx_mutex_create.obj \ +./tx_mutex_delete.obj \ +./tx_mutex_get.obj \ +./tx_mutex_info_get.obj \ +./tx_mutex_initialize.obj \ +./tx_mutex_performance_info_get.obj \ +./tx_mutex_performance_system_info_get.obj \ +./tx_mutex_prioritize.obj \ +./tx_mutex_priority_change.obj \ +./tx_mutex_put.obj \ +./tx_queue_cleanup.obj \ +./tx_queue_create.obj \ +./tx_queue_delete.obj \ +./tx_queue_flush.obj \ +./tx_queue_front_send.obj \ +./tx_queue_info_get.obj \ +./tx_queue_initialize.obj \ +./tx_queue_performance_info_get.obj \ +./tx_queue_performance_system_info_get.obj \ +./tx_queue_prioritize.obj \ +./tx_queue_receive.obj \ +./tx_queue_send.obj \ +./tx_queue_send_notify.obj \ +./tx_semaphore_ceiling_put.obj \ +./tx_semaphore_cleanup.obj \ +./tx_semaphore_create.obj \ +./tx_semaphore_delete.obj \ +./tx_semaphore_get.obj \ +./tx_semaphore_info_get.obj \ +./tx_semaphore_initialize.obj \ +./tx_semaphore_performance_info_get.obj \ +./tx_semaphore_performance_system_info_get.obj \ +./tx_semaphore_prioritize.obj \ +./tx_semaphore_put.obj \ +./tx_semaphore_put_notify.obj \ +./tx_thread_context_restore.obj \ +./tx_thread_context_save.obj \ +./tx_thread_create.obj \ +./tx_thread_delete.obj \ +./tx_thread_entry_exit_notify.obj \ +./tx_thread_identify.obj \ +./tx_thread_info_get.obj \ +./tx_thread_initialize.obj \ +./tx_thread_interrupt_control.obj \ +./tx_thread_performance_info_get.obj \ +./tx_thread_performance_system_info_get.obj \ +./tx_thread_preemption_change.obj \ +./tx_thread_priority_change.obj \ +./tx_thread_relinquish.obj \ +./tx_thread_reset.obj \ +./tx_thread_resume.obj \ +./tx_thread_schedule.obj \ +./tx_thread_shell_entry.obj \ +./tx_thread_sleep.obj \ +./tx_thread_stack_analyze.obj \ +./tx_thread_stack_build.obj \ +./tx_thread_stack_error_handler.obj \ +./tx_thread_stack_error_notify.obj \ +./tx_thread_suspend.obj \ +./tx_thread_system_preempt_check.obj \ +./tx_thread_system_resume.obj \ +./tx_thread_system_return.obj \ +./tx_thread_system_suspend.obj \ +./tx_thread_terminate.obj \ +./tx_thread_time_slice.obj \ +./tx_thread_time_slice_change.obj \ +./tx_thread_timeout.obj \ +./tx_thread_wait_abort.obj \ +./tx_time_get.obj \ +./tx_time_set.obj \ +./tx_timer_activate.obj \ +./tx_timer_change.obj \ +./tx_timer_create.obj \ +./tx_timer_deactivate.obj \ +./tx_timer_delete.obj \ +./tx_timer_expiration_process.obj \ +./tx_timer_info_get.obj \ +./tx_timer_initialize.obj \ +./tx_timer_interrupt.obj \ +./tx_timer_performance_info_get.obj \ +./tx_timer_performance_system_info_get.obj \ +./tx_timer_system_activate.obj \ +./tx_timer_system_deactivate.obj \ +./tx_timer_thread_entry.obj \ +./tx_trace_buffer_full_notify.obj \ +./tx_trace_disable.obj \ +./tx_trace_enable.obj \ +./tx_trace_event_filter.obj \ +./tx_trace_event_unfilter.obj \ +./tx_trace_initialize.obj \ +./tx_trace_interrupt_control.obj \ +./tx_trace_isr_enter_insert.obj \ +./tx_trace_isr_exit_insert.obj \ +./tx_trace_object_register.obj \ +./tx_trace_object_unregister.obj \ +./tx_trace_user_event_insert.obj \ +./txe_block_allocate.obj \ +./txe_block_pool_create.obj \ +./txe_block_pool_delete.obj \ +./txe_block_pool_info_get.obj \ +./txe_block_pool_prioritize.obj \ +./txe_block_release.obj \ +./txe_byte_allocate.obj \ +./txe_byte_pool_create.obj \ +./txe_byte_pool_delete.obj \ +./txe_byte_pool_info_get.obj \ +./txe_byte_pool_prioritize.obj \ +./txe_byte_release.obj \ +./txe_event_flags_create.obj \ +./txe_event_flags_delete.obj \ +./txe_event_flags_get.obj \ +./txe_event_flags_info_get.obj \ +./txe_event_flags_set.obj \ +./txe_event_flags_set_notify.obj \ +./txe_mutex_create.obj \ +./txe_mutex_delete.obj \ +./txe_mutex_get.obj \ +./txe_mutex_info_get.obj \ +./txe_mutex_prioritize.obj \ +./txe_mutex_put.obj \ +./txe_queue_create.obj \ +./txe_queue_delete.obj \ +./txe_queue_flush.obj \ +./txe_queue_front_send.obj \ +./txe_queue_info_get.obj \ +./txe_queue_prioritize.obj \ +./txe_queue_receive.obj \ +./txe_queue_send.obj \ +./txe_queue_send_notify.obj \ +./txe_semaphore_ceiling_put.obj \ +./txe_semaphore_create.obj \ +./txe_semaphore_delete.obj \ +./txe_semaphore_get.obj \ +./txe_semaphore_info_get.obj \ +./txe_semaphore_prioritize.obj \ +./txe_semaphore_put.obj \ +./txe_semaphore_put_notify.obj \ +./txe_thread_create.obj \ +./txe_thread_delete.obj \ +./txe_thread_entry_exit_notify.obj \ +./txe_thread_info_get.obj \ +./txe_thread_preemption_change.obj \ +./txe_thread_priority_change.obj \ +./txe_thread_relinquish.obj \ +./txe_thread_reset.obj \ +./txe_thread_resume.obj \ +./txe_thread_suspend.obj \ +./txe_thread_terminate.obj \ +./txe_thread_time_slice_change.obj \ +./txe_thread_wait_abort.obj \ +./txe_timer_activate.obj \ +./txe_timer_change.obj \ +./txe_timer_create.obj \ +./txe_timer_deactivate.obj \ +./txe_timer_delete.obj \ +./txe_timer_info_get.obj + +ASM_DEPS += \ +./tx_thread_context_restore.d \ +./tx_thread_context_save.d \ +./tx_thread_interrupt_control.d \ +./tx_thread_schedule.d \ +./tx_thread_stack_build.d \ +./tx_thread_system_return.d \ +./tx_timer_interrupt.d + +OBJS__QUOTED += \ +"tx_block_allocate.obj" \ +"tx_block_pool_cleanup.obj" \ +"tx_block_pool_create.obj" \ +"tx_block_pool_delete.obj" \ +"tx_block_pool_info_get.obj" \ +"tx_block_pool_initialize.obj" \ +"tx_block_pool_performance_info_get.obj" \ +"tx_block_pool_performance_system_info_get.obj" \ +"tx_block_pool_prioritize.obj" \ +"tx_block_release.obj" \ +"tx_byte_allocate.obj" \ +"tx_byte_pool_cleanup.obj" \ +"tx_byte_pool_create.obj" \ +"tx_byte_pool_delete.obj" \ +"tx_byte_pool_info_get.obj" \ +"tx_byte_pool_initialize.obj" \ +"tx_byte_pool_performance_info_get.obj" \ +"tx_byte_pool_performance_system_info_get.obj" \ +"tx_byte_pool_prioritize.obj" \ +"tx_byte_pool_search.obj" \ +"tx_byte_release.obj" \ +"tx_event_flags_cleanup.obj" \ +"tx_event_flags_create.obj" \ +"tx_event_flags_delete.obj" \ +"tx_event_flags_get.obj" \ +"tx_event_flags_info_get.obj" \ +"tx_event_flags_initialize.obj" \ +"tx_event_flags_performance_info_get.obj" \ +"tx_event_flags_performance_system_info_get.obj" \ +"tx_event_flags_set.obj" \ +"tx_event_flags_set_notify.obj" \ +"tx_initialize_high_level.obj" \ +"tx_initialize_kernel_enter.obj" \ +"tx_initialize_kernel_setup.obj" \ +"tx_mutex_cleanup.obj" \ +"tx_mutex_create.obj" \ +"tx_mutex_delete.obj" \ +"tx_mutex_get.obj" \ +"tx_mutex_info_get.obj" \ +"tx_mutex_initialize.obj" \ +"tx_mutex_performance_info_get.obj" \ +"tx_mutex_performance_system_info_get.obj" \ +"tx_mutex_prioritize.obj" \ +"tx_mutex_priority_change.obj" \ +"tx_mutex_put.obj" \ +"tx_queue_cleanup.obj" \ +"tx_queue_create.obj" \ +"tx_queue_delete.obj" \ +"tx_queue_flush.obj" \ +"tx_queue_front_send.obj" \ +"tx_queue_info_get.obj" \ +"tx_queue_initialize.obj" \ +"tx_queue_performance_info_get.obj" \ +"tx_queue_performance_system_info_get.obj" \ +"tx_queue_prioritize.obj" \ +"tx_queue_receive.obj" \ +"tx_queue_send.obj" \ +"tx_queue_send_notify.obj" \ +"tx_semaphore_ceiling_put.obj" \ +"tx_semaphore_cleanup.obj" \ +"tx_semaphore_create.obj" \ +"tx_semaphore_delete.obj" \ +"tx_semaphore_get.obj" \ +"tx_semaphore_info_get.obj" \ +"tx_semaphore_initialize.obj" \ +"tx_semaphore_performance_info_get.obj" \ +"tx_semaphore_performance_system_info_get.obj" \ +"tx_semaphore_prioritize.obj" \ +"tx_semaphore_put.obj" \ +"tx_semaphore_put_notify.obj" \ +"tx_thread_context_restore.obj" \ +"tx_thread_context_save.obj" \ +"tx_thread_create.obj" \ +"tx_thread_delete.obj" \ +"tx_thread_entry_exit_notify.obj" \ +"tx_thread_identify.obj" \ +"tx_thread_info_get.obj" \ +"tx_thread_initialize.obj" \ +"tx_thread_interrupt_control.obj" \ +"tx_thread_performance_info_get.obj" \ +"tx_thread_performance_system_info_get.obj" \ +"tx_thread_preemption_change.obj" \ +"tx_thread_priority_change.obj" \ +"tx_thread_relinquish.obj" \ +"tx_thread_reset.obj" \ +"tx_thread_resume.obj" \ +"tx_thread_schedule.obj" \ +"tx_thread_shell_entry.obj" \ +"tx_thread_sleep.obj" \ +"tx_thread_stack_analyze.obj" \ +"tx_thread_stack_build.obj" \ +"tx_thread_stack_error_handler.obj" \ +"tx_thread_stack_error_notify.obj" \ +"tx_thread_suspend.obj" \ +"tx_thread_system_preempt_check.obj" \ +"tx_thread_system_resume.obj" \ +"tx_thread_system_return.obj" \ +"tx_thread_system_suspend.obj" \ +"tx_thread_terminate.obj" \ +"tx_thread_time_slice.obj" \ +"tx_thread_time_slice_change.obj" \ +"tx_thread_timeout.obj" \ +"tx_thread_wait_abort.obj" \ +"tx_time_get.obj" \ +"tx_time_set.obj" \ +"tx_timer_activate.obj" \ +"tx_timer_change.obj" \ +"tx_timer_create.obj" \ +"tx_timer_deactivate.obj" \ +"tx_timer_delete.obj" \ +"tx_timer_expiration_process.obj" \ +"tx_timer_info_get.obj" \ +"tx_timer_initialize.obj" \ +"tx_timer_interrupt.obj" \ +"tx_timer_performance_info_get.obj" \ +"tx_timer_performance_system_info_get.obj" \ +"tx_timer_system_activate.obj" \ +"tx_timer_system_deactivate.obj" \ +"tx_timer_thread_entry.obj" \ +"tx_trace_buffer_full_notify.obj" \ +"tx_trace_disable.obj" \ +"tx_trace_enable.obj" \ +"tx_trace_event_filter.obj" \ +"tx_trace_event_unfilter.obj" \ +"tx_trace_initialize.obj" \ +"tx_trace_interrupt_control.obj" \ +"tx_trace_isr_enter_insert.obj" \ +"tx_trace_isr_exit_insert.obj" \ +"tx_trace_object_register.obj" \ +"tx_trace_object_unregister.obj" \ +"tx_trace_user_event_insert.obj" \ +"txe_block_allocate.obj" \ +"txe_block_pool_create.obj" \ +"txe_block_pool_delete.obj" \ +"txe_block_pool_info_get.obj" \ +"txe_block_pool_prioritize.obj" \ +"txe_block_release.obj" \ +"txe_byte_allocate.obj" \ +"txe_byte_pool_create.obj" \ +"txe_byte_pool_delete.obj" \ +"txe_byte_pool_info_get.obj" \ +"txe_byte_pool_prioritize.obj" \ +"txe_byte_release.obj" \ +"txe_event_flags_create.obj" \ +"txe_event_flags_delete.obj" \ +"txe_event_flags_get.obj" \ +"txe_event_flags_info_get.obj" \ +"txe_event_flags_set.obj" \ +"txe_event_flags_set_notify.obj" \ +"txe_mutex_create.obj" \ +"txe_mutex_delete.obj" \ +"txe_mutex_get.obj" \ +"txe_mutex_info_get.obj" \ +"txe_mutex_prioritize.obj" \ +"txe_mutex_put.obj" \ +"txe_queue_create.obj" \ +"txe_queue_delete.obj" \ +"txe_queue_flush.obj" \ +"txe_queue_front_send.obj" \ +"txe_queue_info_get.obj" \ +"txe_queue_prioritize.obj" \ +"txe_queue_receive.obj" \ +"txe_queue_send.obj" \ +"txe_queue_send_notify.obj" \ +"txe_semaphore_ceiling_put.obj" \ +"txe_semaphore_create.obj" \ +"txe_semaphore_delete.obj" \ +"txe_semaphore_get.obj" \ +"txe_semaphore_info_get.obj" \ +"txe_semaphore_prioritize.obj" \ +"txe_semaphore_put.obj" \ +"txe_semaphore_put_notify.obj" \ +"txe_thread_create.obj" \ +"txe_thread_delete.obj" \ +"txe_thread_entry_exit_notify.obj" \ +"txe_thread_info_get.obj" \ +"txe_thread_preemption_change.obj" \ +"txe_thread_priority_change.obj" \ +"txe_thread_relinquish.obj" \ +"txe_thread_reset.obj" \ +"txe_thread_resume.obj" \ +"txe_thread_suspend.obj" \ +"txe_thread_terminate.obj" \ +"txe_thread_time_slice_change.obj" \ +"txe_thread_wait_abort.obj" \ +"txe_timer_activate.obj" \ +"txe_timer_change.obj" \ +"txe_timer_create.obj" \ +"txe_timer_deactivate.obj" \ +"txe_timer_delete.obj" \ +"txe_timer_info_get.obj" + +C_DEPS__QUOTED += \ +"tx_block_allocate.d" \ +"tx_block_pool_cleanup.d" \ +"tx_block_pool_create.d" \ +"tx_block_pool_delete.d" \ +"tx_block_pool_info_get.d" \ +"tx_block_pool_initialize.d" \ +"tx_block_pool_performance_info_get.d" \ +"tx_block_pool_performance_system_info_get.d" \ +"tx_block_pool_prioritize.d" \ +"tx_block_release.d" \ +"tx_byte_allocate.d" \ +"tx_byte_pool_cleanup.d" \ +"tx_byte_pool_create.d" \ +"tx_byte_pool_delete.d" \ +"tx_byte_pool_info_get.d" \ +"tx_byte_pool_initialize.d" \ +"tx_byte_pool_performance_info_get.d" \ +"tx_byte_pool_performance_system_info_get.d" \ +"tx_byte_pool_prioritize.d" \ +"tx_byte_pool_search.d" \ +"tx_byte_release.d" \ +"tx_event_flags_cleanup.d" \ +"tx_event_flags_create.d" \ +"tx_event_flags_delete.d" \ +"tx_event_flags_get.d" \ +"tx_event_flags_info_get.d" \ +"tx_event_flags_initialize.d" \ +"tx_event_flags_performance_info_get.d" \ +"tx_event_flags_performance_system_info_get.d" \ +"tx_event_flags_set.d" \ +"tx_event_flags_set_notify.d" \ +"tx_initialize_high_level.d" \ +"tx_initialize_kernel_enter.d" \ +"tx_initialize_kernel_setup.d" \ +"tx_mutex_cleanup.d" \ +"tx_mutex_create.d" \ +"tx_mutex_delete.d" \ +"tx_mutex_get.d" \ +"tx_mutex_info_get.d" \ +"tx_mutex_initialize.d" \ +"tx_mutex_performance_info_get.d" \ +"tx_mutex_performance_system_info_get.d" \ +"tx_mutex_prioritize.d" \ +"tx_mutex_priority_change.d" \ +"tx_mutex_put.d" \ +"tx_queue_cleanup.d" \ +"tx_queue_create.d" \ +"tx_queue_delete.d" \ +"tx_queue_flush.d" \ +"tx_queue_front_send.d" \ +"tx_queue_info_get.d" \ +"tx_queue_initialize.d" \ +"tx_queue_performance_info_get.d" \ +"tx_queue_performance_system_info_get.d" \ +"tx_queue_prioritize.d" \ +"tx_queue_receive.d" \ +"tx_queue_send.d" \ +"tx_queue_send_notify.d" \ +"tx_semaphore_ceiling_put.d" \ +"tx_semaphore_cleanup.d" \ +"tx_semaphore_create.d" \ +"tx_semaphore_delete.d" \ +"tx_semaphore_get.d" \ +"tx_semaphore_info_get.d" \ +"tx_semaphore_initialize.d" \ +"tx_semaphore_performance_info_get.d" \ +"tx_semaphore_performance_system_info_get.d" \ +"tx_semaphore_prioritize.d" \ +"tx_semaphore_put.d" \ +"tx_semaphore_put_notify.d" \ +"tx_thread_create.d" \ +"tx_thread_delete.d" \ +"tx_thread_entry_exit_notify.d" \ +"tx_thread_identify.d" \ +"tx_thread_info_get.d" \ +"tx_thread_initialize.d" \ +"tx_thread_performance_info_get.d" \ +"tx_thread_performance_system_info_get.d" \ +"tx_thread_preemption_change.d" \ +"tx_thread_priority_change.d" \ +"tx_thread_relinquish.d" \ +"tx_thread_reset.d" \ +"tx_thread_resume.d" \ +"tx_thread_shell_entry.d" \ +"tx_thread_sleep.d" \ +"tx_thread_stack_analyze.d" \ +"tx_thread_stack_error_handler.d" \ +"tx_thread_stack_error_notify.d" \ +"tx_thread_suspend.d" \ +"tx_thread_system_preempt_check.d" \ +"tx_thread_system_resume.d" \ +"tx_thread_system_suspend.d" \ +"tx_thread_terminate.d" \ +"tx_thread_time_slice.d" \ +"tx_thread_time_slice_change.d" \ +"tx_thread_timeout.d" \ +"tx_thread_wait_abort.d" \ +"tx_time_get.d" \ +"tx_time_set.d" \ +"tx_timer_activate.d" \ +"tx_timer_change.d" \ +"tx_timer_create.d" \ +"tx_timer_deactivate.d" \ +"tx_timer_delete.d" \ +"tx_timer_expiration_process.d" \ +"tx_timer_info_get.d" \ +"tx_timer_initialize.d" \ +"tx_timer_performance_info_get.d" \ +"tx_timer_performance_system_info_get.d" \ +"tx_timer_system_activate.d" \ +"tx_timer_system_deactivate.d" \ +"tx_timer_thread_entry.d" \ +"tx_trace_buffer_full_notify.d" \ +"tx_trace_disable.d" \ +"tx_trace_enable.d" \ +"tx_trace_event_filter.d" \ +"tx_trace_event_unfilter.d" \ +"tx_trace_initialize.d" \ +"tx_trace_interrupt_control.d" \ +"tx_trace_isr_enter_insert.d" \ +"tx_trace_isr_exit_insert.d" \ +"tx_trace_object_register.d" \ +"tx_trace_object_unregister.d" \ +"tx_trace_user_event_insert.d" \ +"txe_block_allocate.d" \ +"txe_block_pool_create.d" \ +"txe_block_pool_delete.d" \ +"txe_block_pool_info_get.d" \ +"txe_block_pool_prioritize.d" \ +"txe_block_release.d" \ +"txe_byte_allocate.d" \ +"txe_byte_pool_create.d" \ +"txe_byte_pool_delete.d" \ +"txe_byte_pool_info_get.d" \ +"txe_byte_pool_prioritize.d" \ +"txe_byte_release.d" \ +"txe_event_flags_create.d" \ +"txe_event_flags_delete.d" \ +"txe_event_flags_get.d" \ +"txe_event_flags_info_get.d" \ +"txe_event_flags_set.d" \ +"txe_event_flags_set_notify.d" \ +"txe_mutex_create.d" \ +"txe_mutex_delete.d" \ +"txe_mutex_get.d" \ +"txe_mutex_info_get.d" \ +"txe_mutex_prioritize.d" \ +"txe_mutex_put.d" \ +"txe_queue_create.d" \ +"txe_queue_delete.d" \ +"txe_queue_flush.d" \ +"txe_queue_front_send.d" \ +"txe_queue_info_get.d" \ +"txe_queue_prioritize.d" \ +"txe_queue_receive.d" \ +"txe_queue_send.d" \ +"txe_queue_send_notify.d" \ +"txe_semaphore_ceiling_put.d" \ +"txe_semaphore_create.d" \ +"txe_semaphore_delete.d" \ +"txe_semaphore_get.d" \ +"txe_semaphore_info_get.d" \ +"txe_semaphore_prioritize.d" \ +"txe_semaphore_put.d" \ +"txe_semaphore_put_notify.d" \ +"txe_thread_create.d" \ +"txe_thread_delete.d" \ +"txe_thread_entry_exit_notify.d" \ +"txe_thread_info_get.d" \ +"txe_thread_preemption_change.d" \ +"txe_thread_priority_change.d" \ +"txe_thread_relinquish.d" \ +"txe_thread_reset.d" \ +"txe_thread_resume.d" \ +"txe_thread_suspend.d" \ +"txe_thread_terminate.d" \ +"txe_thread_time_slice_change.d" \ +"txe_thread_wait_abort.d" \ +"txe_timer_activate.d" \ +"txe_timer_change.d" \ +"txe_timer_create.d" \ +"txe_timer_deactivate.d" \ +"txe_timer_delete.d" \ +"txe_timer_info_get.d" + +ASM_DEPS__QUOTED += \ +"tx_thread_context_restore.d" \ +"tx_thread_context_save.d" \ +"tx_thread_interrupt_control.d" \ +"tx_thread_schedule.d" \ +"tx_thread_stack_build.d" \ +"tx_thread_system_return.d" \ +"tx_timer_interrupt.d" + +C_SRCS__QUOTED += \ +"../tx_block_allocate.c" \ +"../tx_block_pool_cleanup.c" \ +"../tx_block_pool_create.c" \ +"../tx_block_pool_delete.c" \ +"../tx_block_pool_info_get.c" \ +"../tx_block_pool_initialize.c" \ +"../tx_block_pool_performance_info_get.c" \ +"../tx_block_pool_performance_system_info_get.c" \ +"../tx_block_pool_prioritize.c" \ +"../tx_block_release.c" \ +"../tx_byte_allocate.c" \ +"../tx_byte_pool_cleanup.c" \ +"../tx_byte_pool_create.c" \ +"../tx_byte_pool_delete.c" \ +"../tx_byte_pool_info_get.c" \ +"../tx_byte_pool_initialize.c" \ +"../tx_byte_pool_performance_info_get.c" \ +"../tx_byte_pool_performance_system_info_get.c" \ +"../tx_byte_pool_prioritize.c" \ +"../tx_byte_pool_search.c" \ +"../tx_byte_release.c" \ +"../tx_event_flags_cleanup.c" \ +"../tx_event_flags_create.c" \ +"../tx_event_flags_delete.c" \ +"../tx_event_flags_get.c" \ +"../tx_event_flags_info_get.c" \ +"../tx_event_flags_initialize.c" \ +"../tx_event_flags_performance_info_get.c" \ +"../tx_event_flags_performance_system_info_get.c" \ +"../tx_event_flags_set.c" \ +"../tx_event_flags_set_notify.c" \ +"../tx_initialize_high_level.c" \ +"../tx_initialize_kernel_enter.c" \ +"../tx_initialize_kernel_setup.c" \ +"../tx_mutex_cleanup.c" \ +"../tx_mutex_create.c" \ +"../tx_mutex_delete.c" \ +"../tx_mutex_get.c" \ +"../tx_mutex_info_get.c" \ +"../tx_mutex_initialize.c" \ +"../tx_mutex_performance_info_get.c" \ +"../tx_mutex_performance_system_info_get.c" \ +"../tx_mutex_prioritize.c" \ +"../tx_mutex_priority_change.c" \ +"../tx_mutex_put.c" \ +"../tx_queue_cleanup.c" \ +"../tx_queue_create.c" \ +"../tx_queue_delete.c" \ +"../tx_queue_flush.c" \ +"../tx_queue_front_send.c" \ +"../tx_queue_info_get.c" \ +"../tx_queue_initialize.c" \ +"../tx_queue_performance_info_get.c" \ +"../tx_queue_performance_system_info_get.c" \ +"../tx_queue_prioritize.c" \ +"../tx_queue_receive.c" \ +"../tx_queue_send.c" \ +"../tx_queue_send_notify.c" \ +"../tx_semaphore_ceiling_put.c" \ +"../tx_semaphore_cleanup.c" \ +"../tx_semaphore_create.c" \ +"../tx_semaphore_delete.c" \ +"../tx_semaphore_get.c" \ +"../tx_semaphore_info_get.c" \ +"../tx_semaphore_initialize.c" \ +"../tx_semaphore_performance_info_get.c" \ +"../tx_semaphore_performance_system_info_get.c" \ +"../tx_semaphore_prioritize.c" \ +"../tx_semaphore_put.c" \ +"../tx_semaphore_put_notify.c" \ +"../tx_thread_create.c" \ +"../tx_thread_delete.c" \ +"../tx_thread_entry_exit_notify.c" \ +"../tx_thread_identify.c" \ +"../tx_thread_info_get.c" \ +"../tx_thread_initialize.c" \ +"../tx_thread_performance_info_get.c" \ +"../tx_thread_performance_system_info_get.c" \ +"../tx_thread_preemption_change.c" \ +"../tx_thread_priority_change.c" \ +"../tx_thread_relinquish.c" \ +"../tx_thread_reset.c" \ +"../tx_thread_resume.c" \ +"../tx_thread_shell_entry.c" \ +"../tx_thread_sleep.c" \ +"../tx_thread_stack_analyze.c" \ +"../tx_thread_stack_error_handler.c" \ +"../tx_thread_stack_error_notify.c" \ +"../tx_thread_suspend.c" \ +"../tx_thread_system_preempt_check.c" \ +"../tx_thread_system_resume.c" \ +"../tx_thread_system_suspend.c" \ +"../tx_thread_terminate.c" \ +"../tx_thread_time_slice.c" \ +"../tx_thread_time_slice_change.c" \ +"../tx_thread_timeout.c" \ +"../tx_thread_wait_abort.c" \ +"../tx_time_get.c" \ +"../tx_time_set.c" \ +"../tx_timer_activate.c" \ +"../tx_timer_change.c" \ +"../tx_timer_create.c" \ +"../tx_timer_deactivate.c" \ +"../tx_timer_delete.c" \ +"../tx_timer_expiration_process.c" \ +"../tx_timer_info_get.c" \ +"../tx_timer_initialize.c" \ +"../tx_timer_performance_info_get.c" \ +"../tx_timer_performance_system_info_get.c" \ +"../tx_timer_system_activate.c" \ +"../tx_timer_system_deactivate.c" \ +"../tx_timer_thread_entry.c" \ +"../tx_trace_buffer_full_notify.c" \ +"../tx_trace_disable.c" \ +"../tx_trace_enable.c" \ +"../tx_trace_event_filter.c" \ +"../tx_trace_event_unfilter.c" \ +"../tx_trace_initialize.c" \ +"../tx_trace_interrupt_control.c" \ +"../tx_trace_isr_enter_insert.c" \ +"../tx_trace_isr_exit_insert.c" \ +"../tx_trace_object_register.c" \ +"../tx_trace_object_unregister.c" \ +"../tx_trace_user_event_insert.c" \ +"../txe_block_allocate.c" \ +"../txe_block_pool_create.c" \ +"../txe_block_pool_delete.c" \ +"../txe_block_pool_info_get.c" \ +"../txe_block_pool_prioritize.c" \ +"../txe_block_release.c" \ +"../txe_byte_allocate.c" \ +"../txe_byte_pool_create.c" \ +"../txe_byte_pool_delete.c" \ +"../txe_byte_pool_info_get.c" \ +"../txe_byte_pool_prioritize.c" \ +"../txe_byte_release.c" \ +"../txe_event_flags_create.c" \ +"../txe_event_flags_delete.c" \ +"../txe_event_flags_get.c" \ +"../txe_event_flags_info_get.c" \ +"../txe_event_flags_set.c" \ +"../txe_event_flags_set_notify.c" \ +"../txe_mutex_create.c" \ +"../txe_mutex_delete.c" \ +"../txe_mutex_get.c" \ +"../txe_mutex_info_get.c" \ +"../txe_mutex_prioritize.c" \ +"../txe_mutex_put.c" \ +"../txe_queue_create.c" \ +"../txe_queue_delete.c" \ +"../txe_queue_flush.c" \ +"../txe_queue_front_send.c" \ +"../txe_queue_info_get.c" \ +"../txe_queue_prioritize.c" \ +"../txe_queue_receive.c" \ +"../txe_queue_send.c" \ +"../txe_queue_send_notify.c" \ +"../txe_semaphore_ceiling_put.c" \ +"../txe_semaphore_create.c" \ +"../txe_semaphore_delete.c" \ +"../txe_semaphore_get.c" \ +"../txe_semaphore_info_get.c" \ +"../txe_semaphore_prioritize.c" \ +"../txe_semaphore_put.c" \ +"../txe_semaphore_put_notify.c" \ +"../txe_thread_create.c" \ +"../txe_thread_delete.c" \ +"../txe_thread_entry_exit_notify.c" \ +"../txe_thread_info_get.c" \ +"../txe_thread_preemption_change.c" \ +"../txe_thread_priority_change.c" \ +"../txe_thread_relinquish.c" \ +"../txe_thread_reset.c" \ +"../txe_thread_resume.c" \ +"../txe_thread_suspend.c" \ +"../txe_thread_terminate.c" \ +"../txe_thread_time_slice_change.c" \ +"../txe_thread_wait_abort.c" \ +"../txe_timer_activate.c" \ +"../txe_timer_change.c" \ +"../txe_timer_create.c" \ +"../txe_timer_deactivate.c" \ +"../txe_timer_delete.c" \ +"../txe_timer_info_get.c" + +ASM_SRCS__QUOTED += \ +"../tx_thread_context_restore.asm" \ +"../tx_thread_context_save.asm" \ +"../tx_thread_interrupt_control.asm" \ +"../tx_thread_schedule.asm" \ +"../tx_thread_stack_build.asm" \ +"../tx_thread_system_return.asm" \ +"../tx_timer_interrupt.asm" + + |