Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

3 files changed, 13 insertions, 17 deletions

diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S
index f7e3eb2d..a3da17f7 100644
--- a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S
+++ b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S
@@ -1,5 +1,6 @@
 @/***************************************************************************
 @ * Copyright (c) 2024 Microsoft Corporation
+@ * Copyright (c) 2026-present Eclipse ThreadX contributors
 @ *
 @ * This program and the accompanying materials are made available under the
 @ * terms of the MIT License which is available at
@@ -7,6 +8,7 @@
 @ *
 @ * SPDX-License-Identifier: MIT
 @ **************************************************************************/
+@ Portions of this file were generated with AI assistance.
 @
 @
 @/**************************************************************************/
@@ -20,7 +22,6 @@
 @/**************************************************************************/
 @
 @
-    .global  _tx_thread_system_stack_ptr
     .global  _tx_initialize_unused_memory
     .global  _tx_thread_context_save
     .global  _tx_thread_context_restore
@@ -93,24 +94,12 @@ _tx_initialize_low_level:
 @    ORRS    r1, r1, r2                              @ Set the CYCCNTENA bit
 @    STR     r1, [r0]                                @ Enable the cycle count register
 @
-@    /* Setup Vector Table Offset Register.  */
-@
-    LDR     r0, =0xE000E000                         @ Build address of NVIC registers
-    LDR     r2, =0xD08                              @ Offset to vector base register
-    ADD     r0, r0, r2                              @ Build vector base register
-    LDR     r1, =vector_table                       @ Pickup address of vector table
-    STR     r1, [r0]                                @ Set vector table address
-@
-@    /* Set system stack pointer from vector value.  */
-@
-    LDR     r0, =_tx_thread_system_stack_ptr        @ Build address of system stack pointer
-    LDR     r1, =vector_table                       @ Pickup address of vector table
-    LDR     r1, [r1]                                @ Pickup reset stack pointer
-    STR     r1, [r0]                                @ Save system stack pointer
-@
 @    /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference.  */
 @
     LDR     r0, =0xE000E000                         @ Build address of NVIC registers
+    LDR     r1, =0                                  @ Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         @ Reset SysTick Control
+    STR     r1, [r0, #0x18]                         @ Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         @ Setup SysTick Reload Value
     LDR     r1, =0x7                                @ Build SysTick Control Enable Value
diff --git a/ports/cortex_m0/ac6/inc/tx_port.h b/ports/cortex_m0/ac6/inc/tx_port.h
index 006c7e48..8b02e6e3 100644
--- a/ports/cortex_m0/ac6/inc/tx_port.h
+++ b/ports/cortex_m0/ac6/inc/tx_port.h
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -322,11 +324,13 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb sy \n isb sy " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_primask_value();
         __enable_interrupts();
         __restore_interrupts(interrupt_save);
+        __asm__ volatile ("isb sy " : : : "memory");
     }
 }
 
@@ -355,7 +359,7 @@ unsigned int interrupt_save;
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M0/AC6 Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M0/AC6 Version 6.5.2.202603 *";
 #else
 extern  CHAR                    _tx_version_id[];
 #endif
diff --git a/ports/cortex_m0/ac6/src/tx_thread_system_return.S b/ports/cortex_m0/ac6/src/tx_thread_system_return.S
index fc62c0c6..bd7a23f3 100644
--- a/ports/cortex_m0/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m0/ac6/src/tx_thread_system_return.S
@@ -72,12 +72,15 @@ _tx_thread_system_return:
     LDR     r0, =0x10000000                         @ Load PENDSVSET bit
     LDR     r1, =0xE000ED04                         @ Load NVIC base
     STR     r0, [r1]                                @ Set PENDSVBIT in ICSR
+    DSB     #0xF                                    @ Ensure memory access is complete
+    ISB     #0xF                                    @ Flush pipeline
     MRS     r0, IPSR                                @ Pickup IPSR
     CMP     r0, #0                                  @ Is it a thread returning?
     BNE     _isr_context                            @ If ISR, skip interrupt enable
     MRS     r1, PRIMASK                             @ Thread context returning, pickup PRIMASK
     CPSIE   i                                       @ Enable interrupts
     MSR     PRIMASK, r1                             @ Restore original interrupt posture
+    ISB     #0xF                                    @ Flush pipeline
 _isr_context:
     BX      lr                                      @ Return to caller
 @/* }  */