diff options
| author | Yuxin Zhou <[email protected]> | 2021-03-05 05:38:33 +0000 |
|---|---|---|
| committer | Yuxin Zhou <[email protected]> | 2021-03-05 05:38:33 +0000 |
| commit | 10a7932b9d8a9f6f36523cb2f6edf13aa8dee6be (patch) | |
| tree | 87461e5468fb0b4d1416e39fdbc51dceb5ffa2be /ports/cortex_m3/ac5/src | |
| parent | 32e3b3b25f4b17ff51ce8a6bad8d9eb32729a0f6 (diff) | |
Release 6.1.5v6.1.5_rel
Diffstat (limited to 'ports/cortex_m3/ac5/src')
| -rw-r--r-- | ports/cortex_m3/ac5/src/tx_thread_schedule.s | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/ports/cortex_m3/ac5/src/tx_thread_schedule.s b/ports/cortex_m3/ac5/src/tx_thread_schedule.s index c0753dfe..82158967 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m3/ac5/src/tx_thread_schedule.s @@ -30,6 +30,10 @@ IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit ENDIF + IF :DEF:TX_LOW_POWER + IMPORT tx_low_power_enter + IMPORT tx_low_power_exit + ENDIF ; ; AREA ||.text||, CODE, READONLY @@ -39,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/AC5 */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +76,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -217,11 +224,25 @@ __tx_ts_wait LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! - IF :DEF:TX_ENABLE_WFI + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} + ENDIF + + IF:DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed ENDIF + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} + ENDIF + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; |