diff options
| author | Yuxin Zhou <[email protected]> | 2021-07-28 07:24:02 +0000 |
|---|---|---|
| committer | Yuxin Zhou <[email protected]> | 2021-07-28 07:24:02 +0000 |
| commit | d0dab582506f132690b35b36ffea129ad51110b0 (patch) | |
| tree | 13add80dd314dc38efc1830f3d1f36b5a2596e98 /ports/cortex_m33/ac6 | |
| parent | 244365fc6a937c754cfc6bb8e6895dc6f37bac0e (diff) | |
Release 6.1.8v6.1.8_rel
Diffstat (limited to 'ports/cortex_m33/ac6')
19 files changed, 139 insertions, 127 deletions
diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct index 4f774274..b31ea8a4 100644 --- a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct @@ -11,8 +11,8 @@ ; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; <h> RAM Configuration @@ -20,8 +20,8 @@ ; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00020000 /*--------------------- Stack / Heap Configuration --------------------------- ; <h> Stack / Heap Configuration @@ -29,29 +29,27 @@ ; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 /*---------------------------------------------------------------------------- - User Stack & Heap boundary definition + User Stack & Heap boundery definition *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region diff --git a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S index 95ceb7a1..a5e8e946 100644 --- a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -154,10 +154,14 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif /* Do interrupt handler work here */ /* .... */ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} BX LR // } @@ -174,7 +178,13 @@ SysTick_Handler: // VOID TimerInterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} BX LR // } @@ -223,7 +233,7 @@ _unhandled_usage_loop: BL _tx_thread_stack_error_handler // Call ThreadX/user handler POP {r0,lr} // Restore LR and dummy reg -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) // Call the thread exit function to indicate the thread is no longer executing. PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function diff --git a/ports/cortex_m33/ac6/inc/tx_secure_interface.h b/ports/cortex_m33/ac6/inc/tx_secure_interface.h index c2779f40..bab64f05 100644 --- a/ports/cortex_m33/ac6/inc/tx_secure_interface.h +++ b/ports/cortex_m33/ac6/inc/tx_secure_interface.h @@ -51,9 +51,10 @@ /* Define internal secure thread stack function prototypes. */ -extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_initialize(void); extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_initialize(void); extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S index a148559a..3267966b 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S @@ -19,11 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif - - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -48,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* _tx_thread_schedule Thread scheduling routine */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_save.S b/ports/cortex_m33/ac6/src/tx_thread_context_save.S index 90c8e61a..8ca8d4af 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_save.S @@ -20,8 +20,7 @@ /**************************************************************************/ /**************************************************************************/ - -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_enter #endif /**************************************************************************/ @@ -48,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -72,15 +71,13 @@ .type _tx_thread_context_save, function _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return. */ - BX lr // } .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S index bbb3da9a..452c4cae 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S @@ -68,11 +68,15 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller // } .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S index e3a95f5c..51e528ae 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 @@ -70,8 +70,14 @@ .type _tx_thread_interrupt_disable, function _tx_thread_interrupt_disable: /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr // } .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S index 2e29b3cb..f79cb12a 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 @@ -70,7 +70,11 @@ .type _tx_thread_interrupt_restore, function _tx_thread_interrupt_restore: /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr // } .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_schedule.S b/ports/cortex_m33/ac6/src/tx_thread_schedule.S index e0c71318..9ca58e90 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m33/ac6/src/tx_thread_schedule.S @@ -21,7 +21,7 @@ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_thread_enter .global _tx_execution_thread_exit #endif @@ -101,7 +101,6 @@ _tx_thread_schedule: CPSIE i /* Enter the scheduler for the first time. */ - MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR @@ -127,7 +126,7 @@ __tx_wait_here: PendSV_Handler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -135,6 +134,7 @@ __tx_ts_handler: POP {r0, lr} // Recover LR CPSIE i // Enable interrupts #endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address MOV r3, #0 // Build NULL value @@ -211,7 +211,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -243,7 +243,6 @@ _skip_vfp_restore: LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer - /* Return to thread. */ BX lr // Return to thread! /* The following is the idle wait processing... in this case, no threads are ready for execution and the @@ -287,6 +286,7 @@ __tx_ts_ready: /* Re-enable interrupts and restore new thread. */ CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) @@ -299,44 +299,44 @@ __tx_ts_ready: .thumb_func .type SVC_Handler, function SVC_Handler: - TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 + TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 ITE EQ - MRSEQ r0, MSP // Get MSP if return stack is MSP - MRSNE r0, PSP // Get PSP if return stack is PSP + MRSEQ r0, MSP // Get MSP if return stack is MSP + MRSNE r0, PSP // Get PSP if return stack is PSP - LDR r1, [r0,#24] // Load saved PC from stack - LDRB r1, [r1,#-2] // Load SVC number + LDR r1, [r0,#24] // Load saved PC from stack + LDRB r1, [r1,#-2] // Load SVC number - CMP r1, #1 // Is it a secure stack allocate request? - BEQ _tx_svc_secure_alloc // Yes, go there + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there - CMP r1, #2 // Is it a secure stack free request? - BEQ _tx_svc_secure_free // Yes, go there + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there - CMP r1, #3 // Is it a secure stack init request? - BEQ _tx_svc_secure_init // Yes, go there + CMP r1, #3 // Is it a secure stack init request? + BEQ _tx_svc_secure_init // Yes, go there // Unknown SVC argument - just return BX lr _tx_svc_secure_alloc: - PUSH {r0,lr} // Save SP and EXC_RETURN - LDM r0, {r0-r3} // Load function parameters from stack + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate - POP {r12,lr} // Restore SP and EXC_RETURN - STR r0,[r12] // Store function return value + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value BX lr _tx_svc_secure_free: - PUSH {r0,lr} // Save SP and EXC_RETURN - LDM r0, {r0-r3} // Load function parameters from stack + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free - POP {r12,lr} // Restore SP and EXC_RETURN - STR r0,[r12] // Store function return value + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value BX lr _tx_svc_secure_init: - PUSH {r0,lr} // Save SP and EXC_RETURN + PUSH {r0,lr} // Save SP and EXC_RETURN BL _tx_thread_secure_mode_stack_initialize - POP {r12,lr} // Restore SP and EXC_RETURN + POP {r12,lr} // Restore SP and EXC_RETURN BX lr #endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c index e8edd2f5..af8d77f0 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c @@ -29,7 +29,7 @@ #define TX_SOURCE_CODE -#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */ +#include "cmsis_compiler.h" /* For intrinsic functions. */ #include "tx_secure_interface.h" /* Interface for NS code. */ /* Minimum size of secure stack. */ @@ -305,7 +305,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -390,7 +390,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S index 3e3870b0..a3e42ba9 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S @@ -66,7 +66,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_allocate + .global _tx_thread_secure_stack_allocate .thumb_func .type _tx_thread_secure_stack_allocate, function _tx_thread_secure_stack_allocate: diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S index 1511d779..a30f9e8b 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S @@ -64,7 +64,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_free + .global _tx_thread_secure_stack_free .thumb_func .type _tx_thread_secure_stack_free, function _tx_thread_secure_stack_free: diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S index 16f98ef2..f4de0fe6 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S @@ -72,7 +72,7 @@ .type _tx_thread_stack_build, function _tx_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack - on the Cortex-M33 should look like the following after it is built: + on the Cortex-M should look like the following after it is built: Stack Top: LR Interrupted LR (LR at time of PENDSV) diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c index 98e86a2e..5c643784 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c @@ -28,8 +28,8 @@ #include "tx_api.h" #include "tx_thread.h" -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be called via this function pointer. */ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); @@ -38,8 +38,8 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_handler Cortex-M33/AC6 */ -/* 6.1 */ +/* _tx_thread_stack_error_handler Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,7 +75,6 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) { - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR /* Is there a thread? */ if (thread_ptr) @@ -88,10 +87,7 @@ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) /* Determine if the application has registered an error handler. */ if (_tx_thread_application_stack_error_handler != TX_NULL) { - /* Yes, an error handler is present, simply call the application error handler. */ (_tx_thread_application_stack_error_handler)(thread_ptr); } - } - diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c index afa5b98f..0ad24a46 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c @@ -35,8 +35,8 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M33/AC6 */ -/* 6.1 */ +/* _tx_thread_stack_error_notify Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,6 @@ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *threa TX_INTERRUPT_SAVE_AREA - /* Disable interrupts. */ TX_DISABLE @@ -95,4 +94,3 @@ TX_INTERRUPT_SAVE_AREA /* Return success to caller. */ return(TX_SUCCESS); } - diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S index 7094adfd..851eae4e 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m33/ac6/src/tx_thread_system_return.S @@ -75,14 +75,21 @@ _tx_thread_system_return: replaced with in-line assembly in tx_port.h to improved performance. */ MOV r0, #0x10000000 // Load PENDSVSET bit - LDR r1, =0xE000E000 // Load NVIC base + MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller // } diff --git a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S index b1599312..63615c0f 100644 --- a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -74,8 +73,7 @@ .type _tx_timer_interrupt, function _tx_timer_interrupt: - /* Upon entry to this routine, it is assumed that context save has already - been called, and therefore the compiler scratch registers are available + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available for use. */ /* Increment the system clock. */ @@ -92,22 +90,23 @@ _tx_timer_interrupt: LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUB r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOV r0, #1 // Build expired value @@ -127,8 +126,8 @@ __tx_timer_no_time_slice: CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; LDR r3, =_tx_timer_expired // Pickup expiration flag address MOV r2, #1 // Build expired value @@ -140,21 +139,21 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADD r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start @@ -166,7 +165,6 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { @@ -182,7 +180,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -194,8 +192,8 @@ __tx_something_expired: CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -211,8 +209,8 @@ __tx_timer_dont_activate: CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag @@ -223,17 +221,17 @@ __tx_timer_dont_activate: LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register - MOV r2, 0x10000000 // Build value for PendSV bit + LDR r2, =0x10000000 // Build value for PendSV bit CMP r1, r3 // Are they the same? BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: - // } __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment // } @@ -241,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c index 3ff6fa68..e67ebacc 100644 --- a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_allocate PORTABLE C */ -/* 6.1 */ +/* _tx_thread_secure_stack_allocate Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -84,7 +84,6 @@ UINT status; /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -92,7 +91,6 @@ UINT status; /* Now check for invalid thread ID. */ else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -111,7 +109,6 @@ UINT status; /* Determine if everything is okay. */ if (status == TX_SUCCESS) { - /* Call actual secure stack allocate function. */ status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); } @@ -120,4 +117,3 @@ UINT status; return(status); #endif } - diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c index f8207c68..9f6ed6b9 100644 --- a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txe_thread_secure_stack_free PORTABLE C */ -/* 6.1 */ +/* _txe_thread_secure_stack_free Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -118,4 +118,3 @@ UINT status; return(status); #endif } - |