Release 6.1.5v6.1.5_rel

2 files changed, 92 insertions, 71 deletions

diff --git a/ports/cortex_m4/iar/readme_threadx.txt b/ports/cortex_m4/iar/readme_threadx.txt
index 3dfa5c42..fee26deb 100644
--- a/ports/cortex_m4/iar/readme_threadx.txt
+++ b/ports/cortex_m4/iar/readme_threadx.txt
@@ -58,80 +58,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
 
 Non-FPU Stack Frame:
 
-  Stack Offset     Stack Contents 
+    Stack Offset    Stack Contents
 
-     0x00               LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r4          
-     0x08               r5          
-     0x0C               r6          
-     0x10               r7          
-     0x14               r8          
-     0x18               r9          
-     0x1C               r10 (sl)    
-     0x20               r11         
-     0x24               r0          (Hardware stack starts here!!)
-     0x28               r1          
-     0x2C               r2          
-     0x30               r3          
-     0x34               r12         
-     0x38               lr          
-     0x3C               pc          
-     0x40               xPSR        
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
+    0x04            r4          Software stacked GP registers
+    0x08            r5
+    0x0C            r6
+    0x10            r7
+    0x14            r8
+    0x18            r9
+    0x1C            r10
+    0x20            r11
+    0x24            r0          Hardware stacked registers
+    0x28            r1
+    0x2C            r2
+    0x30            r3
+    0x34            r12
+    0x38            lr
+    0x3C            pc
+    0x40            xPSR
 
 FPU Stack Frame (only interrupted thread with FPU enabled):
 
-  Stack Offset     Stack Contents 
+    Stack Offset    Stack Contents
 
-     0x00               LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s0
-     0x08               s1
-     0x0C               s2
-     0x10               s3
-     0x14               s4
-     0x18               s5
-     0x1C               s6
-     0x20               s7
-     0x24               s8
-     0x28               s9
-     0x2C               s10
-     0x30               s11
-     0x34               s12
-     0x38               s13
-     0x3C               s14
-     0x40               s15
-     0x44               s16
-     0x48               s17
-     0x4C               s18
-     0x50               s19
-     0x54               s20
-     0x58               s21
-     0x5C               s22
-     0x60               s23
-     0x64               s24
-     0x68               s25
-     0x6C               s26
-     0x70               s27
-     0x74               s28
-     0x78               s29
-     0x7C               s30
-     0x80               s31
-     0x84               fpscr
-     0x88               r4          
-     0x8C               r5          
-     0x90               r6          
-     0x94               r7          
-     0x98               r8          
-     0x9C               r9          
-     0xA0               r10 (sl)    
-     0xA4               r11         
-     0xA8               r0          (Hardware stack starts here!!)
-     0xAC               r1          
-     0xB0               r2          
-     0xB4               r3          
-     0xB8               r12         
-     0xBC               lr          
-     0xC0               pc          
-     0xC4               xPSR        
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
+    0x04            s16         Software stacked FPU registers
+    0x08            s17
+    0x0C            s18
+    0x10            s19
+    0x14            s20
+    0x18            s21
+    0x1C            s22
+    0x20            s23
+    0x24            s24
+    0x28            s25
+    0x2C            s26
+    0x30            s27
+    0x34            s28
+    0x38            s29
+    0x3C            s30
+    0x40            s31
+    0x44            r4          Software stacked registers
+    0x48            r5
+    0x4C            r6
+    0x50            r7
+    0x54            r8
+    0x58            r9
+    0x5C            r10
+    0x60            r11
+    0x64            r0          Hardware stacked registers
+    0x68            r1
+    0x6C            r2
+    0x70            r3
+    0x74            r12
+    0x78            lr
+    0x7C            pc
+    0x80            xPSR
+    0x84            s0          Hardware stacked FPU registers
+    0x88            s1
+    0x8C            s2
+    0x90            s3
+    0x94            s4
+    0x98            s5
+    0x9C            s6
+    0xA0            s7
+    0xA4            s8
+    0xA8            s9
+    0xAC            s10
+    0xB0            s11
+    0xB4            s12
+    0xB8            s13
+    0xBC            s14
+    0xC0            s15
+    0xC4            fpscr
 
 
 5.  Improving Performance
diff --git a/ports/cortex_m4/iar/src/tx_thread_schedule.s b/ports/cortex_m4/iar/src/tx_thread_schedule.s
index d4356990..45008ba3 100644
--- a/ports/cortex_m4/iar/src/tx_thread_schedule.s
+++ b/ports/cortex_m4/iar/src/tx_thread_schedule.s
@@ -28,6 +28,10 @@
     EXTERN  _tx_execution_thread_enter
     EXTERN  _tx_execution_thread_exit
     EXTERN  _tx_thread_preempt_disable
+#ifdef TX_LOW_POWER
+    EXTERN  tx_low_power_enter
+    EXTERN  tx_low_power_exit
+#endif
 ;
 ;
     SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M4/IAR     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -70,7 +74,10 @@
 ;/*                                                                        */
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
-;/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -236,11 +243,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;