Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

3 files changed, 26 insertions, 18 deletions

diff --git a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s
index 07c27743..f943c572 100644
--- a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s
+++ b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s
@@ -1,5 +1,6 @@
 ;/***************************************************************************
 ; * Copyright (c) 2024 Microsoft Corporation
+; * Copyright (c) 2026-present Eclipse ThreadX contributors
 ; *
 ; * This program and the accompanying materials are made available under the
 ; * terms of the MIT License which is available at
@@ -7,6 +8,7 @@
 ; *
 ; * SPDX-License-Identifier: MIT
 ; **************************************************************************/
+; Portions of this file were generated with AI assistance.
 ;
 ;
 ;/**************************************************************************/
@@ -20,7 +22,6 @@
 ;/**************************************************************************/
 ;
 ;
-    IMPORT  _tx_thread_system_stack_ptr
     IMPORT  _tx_initialize_unused_memory
     IMPORT  _tx_thread_context_save
     IMPORT  _tx_thread_context_restore
@@ -148,12 +149,6 @@ _tx_initialize_low_level
     ADD     r1, r1, #4                              ;
     STR     r1, [r0]                                ; Setup first unused memory pointer
 ;
-;    /* Setup Vector Table Offset Register.  */
-;
-    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
-    LDR     r1, =__tx_vectors                       ; Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        ; Set vector table address
-;
 ;    /* Enable the cycle count register.  */
 ;
 ;    LDR     r0, =0xE0001000                         ; Build address of DWT register
@@ -161,16 +156,12 @@ _tx_initialize_low_level
 ;    ORR     r1, r1, #1                              ; Set the CYCCNTENA bit
 ;    STR     r1, [r0]                                ; Enable the cycle count register
 ;
-;    /* Set system stack pointer from vector value.  */
-;
-    LDR     r0, =_tx_thread_system_stack_ptr        ; Build address of system stack pointer
-    LDR     r1, =__tx_vectors                       ; Pickup address of vector table
-    LDR     r1, [r1]                                ; Pickup reset stack pointer
-    STR     r1, [r0]                                ; Save system stack pointer
-;
 ;    /* Configure SysTick.  */
 ;
     MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    MOV     r1, #0                                  ; Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         ; Reset SysTick Control
+    STR     r1, [r0, #0x18]                         ; Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
     MOV     r1, #0x7                                ; Build SysTick Control Enable Value
diff --git a/ports/cortex_m7/ac5/inc/tx_port.h b/ports/cortex_m7/ac5/inc/tx_port.h
index 1a867956..0f9f49e3 100644
--- a/ports/cortex_m7/ac5/inc/tx_port.h
+++ b/ports/cortex_m7/ac5/inc/tx_port.h
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,8 +541,9 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
+
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
@@ -552,7 +555,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +581,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb sy \n isb sy " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -587,6 +591,7 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb sy " : : : "memory");
     }
 }
 
@@ -699,7 +704,7 @@ void    tx_thread_fpu_disable(void);
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M7/AC5 Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M7/AC5 Version 6.5.2.202603 *";
 #else
 #ifdef TX_MISRA_ENABLE
 extern  CHAR                    _tx_version_id[100];
diff --git a/ports/cortex_m7/ac5/src/tx_thread_schedule.s b/ports/cortex_m7/ac5/src/tx_thread_schedule.s
index 4ff53e17..7929cd0c 100644
--- a/ports/cortex_m7/ac5/src/tx_thread_schedule.s
+++ b/ports/cortex_m7/ac5/src/tx_thread_schedule.s
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -132,7 +134,7 @@ __tx_ts_handler
     BL      _tx_execution_thread_exit               // Call the thread exit function
     POP     {r0, lr}                                // Recover LR
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -260,9 +262,19 @@ __tx_ts_wait
 #endif
 
 #ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+    CPSID   i                                       // Mask every interrupt with PRIMASK, which WFI ignores
+    MOV     r1, #0                                  // Clear BASEPRI so that an interrupt masked by it
+    MSR     BASEPRI, r1                             //   is still able to wake the processor
+#endif
     DSB                                             // Ensure no outstanding memory transactions
     WFI                                             // Wait for interrupt
     ISB                                             // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+    LDR     r1, =TX_PORT_BASEPRI                    // Restore the BASEPRI mask
+    MSR     BASEPRI, r1
+    CPSIE   i                                       // Clear PRIMASK; a pending interrupt is taken here
+#endif
 #endif
 
 #ifdef TX_LOW_POWER