Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

4 files changed, 26 insertions, 21 deletions

diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S
index 11525a95..b97690c2 100644
--- a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S
+++ b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S
@@ -1,5 +1,6 @@
 @/***************************************************************************
 @ * Copyright (c) 2024 Microsoft Corporation
+@ * Copyright (c) 2026-present Eclipse ThreadX contributors
 @ *
 @ * This program and the accompanying materials are made available under the
 @ * terms of the MIT License which is available at
@@ -7,6 +8,7 @@
 @ *
 @ * SPDX-License-Identifier: MIT
 @ **************************************************************************/
+@ Portions of this file were generated with AI assistance.
 @
 @
 @/**************************************************************************/
@@ -20,7 +22,6 @@
 @/**************************************************************************/
 @
 @
-    .global     _tx_thread_system_stack_ptr
     .global     _tx_initialize_unused_memory
     .global     _tx_timer_interrupt
     .global     __main
@@ -93,19 +94,6 @@ _tx_initialize_low_level:
     ADD     r1, r1, #4                              @
     STR     r1, [r0]                                @ Setup first unused memory pointer
 @
-@    /* Setup Vector Table Offset Register.  */
-@
-    MOV     r0, #0xE000E000                         @ Build address of NVIC registers
-    LDR     r1, =vector_table                       @ Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        @ Set vector table address
-@
-@    /* Set system stack pointer from vector value.  */
-@
-    LDR     r0, =_tx_thread_system_stack_ptr        @ Build address of system stack pointer
-    LDR     r1, =vector_table                       @ Pickup address of vector table
-    LDR     r1, [r1]                                @ Pickup reset stack pointer
-    STR     r1, [r0]                                @ Save system stack pointer
-@
 @    /* Enable the cycle count register.  */
 @
     LDR     r0, =0xE0001000                         @ Build address of DWT register
@@ -116,6 +104,9 @@ _tx_initialize_low_level:
 @    /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference.  */
 @
     MOV     r0, #0xE000E000                         @ Build address of NVIC registers
+    MOV     r1, #0                                  @ Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         @ Reset SysTick Control
+    STR     r1, [r0, #0x18]                         @ Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         @ Setup SysTick Reload Value
     MOV     r1, #0x7                                @ Build SysTick Control Enable Value
diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h
index f3947f71..5d280853 100644
--- a/ports/cortex_m7/ac6/inc/tx_port.h
+++ b/ports/cortex_m7/ac6/inc/tx_port.h
@@ -9,8 +9,7 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
-// Some portions generated by Gemini (Gemini 2.0 Flash).
-// Some portions generated by Copilot (Claude Sonnet 4.6).
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -544,8 +543,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
@@ -582,7 +581,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
-    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
+    __asm__ volatile ("dsb sy \n isb sy " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -592,8 +591,10 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb sy " : : : "memory");
     }
 }
+
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);
@@ -703,7 +704,7 @@ void    tx_thread_fpu_disable(void);
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M7/AC6 Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M7/AC6 Version 6.5.2.202603 *";
 #else
 #ifdef TX_MISRA_ENABLE
 extern  CHAR                    _tx_version_id[100];
diff --git a/ports/cortex_m7/ac6/src/tx_thread_schedule.S b/ports/cortex_m7/ac6/src/tx_thread_schedule.S
index e411198e..8c8bdb44 100644
--- a/ports/cortex_m7/ac6/src/tx_thread_schedule.S
+++ b/ports/cortex_m7/ac6/src/tx_thread_schedule.S
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -139,7 +140,7 @@ __tx_ts_handler:
     BL      _tx_execution_thread_exit               // Call the thread exit function
     POP     {r0, lr}                                // Recover LR
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -267,9 +268,19 @@ __tx_ts_wait:
 #endif
 
 #ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+    CPSID   i                                       // Mask every interrupt with PRIMASK, which WFI ignores
+    MOV     r1, #0                                  // Clear BASEPRI so that an interrupt masked by it
+    MSR     BASEPRI, r1                             //   is still able to wake the processor
+#endif
     DSB                                             // Ensure no outstanding memory transactions
     WFI                                             // Wait for interrupt
     ISB                                             // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+    LDR     r1, =TX_PORT_BASEPRI                    // Restore the BASEPRI mask
+    MSR     BASEPRI, r1
+    CPSIE   i                                       // Clear PRIMASK; a pending interrupt is taken here
+#endif
 #endif
 
 #ifdef TX_LOW_POWER
diff --git a/ports/cortex_m7/ac6/src/tx_thread_system_return.S b/ports/cortex_m7/ac6/src/tx_thread_system_return.S
index a092e34c..4071b1a1 100644
--- a/ports/cortex_m7/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m7/ac6/src/tx_thread_system_return.S
@@ -9,7 +9,7 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
-// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -85,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller