Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

7 files changed, 34 insertions, 27 deletions

diff --git a/ports/cortex_m7/iar/CMakeLists.txt b/ports/cortex_m7/iar/CMakeLists.txt
index 57be3aeb..e9583502 100644
--- a/ports/cortex_m7/iar/CMakeLists.txt
+++ b/ports/cortex_m7/iar/CMakeLists.txt
@@ -16,6 +16,7 @@ target_sources(${PROJECT_NAME}
 )
 
 target_include_directories(${PROJECT_NAME}
+    SYSTEM
     PUBLIC
     ${CMAKE_CURRENT_LIST_DIR}/inc
 )
diff --git a/ports/cortex_m7/iar/example_build/tx.ewp b/ports/cortex_m7/iar/example_build/tx.ewp
index 1bb260e3..ea6d4e89 100644
--- a/ports/cortex_m7/iar/example_build/tx.ewp
+++ b/ports/cortex_m7/iar/example_build/tx.ewp
@@ -1047,7 +1047,7 @@
                 </option>
                 <option>
                     <name>IarchiveOutput</name>
-                    <state>C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\Debug\Exe\tx.a</state>
+                    <state>###Unitialized###</state>
                 </option>
             </data>
         </settings>
diff --git a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s
index 76d065cf..b7d109ae 100644
--- a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s
+++ b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s
@@ -1,5 +1,6 @@
 ;/***************************************************************************
 ; * Copyright (c) 2024 Microsoft Corporation
+; * Copyright (c) 2026-present Eclipse ThreadX contributors
 ; *
 ; * This program and the accompanying materials are made available under the
 ; * terms of the MIT License which is available at
@@ -7,6 +8,7 @@
 ; *
 ; * SPDX-License-Identifier: MIT
 ; **************************************************************************/
+; Portions of this file were generated with AI assistance.
 ;
 ;
 ;/**************************************************************************/
@@ -20,10 +22,8 @@
 ;/**************************************************************************/
 ;
 ;
-    EXTERN  _tx_thread_system_stack_ptr
     EXTERN  _tx_initialize_unused_memory
     EXTERN  _tx_timer_interrupt
-    EXTERN  __vector_table
     EXTERN  _tx_execution_isr_enter
     EXTERN  _tx_execution_isr_exit
 ;
@@ -97,22 +97,12 @@ _tx_initialize_low_level:
     ORR     r1, r1, #1                              ; Set the CYCCNTENA bit
     STR     r1, [r0]                                ; Enable the cycle count register
 ;
-;    /* Setup Vector Table Offset Register.  */
-;
-    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
-    LDR     r1, =__vector_table                     ; Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        ; Set vector table address
-;
-;    /* Set system stack pointer from vector value.  */
-;
-    LDR     r0, =_tx_thread_system_stack_ptr        ; Build address of system stack pointer
-    LDR     r1, =__vector_table                     ; Pickup address of vector table
-    LDR     r1, [r1]                                ; Pickup reset stack pointer
-    STR     r1, [r0]                                ; Save system stack pointer
-;
 ;    /* Configure SysTick.  */
 ;
     MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    MOV     r1, #0                                  ; Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         ; Reset SysTick Control
+    STR     r1, [r0, #0x18]                         ; Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
     MOV     r1, #0x7                                ; Build SysTick Control Enable Value
diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h
index b6f19933..9c1d4717 100644
--- a/ports/cortex_m7/iar/inc/tx_port.h
+++ b/ports/cortex_m7/iar/inc/tx_port.h
@@ -9,8 +9,7 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
-// Some portions generated by Gemini (Gemini 2.0 Flash).
-// Some portions generated by Copilot (Claude Sonnet 4.6).
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -544,8 +543,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
@@ -582,7 +581,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
-    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
+    __asm__ volatile ("dsb sy \n isb sy " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -592,8 +591,10 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb sy " : : : "memory");
     }
 }
+
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);
@@ -703,7 +704,7 @@ void    tx_thread_fpu_disable(void);
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M7/IAR Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M7/IAR Version 6.5.2.202603 *";
 #else
 #ifdef TX_MISRA_ENABLE
 extern  CHAR                    _tx_version_id[100];
diff --git a/ports/cortex_m7/iar/src/tx_iar.c b/ports/cortex_m7/iar/src/tx_iar.c
index 238b485e..ab6c209c 100644
--- a/ports/cortex_m7/iar/src/tx_iar.c
+++ b/ports/cortex_m7/iar/src/tx_iar.c
@@ -9,6 +9,7 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
 
 /**************************************************************************/
 /**************************************************************************/
@@ -270,7 +271,7 @@ TX_MUTEX    *mutex_ptr;
         mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
 
         /* Check for wrap-around on the next free mutex.  */
-        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK)
         {
 
             /* Yes, set the free index back to 0.  */
@@ -287,7 +288,7 @@ TX_MUTEX    *mutex_ptr;
     }
 
     /* Determine if a free mutex was found.   */
-    if (i >= _MAX_LOCK)
+    if (i >= _MAX_FLOCK)
     {
 
         /* Error!  No more free mutexes!  */
@@ -678,7 +679,7 @@ TX_MUTEX    *mutex_ptr;
         mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
 
         /* Check for wrap-around on the next free mutex.  */
-        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK)
         {
 
             /* Yes, set the free index back to 0.  */
@@ -695,7 +696,7 @@ TX_MUTEX    *mutex_ptr;
     }
 
     /* Determine if a free mutex was found.   */
-    if (i >= _MAX_LOCK)
+    if (i >= _MAX_FLOCK)
     {
 
         /* Error!  No more free mutexes!  */
diff --git a/ports/cortex_m7/iar/src/tx_thread_schedule.s b/ports/cortex_m7/iar/src/tx_thread_schedule.s
index 58279c1a..847ab02d 100644
--- a/ports/cortex_m7/iar/src/tx_thread_schedule.s
+++ b/ports/cortex_m7/iar/src/tx_thread_schedule.s
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -132,7 +134,7 @@ __tx_ts_handler:
     BL      _tx_execution_thread_exit               // Call the thread exit function
     POP     {r0, lr}                                // Recover LR
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -260,9 +262,19 @@ __tx_ts_wait:
 #endif
 
 #ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+    CPSID   i                                       // Mask every interrupt with PRIMASK, which WFI ignores
+    MOV     r1, #0                                  // Clear BASEPRI so that an interrupt masked by it
+    MSR     BASEPRI, r1                             //   is still able to wake the processor
+#endif
     DSB                                             // Ensure no outstanding memory transactions
     WFI                                             // Wait for interrupt
     ISB                                             // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+    LDR     r1, =TX_PORT_BASEPRI                    // Restore the BASEPRI mask
+    MSR     BASEPRI, r1
+    CPSIE   i                                       // Clear PRIMASK; a pending interrupt is taken here
+#endif
 #endif
 
 #ifdef TX_LOW_POWER
diff --git a/ports/cortex_m7/iar/src/tx_thread_system_return.s b/ports/cortex_m7/iar/src/tx_thread_system_return.s
index 00a07ea8..ab1f05ba 100644
--- a/ports/cortex_m7/iar/src/tx_thread_system_return.s
+++ b/ports/cortex_m7/iar/src/tx_thread_system_return.s
@@ -9,7 +9,7 @@
 ;* SPDX-License-Identifier: MIT
 ;**************************************************************************
 
-; Some portions generated by Gemini (Gemini 2.0 Flash).
+; Portions of this file were generated with AI assistance.
 
 
 ;**************************************************************************
@@ -83,10 +83,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller