updated to 6.0.1 and added additional processors/toolchains

4 files changed, 1005 insertions, 0 deletions

diff --git a/ports/cortex_r5/ac5/example_build/build_threadx.bat b/ports/cortex_r5/ac5/example_build/build_threadx.bat
new file mode 100644
index 00000000..c30b6643
--- /dev/null
+++ b/ports/cortex_r5/ac5/example_build/build_threadx.bat
@@ -0,0 +1,238 @@
+del tx.a
+armasm -g --cpu=cortex-r5 --apcs=interwork tx_initialize_low_level.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_stack_build.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_schedule.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_system_return.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_context_save.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_context_restore.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_interrupt_control.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_timer_interrupt.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_context_restore.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_context_save.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_nesting_end.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_nesting_start.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_interrupt_disable.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_interrupt_restore.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_irq_nesting_end.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_irq_nesting_start.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_vectored_context_save.s
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+armar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o 
+armar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o
+armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_r5/ac5/example_build/build_threadx_sample.bat b/ports/cortex_r5/ac5/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..3adb3bab
--- /dev/null
+++ b/ports/cortex_r5/ac5/example_build/build_threadx_sample.bat
@@ -0,0 +1,4 @@
+armasm -g --cpu=cortex-r5 --apcs=interwork tx_initialize_low_level.s
+armcc -c -g --cpu=cortex-r5 -I../../../../common/inc -I../inc sample_threadx.c
+armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first tx_initialize_low_level.o(Init) --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a
+
diff --git a/ports/cortex_r5/ac5/example_build/sample_threadx.c b/ports/cortex_r5/ac5/example_build/sample_threadx.c
new file mode 100644
index 00000000..418ec634
--- /dev/null
+++ b/ports/cortex_r5/ac5/example_build/sample_threadx.c
@@ -0,0 +1,369 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..b4cbb423
--- /dev/null
+++ b/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s
@@ -0,0 +1,394 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
+FIQ_MODE        EQU     0xD1                    ; FIQ mode
+IRQ_MODE        EQU     0xD2                    ; IRQ mode
+SVC_MODE        EQU     0xD3                    ; SVC mode
+SYS_MODE        EQU     0xDF                    ; SYS mode
+    ELSE
+DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
+FIQ_MODE        EQU     0x91                    ; FIQ mode
+IRQ_MODE        EQU     0x92                    ; IRQ mode
+SVC_MODE        EQU     0x93                    ; SVC mode
+SYS_MODE        EQU     0x9F                    ; SYS mode
+    ENDIF
+HEAP_SIZE       EQU     4096                    ; Heap size
+FIQ_STACK_SIZE  EQU     512                     ; FIQ stack size
+SYS_STACK_SIZE  EQU     1024                    ; SYS stack size (used for nested interrupts)
+IRQ_STACK_SIZE  EQU     1024                    ; IRQ stack size
+;
+;
+    IMPORT      _tx_thread_system_stack_ptr
+    IMPORT      _tx_initialize_unused_memory
+    IMPORT      _tx_thread_context_save
+    IMPORT      _tx_thread_context_restore
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+    IMPORT      _tx_thread_fiq_context_save
+    IMPORT      _tx_thread_fiq_context_restore
+    ENDIF
+    IF  :DEF:TX_ENABLE_IRQ_NESTING
+    IMPORT      _tx_thread_irq_nesting_start
+    IMPORT      _tx_thread_irq_nesting_end
+    ENDIF
+    IF  :DEF:TX_ENABLE_FIQ_NESTING
+    IMPORT      _tx_thread_fiq_nesting_start
+    IMPORT      _tx_thread_fiq_nesting_end
+    ENDIF
+    IMPORT      _tx_timer_interrupt
+    IMPORT      __main
+    IMPORT      _tx_version_id
+    IMPORT      _tx_build_options
+    IMPORT      |Image$$ZI$$Limit|
+;
+;
+        AREA  Init, CODE, READONLY
+;
+;/* Define the default Cortex-R5 vector area.  This should be located or copied to 0.  */
+;
+    EXPORT  __vectors
+__vectors
+    LDR     pc,=__main                          ; Reset goes to startup function
+    LDR     pc,=__tx_undefined                  ; Undefined handler
+    LDR     pc,=__tx_swi_interrupt              ; Software interrupt handler
+    LDR     pc,=__tx_prefetch_handler           ; Prefetch exception handler
+    LDR     pc,=__tx_abort_handler              ; Abort exception handler
+    LDR     pc,=__tx_reserved_handler           ; Reserved exception handler
+    LDR     pc,=__tx_irq_handler                ; IRQ interrupt handler
+    LDR     pc,=__tx_fiq_handler                ; FIQ interrupt handler
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_low_level                           Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for any low-level processor            */ 
+;/*    initialization, including setting up interrupt vectors, setting     */ 
+;/*    up a periodic timer interrupt source, saving the system stack       */ 
+;/*    pointer for use in ISR processing later, and finding the first      */ 
+;/*    available RAM memory address for tx_application_define.             */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    EXPORT  _tx_initialize_low_level
+_tx_initialize_low_level
+;
+;
+;    /****** NOTE ****** We must be in SVC MODE at this point.  Some monitors
+;       enter this routine in USER mode and require a software interrupt to
+;       change into SVC mode.  */
+;
+    LDR     r1, =|Image$$ZI$$Limit|             ; Get end of non-initialized RAM area
+    LDR     r2, =HEAP_SIZE                      ; Pickup the heap size
+    ADD     r1, r2, r1                          ; Setup heap limit
+    ADD     r1, r1, #4                          ; Setup stack limit
+;
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+;    /* Setup the system mode stack for nested interrupt support  */
+    LDR     r2, =SYS_STACK_SIZE                 ; Pickup stack size
+    MOV     r3, #SYS_MODE                       ; Build SYS mode CPSR
+    MSR     CPSR_c, r3                          ; Enter SYS mode
+    ADD     r1, r1, r2                          ; Calculate start of SYS stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    MOV     sp, r1                              ; Setup SYS stack pointer
+    ENDIF
+;
+    LDR     r2, =FIQ_STACK_SIZE                 ; Pickup stack size
+    MOV     r0, #FIQ_MODE                       ; Build FIQ mode CPSR
+    MSR     CPSR_c, r0                          ; Enter FIQ mode
+    ADD     r1, r1, r2                          ; Calculate start of FIQ stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    MOV     sp, r1                              ; Setup FIQ stack pointer
+    MOV     sl, #0                              ; Clear sl
+    MOV     fp, #0                              ; Clear fp
+    LDR     r2, =IRQ_STACK_SIZE                 ; Pickup IRQ (system stack size)
+    MOV     r0, #IRQ_MODE                       ; Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          ; Enter IRQ mode
+    ADD     r1, r1, r2                          ; Calculate start of IRQ stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    MOV     sp, r1                              ; Setup IRQ stack pointer
+    MOV     r0, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r0                          ; Enter SVC mode
+    LDR     r3, =_tx_thread_system_stack_ptr    ; Pickup stack pointer
+    STR     r1, [r3, #0]                        ; Save the system stack
+;
+;    /* Save the system stack pointer.  */
+;    _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
+;
+    LDR     r1, =_tx_thread_system_stack_ptr    ; Pickup address of system stack ptr
+    LDR     r0, [r1, #0]                        ; Pickup system stack 
+    ADD     r0, r0, #4                          ; Increment to next free word
+;
+;    /* Save the first available memory address.  */
+;    _tx_initialize_unused_memory =  (VOID_PTR) |Image$$ZI$$Limit| + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK;
+;
+    LDR     r2, =_tx_initialize_unused_memory   ; Pickup unused memory ptr address
+    STR     r0, [r2, #0]                        ; Save first free memory address
+;
+;    /* Setup Timer for periodic interrupts.  */
+;
+;    /* Done, return to caller.  */
+;
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;}
+;
+;
+;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code.  This
+;   routine will set the initial stack to use the ThreadX IRQ & FIQ & 
+;   (optionally SYS) stack areas.  */
+;
+    EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+    LDR     r0, =|Image$$ZI$$Limit|             ; Get end of non-initialized RAM area
+    LDR     r2, =HEAP_SIZE                      ; Pickup the heap size
+    ADD     r2, r2, r0                          ; Setup heap limit
+    ADD     r3, r2, #4                          ; Setup stack limit
+    MOV     r1, r3                              ; Setup start of stack
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+    LDR     r12, =SYS_STACK_SIZE                ; Pickup IRQ system stack
+    ADD     r1, r1, r12                         ; Setup the return system stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    ENDIF
+    LDR     r12, =FIQ_STACK_SIZE                ; Pickup FIQ stack size
+    ADD     r1, r1, r12                         ; Setup the return system stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    LDR     r12, =IRQ_STACK_SIZE                ; Pickup IRQ system stack
+    ADD     r1, r1, r12                         ; Setup the return system stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;
+;/* Define shells for each of the interrupt vectors.  */
+;
+    EXPORT  __tx_undefined
+__tx_undefined
+    B       __tx_undefined                      ; Undefined handler
+;
+    EXPORT  __tx_swi_interrupt
+__tx_swi_interrupt
+    B       __tx_swi_interrupt                  ; Software interrupt handler
+;
+    EXPORT  __tx_prefetch_handler
+__tx_prefetch_handler
+    B       __tx_prefetch_handler               ; Prefetch exception handler
+;
+    EXPORT  __tx_abort_handler
+__tx_abort_handler
+    B       __tx_abort_handler                  ; Abort exception handler
+;
+    EXPORT  __tx_reserved_handler
+__tx_reserved_handler
+    B       __tx_reserved_handler               ; Reserved exception handler
+;
+;
+    EXPORT  __tx_irq_handler
+    EXPORT  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;
+    BL      _tx_timer_interrupt                 ; Timer interrupt handler
+_tx_not_timer_interrupt
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_start
+    ENDIF
+;
+;
+;    /* Application IRQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_end
+    ENDIF
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+;
+;
+;    /* This is an example of a vectored IRQ handler.  */
+;
+    EXPORT  __tx_example_vectored_irq_handler
+__tx_example_vectored_irq_handler
+;
+;
+;    /* Save initial context and call context save to prepare for 
+;       vectored ISR execution.  */
+;
+;    STMDB   sp!, {r0-r3}                        ; Save some scratch registers
+;    MRS     r0, SPSR                            ; Pickup saved SPSR
+;    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+;    STMDB   sp!, {r0, r10, r12, lr}             ; Store other scratch registers
+;    BL      _tx_thread_vectored_context_save    ; Vectored context save
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+;    IF :DEF:TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_start
+;    ENDIF
+;
+;    /* Application IRQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+;    IF :DEF:TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_end
+;    ENDIF
+;
+;    /* Jump to context restore to restore system context.  */
+;    B       _tx_thread_context_restore
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+    EXPORT  __tx_fiq_handler
+    EXPORT  __tx_fiq_processing_return
+__tx_fiq_handler
+;
+;    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return
+;
+;    /* At this point execution is still in the FIQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  */
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start 
+;       from FIQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with FIQ interrupts enabled. 
+;
+;       NOTE:  It is very important to ensure all FIQ interrupts are cleared 
+;       prior to enabling nested FIQ interrupts.  */
+    IF  :DEF:TX_ENABLE_FIQ_NESTING
+    BL      _tx_thread_fiq_nesting_start
+    ENDIF
+;
+;    /* Application FIQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_fiq_context_restore.  */
+    IF  :DEF:TX_ENABLE_FIQ_NESTING
+    BL      _tx_thread_fiq_nesting_end
+    ENDIF
+;
+;    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+;
+;
+    ELSE
+    EXPORT  __tx_fiq_handler
+__tx_fiq_handler
+    B       __tx_fiq_handler                    ; FIQ interrupt handler
+    ENDIF
+;
+;    /* Reference build options and version ID to ensure they come in.  */
+;
+    LDR     r2, =_tx_build_options              ; Pickup build options variable address
+    LDR     r0, [r2, #0]                        ; Pickup build options content
+    LDR     r2, =_tx_version_id                 ; Pickup version ID variable address
+    LDR     r0, [r2, #0]                        ; Pickup version ID content
+;
+;
+    END
+