Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

1 files changed, 24 insertions, 2 deletions

diff --git a/ports/cortex_r5/gnu/inc/tx_port.h b/ports/cortex_r5/gnu/inc/tx_port.h
index 41f60412..b9b9ab2a 100644
--- a/ports/cortex_r5/gnu/inc/tx_port.h
+++ b/ports/cortex_r5/gnu/inc/tx_port.h
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -183,7 +184,16 @@ typedef unsigned short                          USHORT;
 
 #define TX_THREAD_EXTENSION_0
 #define TX_THREAD_EXTENSION_1
-#define TX_THREAD_EXTENSION_2
+
+/* TX_THREAD_EXTENSION_2 carries the per-thread VFP enable flag that the lazy
+   floating-point save and restore in tx_thread_schedule, tx_thread_system_return
+   and tx_thread_context_restore reads and writes as [thread, #144].  Without it
+   a TX_ENABLE_VFP_SUPPORT build has no such member and those accesses land on
+   tx_thread_filex_ptr instead.  Defined unconditionally, matching the Armv7-A
+   ports: the offset is hard-coded in assembly, so a conditional member would
+   move every following field and be correct in only one configuration.  */
+
+#define TX_THREAD_EXTENSION_2                   ULONG       tx_thread_vfp_enable;
 #define TX_THREAD_EXTENSION_3
 
 
@@ -238,6 +248,18 @@ typedef unsigned short                          USHORT;
 #define TX_TIMER_DELETE_EXTENSION(timer_ptr)
 
 
+/* Per-thread floating-point control, implemented in tx_thread_schedule and
+   available only in a TX_ENABLE_VFP_SUPPORT build.  Floating-point context is
+   saved lazily: only threads that ask for it pay the cost.  Note these set a
+   software flag for the context switch; enabling the FPU itself (CPACR, FPEXC)
+   remains the board support package's responsibility.  */
+
+#ifdef TX_ENABLE_VFP_SUPPORT
+void    tx_thread_vfp_enable(void);
+void    tx_thread_vfp_disable(void);
+#endif
+
+
 /* Determine if the ARM architecture has the CLZ instruction. This is available on
    architectures v5 and above. If available, redefine the macro for calculating the
    lowest bit set.  */
@@ -300,7 +322,7 @@ unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-R5/GNU Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-R5/GNU Version 6.5.2.202603 *";
 #else
 extern  CHAR                    _tx_version_id[];
 #endif