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| author | Frédéric Desbiens <[email protected]> | 2026-06-08 10:01:32 +0200 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-06-08 10:01:32 +0200 |
| commit | 87ab09cce305eb9cd4aacac4e8c62af72f665bff (patch) | |
| tree | dd062ebbea5235d1921c64b396bf7e4ce79e9e15 /ports/risc-v32/gnu/src/tx_thread_context_save.S | |
| parent | 9ab0cf9683f832cdb48e2099533a5b06a3afcd64 (diff) | |
| parent | 730b61874bc5cf40768987605ae5187fde0fa1e2 (diff) | |
Merge pull request #544 from eclipse-threadx/devv6.5.1.202602_rel
Merging changes for the v.6.5.1.202602 release
Diffstat (limited to 'ports/risc-v32/gnu/src/tx_thread_context_save.S')
| -rw-r--r-- | ports/risc-v32/gnu/src/tx_thread_context_save.S | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/ports/risc-v32/gnu/src/tx_thread_context_save.S b/ports/risc-v32/gnu/src/tx_thread_context_save.S index 66402934..0a0c0c15 100644 --- a/ports/risc-v32/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v32/gnu/src/tx_thread_context_save.S @@ -29,6 +29,7 @@ /* AUTHOR */ /* */ /* Akif Ejaz, 10xEngineers */ +/* Wei-Chen Lai, National Cheng Kung University */ /* */ /* DESCRIPTION */ /* */ @@ -96,6 +97,15 @@ _tx_thread_context_save: sw t5, 14*4(sp) // Store t5 sw t6, 13*4(sp) // Store t6 + /* Save mstatus and skip FP state if FS is Off. */ + csrr t0, mstatus + sw t0, 29*4(sp) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + srli t1, t0, 13 + andi t1, t1, 0x3 + beqz t1, _tx_thread_skip_fpu_save +#endif + /* Save floating point registers. */ #if defined(__riscv_float_abi_single) fsw f0, 31*4(sp) // Store ft0 @@ -144,14 +154,11 @@ _tx_thread_context_save: csrr t0, fcsr sw t0, 63*4(sp) // Store fcsr #endif +_tx_thread_skip_fpu_save: csrr t0, mepc sw t0, 30*4(sp) // Save it on the stack - /* Save mstatus. */ - csrr t0, mstatus - sw t0, 29*4(sp) - la t1, _tx_thread_current_ptr // Pickup address of current thread ptr lw t2, 0(t1) // Pickup current thread pointer beqz t2, _tx_thread_idle_system_save // If NULL, idle system was interrupted @@ -190,6 +197,15 @@ _tx_thread_nested_save: sw t5, 14*4(sp) // Store t5 sw t6, 13*4(sp) // Store t6 + /* Save mstatus and skip FP state if FS is Off. */ + csrr t0, mstatus + sw t0, 29*4(sp) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + srli t1, t0, 13 + andi t1, t1, 0x3 + beqz t1, _tx_thread_skip_nested_fpu_save +#endif + /* Save floating point registers. */ #if defined(__riscv_float_abi_single) fsw f0, 31*4(sp) // Store ft0 @@ -238,13 +254,11 @@ _tx_thread_nested_save: csrr t0, fcsr sw t0, 63*4(sp) // Store fcsr #endif +_tx_thread_skip_nested_fpu_save: csrr t0, mepc sw t0, 30*4(sp) // Save it on stack - csrr t0, mstatus - sw t0, 29*4(sp) - /* Call the ISR execution exit function if enabled. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY call _tx_execution_isr_enter // Call the ISR execution enter function |