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authorFrédéric Desbiens <[email protected]>2026-10-02 10:42:44 -0400
committerGitHub <[email protected]>2026-10-02 10:42:44 -0400
commit93387b0a60382a29579bbad5045c68328e3751df (patch)
tree42be790d602cb76f55090e5a7c418df7ea2b3428 /ports/risc-v32/gnu/src
parent44d7c95c582d415c4ad84527180b29c93c3bf664 (diff)
parent28281cd5647d4671236ca08d19bd18ed15b2265a (diff)
Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel
Merged changes ahead of the v6.5.2.202603 release
Diffstat (limited to 'ports/risc-v32/gnu/src')
-rw-r--r--ports/risc-v32/gnu/src/tx_initialize_low_level.S9
-rw-r--r--ports/risc-v32/gnu/src/tx_thread_context_restore.S205
-rw-r--r--ports/risc-v32/gnu/src/tx_thread_context_save.S168
-rw-r--r--ports/risc-v32/gnu/src/tx_thread_schedule.S171
-rw-r--r--ports/risc-v32/gnu/src/tx_thread_stack_build.S104
-rw-r--r--ports/risc-v32/gnu/src/tx_thread_system_return.S57
-rw-r--r--ports/risc-v32/gnu/src/tx_timer_interrupt.S4
7 files changed, 247 insertions, 471 deletions
diff --git a/ports/risc-v32/gnu/src/tx_initialize_low_level.S b/ports/risc-v32/gnu/src/tx_initialize_low_level.S
index 2940f215..ca97ba62 100644
--- a/ports/risc-v32/gnu/src/tx_initialize_low_level.S
+++ b/ports/risc-v32/gnu/src/tx_initialize_low_level.S
@@ -62,8 +62,7 @@ __tx_free_memory_start:
/**************************************************************************/
/* VOID _tx_initialize_low_level(VOID)
{ */
- .weak _tx_initialize_low_level
- .weak _tx_initialize_low_level
+ .weak _tx_initialize_low_level // Weak: a BSP definition overrides this default
_tx_initialize_low_level:
/* Save the system stack pointer. */
@@ -79,8 +78,10 @@ _tx_initialize_low_level:
la t1, _tx_initialize_unused_memory // Pickup address of unused memory
sw t0, 0(t1) // Save unused memory address
- /* Initialize floating point control/status register if floating point is enabled. */
-#ifdef __riscv_flen
+ /* Initialize floating point state if floating point is enabled. */
+#if defined(__riscv_float_abi_double)
+ li t0, 0x2000 // mstatus.FS = Initial (bits 14:13 = 01)
+ csrrs zero, mstatus, t0 // Enable the FP unit before touching fcsr
li t0, 0
csrw fcsr, t0 // Clear FP control/status register
#endif
diff --git a/ports/risc-v32/gnu/src/tx_thread_context_restore.S b/ports/risc-v32/gnu/src/tx_thread_context_restore.S
index d3d449e4..c4854643 100644
--- a/ports/risc-v32/gnu/src/tx_thread_context_restore.S
+++ b/ports/risc-v32/gnu/src/tx_thread_context_restore.S
@@ -20,6 +20,14 @@
/**************************************************************************/
.section .text
+
+/* Trap frame layout (stack grows down, all totals mod 16 = 0):
+ FP build (double ABI): integer slots 0-31 at i*4 (0-127; slot 31 is pad),
+ f0-f31 as doubles at 128 + i*8 (128-383), fcsr at 384, pad 388-399.
+ SOFT_FLOAT build: integer slots 0-31 at i*4 only. */
+#include "tx_port.h"
+ .equ TX_TRAP_FRAME_SIZE, TX_RISCV_TRAP_FRAME_SIZE
+
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -84,57 +92,32 @@ _tx_thread_context_restore:
interrupt. */
/* Recover floating point registers only if saved mstatus.FS was not Off. */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
lw t1, 29*4(sp) // Pickup saved mstatus
srli t1, t1, 13
andi t1, t1, 0x3
beqz t1, _tx_thread_skip_fp_restore // Skip if FS was Off
-#endif
-#if defined(__riscv_float_abi_single)
- flw f0, 31*4(sp) // Recover ft0
- flw f1, 32*4(sp) // Recover ft1
- flw f2, 33*4(sp) // Recover ft2
- flw f3, 34*4(sp) // Recover ft3
- flw f4, 35*4(sp) // Recover ft4
- flw f5, 36*4(sp) // Recover ft5
- flw f6, 37*4(sp) // Recover ft6
- flw f7, 38*4(sp) // Recover ft7
- flw f10, 41*4(sp) // Recover fa0
- flw f11, 42*4(sp) // Recover fa1
- flw f12, 43*4(sp) // Recover fa2
- flw f13, 44*4(sp) // Recover fa3
- flw f14, 45*4(sp) // Recover fa4
- flw f15, 46*4(sp) // Recover fa5
- flw f16, 47*4(sp) // Recover fa6
- flw f17, 48*4(sp) // Recover fa7
- flw f28, 59*4(sp) // Recover ft8
- flw f29, 60*4(sp) // Recover ft9
- flw f30, 61*4(sp) // Recover ft10
- flw f31, 62*4(sp) // Recover ft11
- lw t0, 63*4(sp) // Recover fcsr
- csrw fcsr, t0 // Restore fcsr
-#elif defined(__riscv_float_abi_double)
- fld f0, 31*4(sp) // Recover ft0
- fld f1, 32*4(sp) // Recover ft1
- fld f2, 33*4(sp) // Recover ft2
- fld f3, 34*4(sp) // Recover ft3
- fld f4, 35*4(sp) // Recover ft4
- fld f5, 36*4(sp) // Recover ft5
- fld f6, 37*4(sp) // Recover ft6
- fld f7, 38*4(sp) // Recover ft7
- fld f10, 41*4(sp) // Recover fa0
- fld f11, 42*4(sp) // Recover fa1
- fld f12, 43*4(sp) // Recover fa2
- fld f13, 44*4(sp) // Recover fa3
- fld f14, 45*4(sp) // Recover fa4
- fld f15, 46*4(sp) // Recover fa5
- fld f16, 47*4(sp) // Recover fa6
- fld f17, 48*4(sp) // Recover fa7
- fld f28, 59*4(sp) // Recover ft8
- fld f29, 60*4(sp) // Recover ft9
- fld f30, 61*4(sp) // Recover ft10
- fld f31, 62*4(sp) // Recover ft11
- lw t0, 63*4(sp) // Recover fcsr
+ fld f0, 16*8(sp) // Recover ft0
+ fld f1, 17*8(sp) // Recover ft1
+ fld f2, 18*8(sp) // Recover ft2
+ fld f3, 19*8(sp) // Recover ft3
+ fld f4, 20*8(sp) // Recover ft4
+ fld f5, 21*8(sp) // Recover ft5
+ fld f6, 22*8(sp) // Recover ft6
+ fld f7, 23*8(sp) // Recover ft7
+ fld f10, 26*8(sp) // Recover fa0
+ fld f11, 27*8(sp) // Recover fa1
+ fld f12, 28*8(sp) // Recover fa2
+ fld f13, 29*8(sp) // Recover fa3
+ fld f14, 30*8(sp) // Recover fa4
+ fld f15, 31*8(sp) // Recover fa5
+ fld f16, 32*8(sp) // Recover fa6
+ fld f17, 33*8(sp) // Recover fa7
+ fld f28, 44*8(sp) // Recover ft8
+ fld f29, 45*8(sp) // Recover ft9
+ fld f30, 46*8(sp) // Recover ft10
+ fld f31, 47*8(sp) // Recover ft11
+ lw t0, 96*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#endif
_tx_thread_skip_fp_restore:
@@ -166,7 +149,7 @@ _tx_thread_skip_fp_restore:
and t1, t1, t4
or t1, t1, t3
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state
or t1, t1, t0
#endif
@@ -190,11 +173,7 @@ _tx_thread_skip_fp_restore:
lw t5, 14*4(sp) // Recover t5
lw t6, 13*4(sp) // Recover t6
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
-#else
- addi sp, sp, 32*4 // Recover stack frame - without floating point enabled
-#endif
+ addi sp, sp, TX_TRAP_FRAME_SIZE // Recover stack frame
mret // Return to point of interrupt
/* } */
@@ -213,7 +192,7 @@ _tx_thread_not_nested_restore:
la t0, _tx_thread_preempt_disable // Pickup preempt disable flag address
lw t2, 0(t0) // Pickup preempt disable flag (UINT)
- bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread
+ bnez t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread
la t0, _tx_thread_execute_ptr // Pickup thread execute pointer address
@@ -231,57 +210,32 @@ _tx_thread_no_preempt_restore:
lw sp, 8(t1) // Switch back to thread's stack
/* Recover floating point registers only if saved mstatus.FS was not Off. */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
lw t3, 29*4(sp) // Pickup saved mstatus
srli t3, t3, 13
andi t3, t3, 0x3
beqz t3, _tx_thread_no_preempt_skip_fp_restore // Skip if FS was Off
-#endif
-#if defined(__riscv_float_abi_single)
- flw f0, 31*4(sp) // Recover ft0
- flw f1, 32*4(sp) // Recover ft1
- flw f2, 33*4(sp) // Recover ft2
- flw f3, 34*4(sp) // Recover ft3
- flw f4, 35*4(sp) // Recover ft4
- flw f5, 36*4(sp) // Recover ft5
- flw f6, 37*4(sp) // Recover ft6
- flw f7, 38*4(sp) // Recover ft7
- flw f10, 41*4(sp) // Recover fa0
- flw f11, 42*4(sp) // Recover fa1
- flw f12, 43*4(sp) // Recover fa2
- flw f13, 44*4(sp) // Recover fa3
- flw f14, 45*4(sp) // Recover fa4
- flw f15, 46*4(sp) // Recover fa5
- flw f16, 47*4(sp) // Recover fa6
- flw f17, 48*4(sp) // Recover fa7
- flw f28, 59*4(sp) // Recover ft8
- flw f29, 60*4(sp) // Recover ft9
- flw f30, 61*4(sp) // Recover ft10
- flw f31, 62*4(sp) // Recover ft11
- lw t0, 63*4(sp) // Recover fcsr
- csrw fcsr, t0 // Restore fcsr
-#elif defined(__riscv_float_abi_double)
- fld f0, 31*4(sp) // Recover ft0
- fld f1, 32*4(sp) // Recover ft1
- fld f2, 33*4(sp) // Recover ft2
- fld f3, 34*4(sp) // Recover ft3
- fld f4, 35*4(sp) // Recover ft4
- fld f5, 36*4(sp) // Recover ft5
- fld f6, 37*4(sp) // Recover ft6
- fld f7, 38*4(sp) // Recover ft7
- fld f10, 41*4(sp) // Recover fa0
- fld f11, 42*4(sp) // Recover fa1
- fld f12, 43*4(sp) // Recover fa2
- fld f13, 44*4(sp) // Recover fa3
- fld f14, 45*4(sp) // Recover fa4
- fld f15, 46*4(sp) // Recover fa5
- fld f16, 47*4(sp) // Recover fa6
- fld f17, 48*4(sp) // Recover fa7
- fld f28, 59*4(sp) // Recover ft8
- fld f29, 60*4(sp) // Recover ft9
- fld f30, 61*4(sp) // Recover ft10
- fld f31, 62*4(sp) // Recover ft11
- lw t0, 63*4(sp) // Recover fcsr
+ fld f0, 16*8(sp) // Recover ft0
+ fld f1, 17*8(sp) // Recover ft1
+ fld f2, 18*8(sp) // Recover ft2
+ fld f3, 19*8(sp) // Recover ft3
+ fld f4, 20*8(sp) // Recover ft4
+ fld f5, 21*8(sp) // Recover ft5
+ fld f6, 22*8(sp) // Recover ft6
+ fld f7, 23*8(sp) // Recover ft7
+ fld f10, 26*8(sp) // Recover fa0
+ fld f11, 27*8(sp) // Recover fa1
+ fld f12, 28*8(sp) // Recover fa2
+ fld f13, 29*8(sp) // Recover fa3
+ fld f14, 30*8(sp) // Recover fa4
+ fld f15, 31*8(sp) // Recover fa5
+ fld f16, 32*8(sp) // Recover fa6
+ fld f17, 33*8(sp) // Recover fa7
+ fld f28, 44*8(sp) // Recover ft8
+ fld f29, 45*8(sp) // Recover ft9
+ fld f30, 46*8(sp) // Recover ft10
+ fld f31, 47*8(sp) // Recover ft11
+ lw t0, 96*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#endif
_tx_thread_no_preempt_skip_fp_restore:
@@ -304,7 +258,7 @@ _tx_thread_no_preempt_skip_fp_restore:
and t1, t1, t4
or t1, t1, t3
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
li t0, 0x2000 // Set FS bits for FP state
or t1, t1, t0
#endif
@@ -328,11 +282,7 @@ _tx_thread_no_preempt_skip_fp_restore:
lw t5, 14*4(sp) // Recover t5
lw t6, 13*4(sp) // Recover t6
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
-#else
- addi sp, sp, 32*4 // Recover stack frame - without floating point enabled
-#endif
+ addi sp, sp, TX_TRAP_FRAME_SIZE // Recover stack frame
mret // Return to point of interrupt
/* }
@@ -347,38 +297,23 @@ _tx_thread_preempt_restore:
sw t3, 0(t0) // Store stack type
/* Store floating point preserved registers only if saved mstatus.FS was not Off. */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
lw t3, 29*4(t0) // Pickup saved mstatus
srli t3, t3, 13
andi t3, t3, 0x3
beqz t3, _tx_thread_preempt_skip_fp_restore // Skip if FS was Off
-#endif
-#ifdef __riscv_float_abi_single
- fsw f8, 39*4(t0) // Store fs0
- fsw f9, 40*4(t0) // Store fs1
- fsw f18, 49*4(t0) // Store fs2
- fsw f19, 50*4(t0) // Store fs3
- fsw f20, 51*4(t0) // Store fs4
- fsw f21, 52*4(t0) // Store fs5
- fsw f22, 53*4(t0) // Store fs6
- fsw f23, 54*4(t0) // Store fs7
- fsw f24, 55*4(t0) // Store fs8
- fsw f25, 56*4(t0) // Store fs9
- fsw f26, 57*4(t0) // Store fs10
- fsw f27, 58*4(t0) // Store fs11
-#elif defined(__riscv_float_abi_double)
- fsd f8, 39*4(t0) // Store fs0
- fsd f9, 40*4(t0) // Store fs1
- fsd f18, 49*4(t0) // Store fs2
- fsd f19, 50*4(t0) // Store fs3
- fsd f20, 51*4(t0) // Store fs4
- fsd f21, 52*4(t0) // Store fs5
- fsd f22, 53*4(t0) // Store fs6
- fsd f23, 54*4(t0) // Store fs7
- fsd f24, 55*4(t0) // Store fs8
- fsd f25, 56*4(t0) // Store fs9
- fsd f26, 57*4(t0) // Store fs10
- fsd f27, 58*4(t0) // Store fs11
+ fsd f8, 192(t0) // Store fs0
+ fsd f9, 200(t0) // Store fs1
+ fsd f18, 272(t0) // Store fs2
+ fsd f19, 280(t0) // Store fs3
+ fsd f20, 288(t0) // Store fs4
+ fsd f21, 296(t0) // Store fs5
+ fsd f22, 304(t0) // Store fs6
+ fsd f23, 312(t0) // Store fs7
+ fsd f24, 320(t0) // Store fs8
+ fsd f25, 328(t0) // Store fs9
+ fsd f26, 336(t0) // Store fs10
+ fsd f27, 344(t0) // Store fs11
#endif
_tx_thread_preempt_skip_fp_restore:
diff --git a/ports/risc-v32/gnu/src/tx_thread_context_save.S b/ports/risc-v32/gnu/src/tx_thread_context_save.S
index 0a0c0c15..e93d5870 100644
--- a/ports/risc-v32/gnu/src/tx_thread_context_save.S
+++ b/ports/risc-v32/gnu/src/tx_thread_context_save.S
@@ -1,5 +1,6 @@
/***************************************************************************
* Copyright (c) 2025 10xEngineers
+ * Copyright (c) 2026 Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
@@ -8,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
+// Portions of this file were generated with AI assistance.
/**************************************************************************/
/**************************************************************************/
@@ -20,6 +22,10 @@
/**************************************************************************/
.section .text
+
+#include "tx_port.h"
+ .equ TX_TRAP_FRAME_SIZE, TX_RISCV_TRAP_FRAME_SIZE
+
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -61,7 +67,7 @@ _tx_thread_context_save:
/* Upon entry to this routine, RA/x1 has been saved on the stack
and the stack has been already allocated for the entire context:
- addi sp, sp, -32*4 (or -65*4)
+ addi sp, sp, -TX_TRAP_FRAME_SIZE (400 with FP, 128 without)
sw ra, 28*4(sp)
*/
@@ -100,59 +106,34 @@ _tx_thread_context_save:
/* Save mstatus and skip FP state if FS is Off. */
csrr t0, mstatus
sw t0, 29*4(sp)
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
srli t1, t0, 13
andi t1, t1, 0x3
beqz t1, _tx_thread_skip_fpu_save
-#endif
- /* Save floating point registers. */
-#if defined(__riscv_float_abi_single)
- fsw f0, 31*4(sp) // Store ft0
- fsw f1, 32*4(sp) // Store ft1
- fsw f2, 33*4(sp) // Store ft2
- fsw f3, 34*4(sp) // Store ft3
- fsw f4, 35*4(sp) // Store ft4
- fsw f5, 36*4(sp) // Store ft5
- fsw f6, 37*4(sp) // Store ft6
- fsw f7, 38*4(sp) // Store ft7
- fsw f10, 41*4(sp) // Store fa0
- fsw f11, 42*4(sp) // Store fa1
- fsw f12, 43*4(sp) // Store fa2
- fsw f13, 44*4(sp) // Store fa3
- fsw f14, 45*4(sp) // Store fa4
- fsw f15, 46*4(sp) // Store fa5
- fsw f16, 47*4(sp) // Store fa6
- fsw f17, 48*4(sp) // Store fa7
- fsw f28, 59*4(sp) // Store ft8
- fsw f29, 60*4(sp) // Store ft9
- fsw f30, 61*4(sp) // Store ft10
- fsw f31, 62*4(sp) // Store ft11
- csrr t0, fcsr
- sw t0, 63*4(sp) // Store fcsr
-#elif defined(__riscv_float_abi_double)
- fsd f0, 31*4(sp) // Store ft0
- fsd f1, 32*4(sp) // Store ft1
- fsd f2, 33*4(sp) // Store ft2
- fsd f3, 34*4(sp) // Store ft3
- fsd f4, 35*4(sp) // Store ft4
- fsd f5, 36*4(sp) // Store ft5
- fsd f6, 37*4(sp) // Store ft6
- fsd f7, 38*4(sp) // Store ft7
- fsd f10, 41*4(sp) // Store fa0
- fsd f11, 42*4(sp) // Store fa1
- fsd f12, 43*4(sp) // Store fa2
- fsd f13, 44*4(sp) // Store fa3
- fsd f14, 45*4(sp) // Store fa4
- fsd f15, 46*4(sp) // Store fa5
- fsd f16, 47*4(sp) // Store fa6
- fsd f17, 48*4(sp) // Store fa7
- fsd f28, 59*4(sp) // Store ft8
- fsd f29, 60*4(sp) // Store ft9
- fsd f30, 61*4(sp) // Store ft10
- fsd f31, 62*4(sp) // Store ft11
+ /* Save floating point registers (doubles at 128 + i*8). */
+ fsd f0, 16*8(sp) // Store ft0
+ fsd f1, 17*8(sp) // Store ft1
+ fsd f2, 18*8(sp) // Store ft2
+ fsd f3, 19*8(sp) // Store ft3
+ fsd f4, 20*8(sp) // Store ft4
+ fsd f5, 21*8(sp) // Store ft5
+ fsd f6, 22*8(sp) // Store ft6
+ fsd f7, 23*8(sp) // Store ft7
+ fsd f10, 26*8(sp) // Store fa0
+ fsd f11, 27*8(sp) // Store fa1
+ fsd f12, 28*8(sp) // Store fa2
+ fsd f13, 29*8(sp) // Store fa3
+ fsd f14, 30*8(sp) // Store fa4
+ fsd f15, 31*8(sp) // Store fa5
+ fsd f16, 32*8(sp) // Store fa6
+ fsd f17, 33*8(sp) // Store fa7
+ fsd f28, 44*8(sp) // Store ft8
+ fsd f29, 45*8(sp) // Store ft9
+ fsd f30, 46*8(sp) // Store ft10
+ fsd f31, 47*8(sp) // Store ft11
csrr t0, fcsr
- sw t0, 63*4(sp) // Store fcsr
+ sw t0, 96*4(sp) // Store fcsr
#endif
_tx_thread_skip_fpu_save:
@@ -173,7 +154,11 @@ _tx_thread_skip_fpu_save:
/* Call the ISR execution exit function if enabled. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+ addi sp, sp, -16 // Reserve space to save the return address
+ sw ra, 0(sp) // Save the return address
call _tx_execution_isr_enter // Call the ISR execution enter function
+ lw ra, 0(sp) // Recover the return address
+ addi sp, sp, 16 // Recover the reserved stack space
#endif
ret // Return to ISR
@@ -200,59 +185,34 @@ _tx_thread_nested_save:
/* Save mstatus and skip FP state if FS is Off. */
csrr t0, mstatus
sw t0, 29*4(sp)
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
srli t1, t0, 13
andi t1, t1, 0x3
beqz t1, _tx_thread_skip_nested_fpu_save
-#endif
- /* Save floating point registers. */
-#if defined(__riscv_float_abi_single)
- fsw f0, 31*4(sp) // Store ft0
- fsw f1, 32*4(sp) // Store ft1
- fsw f2, 33*4(sp) // Store ft2
- fsw f3, 34*4(sp) // Store ft3
- fsw f4, 35*4(sp) // Store ft4
- fsw f5, 36*4(sp) // Store ft5
- fsw f6, 37*4(sp) // Store ft6
- fsw f7, 38*4(sp) // Store ft7
- fsw f10, 41*4(sp) // Store fa0
- fsw f11, 42*4(sp) // Store fa1
- fsw f12, 43*4(sp) // Store fa2
- fsw f13, 44*4(sp) // Store fa3
- fsw f14, 45*4(sp) // Store fa4
- fsw f15, 46*4(sp) // Store fa5
- fsw f16, 47*4(sp) // Store fa6
- fsw f17, 48*4(sp) // Store fa7
- fsw f28, 59*4(sp) // Store ft8
- fsw f29, 60*4(sp) // Store ft9
- fsw f30, 61*4(sp) // Store ft10
- fsw f31, 62*4(sp) // Store ft11
- csrr t0, fcsr
- sw t0, 63*4(sp) // Store fcsr
-#elif defined(__riscv_float_abi_double)
- fsd f0, 31*4(sp) // Store ft0
- fsd f1, 32*4(sp) // Store ft1
- fsd f2, 33*4(sp) // Store ft2
- fsd f3, 34*4(sp) // Store ft3
- fsd f4, 35*4(sp) // Store ft4
- fsd f5, 36*4(sp) // Store ft5
- fsd f6, 37*4(sp) // Store ft6
- fsd f7, 38*4(sp) // Store ft7
- fsd f10, 41*4(sp) // Store fa0
- fsd f11, 42*4(sp) // Store fa1
- fsd f12, 43*4(sp) // Store fa2
- fsd f13, 44*4(sp) // Store fa3
- fsd f14, 45*4(sp) // Store fa4
- fsd f15, 46*4(sp) // Store fa5
- fsd f16, 47*4(sp) // Store fa6
- fsd f17, 48*4(sp) // Store fa7
- fsd f28, 59*4(sp) // Store ft8
- fsd f29, 60*4(sp) // Store ft9
- fsd f30, 61*4(sp) // Store ft10
- fsd f31, 62*4(sp) // Store ft11
+ /* Save floating point registers (doubles at 128 + i*8). */
+ fsd f0, 16*8(sp) // Store ft0
+ fsd f1, 17*8(sp) // Store ft1
+ fsd f2, 18*8(sp) // Store ft2
+ fsd f3, 19*8(sp) // Store ft3
+ fsd f4, 20*8(sp) // Store ft4
+ fsd f5, 21*8(sp) // Store ft5
+ fsd f6, 22*8(sp) // Store ft6
+ fsd f7, 23*8(sp) // Store ft7
+ fsd f10, 26*8(sp) // Store fa0
+ fsd f11, 27*8(sp) // Store fa1
+ fsd f12, 28*8(sp) // Store fa2
+ fsd f13, 29*8(sp) // Store fa3
+ fsd f14, 30*8(sp) // Store fa4
+ fsd f15, 31*8(sp) // Store fa5
+ fsd f16, 32*8(sp) // Store fa6
+ fsd f17, 33*8(sp) // Store fa7
+ fsd f28, 44*8(sp) // Store ft8
+ fsd f29, 45*8(sp) // Store ft9
+ fsd f30, 46*8(sp) // Store ft10
+ fsd f31, 47*8(sp) // Store ft11
csrr t0, fcsr
- sw t0, 63*4(sp) // Store fcsr
+ sw t0, 96*4(sp) // Store fcsr
#endif
_tx_thread_skip_nested_fpu_save:
@@ -261,7 +221,11 @@ _tx_thread_skip_nested_fpu_save:
/* Call the ISR execution exit function if enabled. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+ addi sp, sp, -16 // Reserve space to save the return address
+ sw ra, 0(sp) // Save the return address
call _tx_execution_isr_enter // Call the ISR execution enter function
+ lw ra, 0(sp) // Recover the return address
+ addi sp, sp, 16 // Recover the reserved stack space
#endif
ret // Return to ISR
@@ -270,16 +234,16 @@ _tx_thread_idle_system_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+ addi sp, sp, -16 // Reserve space to save the return address
+ sw ra, 0(sp) // Save the return address
call _tx_execution_isr_enter // Call the ISR execution enter function
+ lw ra, 0(sp) // Recover the return address
+ addi sp, sp, 16 // Recover the reserved stack space
#endif
/* Interrupt occurred in the scheduling loop. */
/* }
} */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
-#else
- addi sp, sp, 32*4 // Recover the reserved stack space
-#endif
+ addi sp, sp, TX_TRAP_FRAME_SIZE // Recover the reserved stack space
ret // Return to calling ISR
diff --git a/ports/risc-v32/gnu/src/tx_thread_schedule.S b/ports/risc-v32/gnu/src/tx_thread_schedule.S
index 79bfd51a..7d2c4191 100644
--- a/ports/risc-v32/gnu/src/tx_thread_schedule.S
+++ b/ports/risc-v32/gnu/src/tx_thread_schedule.S
@@ -21,6 +21,11 @@
.section .text
+
+#include "tx_port.h"
+ .equ TX_TRAP_FRAME_SIZE, TX_RISCV_TRAP_FRAME_SIZE
+ .equ TX_SOL_FRAME_SIZE, TX_RISCV_SOL_FRAME_SIZE
+
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -130,86 +135,49 @@ _tx_thread_ready_to_run:
/* if (*sp)
{ */
- lw t0, 0(sp) // Pickup stack type
+ lw t0, 0*4(sp) // Pickup stack type
beqz t0, _tx_thread_solicited_return // If 0, solicited return
/* Recover floating point registers only if saved mstatus.FS was not Off. */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
lw t1, 29*4(sp) // Pickup saved mstatus
srli t1, t1, 13
andi t1, t1, 0x3
beqz t1, _tx_thread_schedule_skip_fp_restore // Skip if FS was Off
-#if defined(__riscv_float_abi_single)
- flw f0, 31*4(sp) // Recover ft0
- flw f1, 32*4(sp) // Recover ft1
- flw f2, 33*4(sp) // Recover ft2
- flw f3, 34*4(sp) // Recover ft3
- flw f4, 35*4(sp) // Recover ft4
- flw f5, 36*4(sp) // Recover ft5
- flw f6, 37*4(sp) // Recover ft6
- flw f7, 38*4(sp) // Recover ft7
- flw f8, 39*4(sp) // Recover fs0
- flw f9, 40*4(sp) // Recover fs1
- flw f10, 41*4(sp) // Recover fa0
- flw f11, 42*4(sp) // Recover fa1
- flw f12, 43*4(sp) // Recover fa2
- flw f13, 44*4(sp) // Recover fa3
- flw f14, 45*4(sp) // Recover fa4
- flw f15, 46*4(sp) // Recover fa5
- flw f16, 47*4(sp) // Recover fa6
- flw f17, 48*4(sp) // Recover fa7
- flw f18, 49*4(sp) // Recover fs2
- flw f19, 50*4(sp) // Recover fs3
- flw f20, 51*4(sp) // Recover fs4
- flw f21, 52*4(sp) // Recover fs5
- flw f22, 53*4(sp) // Recover fs6
- flw f23, 54*4(sp) // Recover fs7
- flw f24, 55*4(sp) // Recover fs8
- flw f25, 56*4(sp) // Recover fs9
- flw f26, 57*4(sp) // Recover fs10
- flw f27, 58*4(sp) // Recover fs11
- flw f28, 59*4(sp) // Recover ft8
- flw f29, 60*4(sp) // Recover ft9
- flw f30, 61*4(sp) // Recover ft10
- flw f31, 62*4(sp) // Recover ft11
- lw t0, 63*4(sp) // Recover fcsr
+ fld f0, 16*8(sp) // Recover ft0
+ fld f1, 17*8(sp) // Recover ft1
+ fld f2, 18*8(sp) // Recover ft2
+ fld f3, 19*8(sp) // Recover ft3
+ fld f4, 20*8(sp) // Recover ft4
+ fld f5, 21*8(sp) // Recover ft5
+ fld f6, 22*8(sp) // Recover ft6
+ fld f7, 23*8(sp) // Recover ft7
+ fld f8, 24*8(sp) // Recover fs0
+ fld f9, 25*8(sp) // Recover fs1
+ fld f10, 26*8(sp) // Recover fa0
+ fld f11, 27*8(sp) // Recover fa1
+ fld f12, 28*8(sp) // Recover fa2
+ fld f13, 29*8(sp) // Recover fa3
+ fld f14, 30*8(sp) // Recover fa4
+ fld f15, 31*8(sp) // Recover fa5
+ fld f16, 32*8(sp) // Recover fa6
+ fld f17, 33*8(sp) // Recover fa7
+ fld f18, 34*8(sp) // Recover fs2
+ fld f19, 35*8(sp) // Recover fs3
+ fld f20, 36*8(sp) // Recover fs4
+ fld f21, 37*8(sp) // Recover fs5
+ fld f22, 38*8(sp) // Recover fs6
+ fld f23, 39*8(sp) // Recover fs7
+ fld f24, 40*8(sp) // Recover fs8
+ fld f25, 41*8(sp) // Recover fs9
+ fld f26, 42*8(sp) // Recover fs10
+ fld f27, 43*8(sp) // Recover fs11
+ fld f28, 44*8(sp) // Recover ft8
+ fld f29, 45*8(sp) // Recover ft9
+ fld f30, 46*8(sp) // Recover ft10
+ fld f31, 47*8(sp) // Recover ft11
+ lw t0, 96*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
-#elif defined(__riscv_float_abi_double)
- fld f0, 31*4(sp) // Recover ft0
- fld f1, 32*4(sp) // Recover ft1
- fld f2, 33*4(sp) // Recover ft2
- fld f3, 34*4(sp) // Recover ft3
- fld f4, 35*4(sp) // Recover ft4
- fld f5, 36*4(sp) // Recover ft5
- fld f6, 37*4(sp) // Recover ft6
- fld f7, 38*4(sp) // Recover ft7
- fld f8, 39*4(sp) // Recover fs0
- fld f9, 40*4(sp) // Recover fs1
- fld f10, 41*4(sp) // Recover fa0
- fld f11, 42*4(sp) // Recover fa1
- fld f12, 43*4(sp) // Recover fa2
- fld f13, 44*4(sp) // Recover fa3
- fld f14, 45*4(sp) // Recover fa4
- fld f15, 46*4(sp) // Recover fa5
- fld f16, 47*4(sp) // Recover fa6
- fld f17, 48*4(sp) // Recover fa7
- fld f18, 49*4(sp) // Recover fs2
- fld f19, 50*4(sp) // Recover fs3
- fld f20, 51*4(sp) // Recover fs4
- fld f21, 52*4(sp) // Recover fs5
- fld f22, 53*4(sp) // Recover fs6
- fld f23, 54*4(sp) // Recover fs7
- fld f24, 55*4(sp) // Recover fs8
- fld f25, 56*4(sp) // Recover fs9
- fld f26, 57*4(sp) // Recover fs10
- fld f27, 58*4(sp) // Recover fs11
- fld f28, 59*4(sp) // Recover ft8
- fld f29, 60*4(sp) // Recover ft9
- fld f30, 61*4(sp) // Recover ft10
- fld f31, 62*4(sp) // Recover ft11
- lw t0, 63*4(sp) // Recover fcsr
- csrw fcsr, t0 // Restore fcsr
-#endif
_tx_thread_schedule_skip_fp_restore:
#endif
@@ -218,7 +186,7 @@ _tx_thread_schedule_skip_fp_restore:
csrw mepc, t0 // Setup mepc
li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80)
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
li t1, 0x2000 // Set FS bits for FP state
or t0, t0, t1
#endif
@@ -253,52 +221,31 @@ _tx_thread_schedule_skip_fp_restore:
lw x26, 2*4(sp) // Recover s10
lw x27, 1*4(sp) // Recover s11
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
-#else
- addi sp, sp, 32*4 // Recover stack frame - without floating point enabled
-#endif
+ addi sp, sp, TX_TRAP_FRAME_SIZE // Recover stack frame
mret // Return to thread
_tx_thread_solicited_return:
/* Recover floating point registers only if saved mstatus.FS was not Off. */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
lw t1, 14*4(sp) // Pickup saved mstatus
srli t1, t1, 13
andi t1, t1, 0x3
beqz t1, _tx_thread_schedule_solicited_skip_fp_restore // Skip if FS was Off
-#if defined(__riscv_float_abi_single)
- flw f8, 15*4(sp) // Recover fs0
- flw f9, 16*4(sp) // Recover fs1
- flw f18, 17*4(sp) // Recover fs2
- flw f19, 18*4(sp) // Recover fs3
- flw f20, 19*4(sp) // Recover fs4
- flw f21, 20*4(sp) // Recover fs5
- flw f22, 21*4(sp) // Recover fs6
- flw f23, 22*4(sp) // Recover fs7
- flw f24, 23*4(sp) // Recover fs8
- flw f25, 24*4(sp) // Recover fs9
- flw f26, 25*4(sp) // Recover fs10
- flw f27, 26*4(sp) // Recover fs11
- lw t0, 27*4(sp) // Recover fcsr
- csrw fcsr, t0 // Restore fcsr
-#elif defined(__riscv_float_abi_double)
- fld f8, 15*4(sp) // Recover fs0
- fld f9, 16*4(sp) // Recover fs1
- fld f18, 17*4(sp) // Recover fs2
- fld f19, 18*4(sp) // Recover fs3
- fld f20, 19*4(sp) // Recover fs4
- fld f21, 20*4(sp) // Recover fs5
- fld f22, 21*4(sp) // Recover fs6
- fld f23, 22*4(sp) // Recover fs7
- fld f24, 23*4(sp) // Recover fs8
- fld f25, 24*4(sp) // Recover fs9
- fld f26, 25*4(sp) // Recover fs10
- fld f27, 26*4(sp) // Recover fs11
- lw t0, 27*4(sp) // Recover fcsr
+ fld f8, 8*8(sp) // Recover fs0
+ fld f9, 9*8(sp) // Recover fs1
+ fld f18, 10*8(sp) // Recover fs2
+ fld f19, 11*8(sp) // Recover fs3
+ fld f20, 12*8(sp) // Recover fs4
+ fld f21, 13*8(sp) // Recover fs5
+ fld f22, 14*8(sp) // Recover fs6
+ fld f23, 15*8(sp) // Recover fs7
+ fld f24, 16*8(sp) // Recover fs8
+ fld f25, 17*8(sp) // Recover fs9
+ fld f26, 18*8(sp) // Recover fs10
+ fld f27, 19*8(sp) // Recover fs11
+ lw t0, 40*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
-#endif
_tx_thread_schedule_solicited_skip_fp_restore:
#endif
@@ -320,11 +267,7 @@ _tx_thread_schedule_solicited_skip_fp_restore:
lw x26, 2*4(sp) // Recover s10
lw x27, 1*4(sp) // Recover s11
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- addi sp, sp, 29*4 // Recover stack frame - with floating point enabled
-#else
- addi sp, sp, 16*4 // Recover stack frame - without floating point enabled
-#endif
+ addi sp, sp, TX_SOL_FRAME_SIZE // Recover stack frame
ret // Return to thread
/* } */
diff --git a/ports/risc-v32/gnu/src/tx_thread_stack_build.S b/ports/risc-v32/gnu/src/tx_thread_stack_build.S
index 4ade60ca..3f7ae5d6 100644
--- a/ports/risc-v32/gnu/src/tx_thread_stack_build.S
+++ b/ports/risc-v32/gnu/src/tx_thread_stack_build.S
@@ -21,6 +21,10 @@
.section .text
+
+#include "tx_port.h"
+ .equ TX_TRAP_FRAME_SIZE, TX_RISCV_TRAP_FRAME_SIZE
+
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -92,42 +96,14 @@ _tx_thread_stack_build:
x11 26 Initial a1
x10 27 Initial a0
x1 28 Initial ra
- -- 29 reserved
+ mstatus 29 Initial mstatus seed
mepc 30 Initial mepc
-If floating point support:
- f0 31 Initial ft0
- f1 32 Initial ft1
- f2 33 Initial ft2
- f3 34 Initial ft3
- f4 35 Initial ft4
- f5 36 Initial ft5
- f6 37 Initial ft6
- f7 38 Initial ft7
- f8 39 Initial fs0
- f9 40 Initial fs1
- f10 41 Initial fa0
- f11 42 Initial fa1
- f12 43 Initial fa2
- f13 44 Initial fa3
- f14 45 Initial fa4
- f15 46 Initial fa5
- f16 47 Initial fa6
- f17 48 Initial fa7
- f18 49 Initial fs2
- f19 50 Initial fs3
- f20 51 Initial fs4
- f21 52 Initial fs5
- f22 53 Initial fs6
- f23 54 Initial fs7
- f24 55 Initial fs8
- f25 56 Initial fs9
- f26 57 Initial fs10
- f27 58 Initial fs11
- f28 59 Initial ft8
- f29 60 Initial ft9
- f30 61 Initial ft10
- f31 62 Initial ft11
- fscr 63 Initial fscr
+ -- 31 pad (0)
+ If floating point support (double ABI), byte offsets from
+ the frame base:
+ f0-f31 128 + i*8 Initial FP registers (all 0)
+ fcsr 384 Initial fcsr (0)
+ pad 388-399 (0)
Stack Bottom: (higher memory address) */
@@ -137,11 +113,7 @@ If floating point support:
/* Actually build the stack frame. */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- addi t0, t0, -65*4
-#else
- addi t0, t0, -32*4 // Allocate space for the stack frame
-#endif
+ addi t0, t0, -TX_TRAP_FRAME_SIZE // Allocate space for the stack frame
li t1, 1 // Build stack type
sw t1, 0*4(t0) // Place stack type on the top
sw zero, 1*4(t0) // Initial s11
@@ -173,44 +145,22 @@ If floating point support:
sw zero, 27*4(t0) // Initial a0
sw zero, 28*4(t0) // Initial ra
sw a1, 30*4(t0) // Initial mepc (thread entry point)
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- sw zero, 31*4(t0) // Initial ft0
- sw zero, 32*4(t0) // Initial ft1
- sw zero, 33*4(t0) // Initial ft2
- sw zero, 34*4(t0) // Initial ft3
- sw zero, 35*4(t0) // Initial ft4
- sw zero, 36*4(t0) // Initial ft5
- sw zero, 37*4(t0) // Initial ft6
- sw zero, 38*4(t0) // Initial ft7
- sw zero, 39*4(t0) // Initial fs0
- sw zero, 40*4(t0) // Initial fs1
- sw zero, 41*4(t0) // Initial fa0
- sw zero, 42*4(t0) // Initial fa1
- sw zero, 43*4(t0) // Initial fa2
- sw zero, 44*4(t0) // Initial fa3
- sw zero, 45*4(t0) // Initial fa4
- sw zero, 46*4(t0) // Initial fa5
- sw zero, 47*4(t0) // Initial fa6
- sw zero, 48*4(t0) // Initial fa7
- sw zero, 49*4(t0) // Initial fs2
- sw zero, 50*4(t0) // Initial fs3
- sw zero, 51*4(t0) // Initial fs4
- sw zero, 52*4(t0) // Initial fs5
- sw zero, 53*4(t0) // Initial fs6
- sw zero, 54*4(t0) // Initial fs7
- sw zero, 55*4(t0) // Initial fs8
- sw zero, 56*4(t0) // Initial fs9
- sw zero, 57*4(t0) // Initial fs10
- sw zero, 58*4(t0) // Initial fs11
- sw zero, 59*4(t0) // Initial ft8
- sw zero, 60*4(t0) // Initial ft9
- sw zero, 61*4(t0) // Initial ft10
- sw zero, 62*4(t0) // Initial ft11
- csrr a1, fcsr // Read fcsr for initial value
- sw a1, 63*4(t0) // Initial fcsr
- sw zero, 64*4(t0) // Reserved word (0)
+ sw zero, 31*4(t0) // Pad word (0)
+#if defined(__riscv_float_abi_double)
+ li t1, 0x6000 // mstatus seed: FS = Dirty (bits 14:13 = 11)
+ sw t1, 29*4(t0) // so the first dispatch restores the clean FP state
+
+ /* Zero the whole FP area: f0-f31 double slots (128-383), fcsr (384)
+ and the pad words up to the frame end. Threads start with clean
+ FP registers and fcsr = 0. */
+ addi t1, t0, 32*4 // First FP-area word (offset 128)
+ addi t2, t0, TX_TRAP_FRAME_SIZE // One past the frame end (offset 400)
+_tx_thread_stack_build_fp_zero:
+ sw zero, 0(t1) // Clear FP-area word
+ addi t1, t1, 4
+ bne t1, t2, _tx_thread_stack_build_fp_zero
#else
- sw zero, 31*4(t0) // Reserved word (0)
+ sw zero, 29*4(t0) // Initial mstatus slot (0, no FP gate)
#endif
/* Setup stack pointer. */
diff --git a/ports/risc-v32/gnu/src/tx_thread_system_return.S b/ports/risc-v32/gnu/src/tx_thread_system_return.S
index 20ff25f2..2e49bc3f 100644
--- a/ports/risc-v32/gnu/src/tx_thread_system_return.S
+++ b/ports/risc-v32/gnu/src/tx_thread_system_return.S
@@ -21,6 +21,10 @@
.section .text
+
+#include "tx_port.h"
+ .equ TX_SOL_FRAME_SIZE, TX_RISCV_SOL_FRAME_SIZE
+
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -63,54 +67,33 @@ _tx_thread_system_return:
/* Save minimal context on the stack. */
/* sp -= sizeof(stack_frame); */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- addi sp, sp, -29*4 // Allocate space on the stack - with floating point enabled
-#else
- addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled
-#endif
+ addi sp, sp, -TX_SOL_FRAME_SIZE // Allocate the solicited stack frame
- sw zero, 0(sp) // Solicited stack type (store early so slot is always written)
+ sw zero, 0*4(sp) // Solicited stack type (store early so slot is always written)
/* Read and save mstatus first; use it to guard FP register save. */
csrr t0, mstatus // Pickup current mstatus
sw t0, 14*4(sp) // Save mstatus
/* Store floating point preserved registers — only if FS != Off. */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
srli t1, t0, 13 // Shift FS field to bits [1:0]
andi t1, t1, 0x3 // Isolate FS bits
beqz t1, _tx_thread_system_return_skip_fp // Skip FP save if FS == Off
-#if defined(__riscv_float_abi_single)
- fsw f8, 15*4(sp) // Store fs0
- fsw f9, 16*4(sp) // Store fs1
- fsw f18, 17*4(sp) // Store fs2
- fsw f19, 18*4(sp) // Store fs3
- fsw f20, 19*4(sp) // Store fs4
- fsw f21, 20*4(sp) // Store fs5
- fsw f22, 21*4(sp) // Store fs6
- fsw f23, 22*4(sp) // Store fs7
- fsw f24, 23*4(sp) // Store fs8
- fsw f25, 24*4(sp) // Store fs9
- fsw f26, 25*4(sp) // Store fs10
- fsw f27, 26*4(sp) // Store fs11
+ fsd f8, 8*8(sp) // Store fs0
+ fsd f9, 9*8(sp) // Store fs1
+ fsd f18, 10*8(sp) // Store fs2
+ fsd f19, 11*8(sp) // Store fs3
+ fsd f20, 12*8(sp) // Store fs4
+ fsd f21, 13*8(sp) // Store fs5
+ fsd f22, 14*8(sp) // Store fs6
+ fsd f23, 15*8(sp) // Store fs7
+ fsd f24, 16*8(sp) // Store fs8
+ fsd f25, 17*8(sp) // Store fs9
+ fsd f26, 18*8(sp) // Store fs10
+ fsd f27, 19*8(sp) // Store fs11
csrr t0, fcsr
- sw t0, 27*4(sp) // Store fcsr
-#elif defined(__riscv_float_abi_double)
- fsd f8, 15*4(sp) // Store fs0
- fsd f9, 16*4(sp) // Store fs1
- fsd f18, 17*4(sp) // Store fs2
- fsd f19, 18*4(sp) // Store fs3
- fsd f20, 19*4(sp) // Store fs4
- fsd f21, 20*4(sp) // Store fs5
- fsd f22, 21*4(sp) // Store fs6
- fsd f23, 22*4(sp) // Store fs7
- fsd f24, 23*4(sp) // Store fs8
- fsd f25, 24*4(sp) // Store fs9
- fsd f26, 25*4(sp) // Store fs10
- fsd f27, 26*4(sp) // Store fs11
- csrr t0, fcsr
- sw t0, 27*4(sp) // Store fcsr
-#endif
+ sw t0, 40*4(sp) // Store fcsr
_tx_thread_system_return_skip_fp:
#endif
diff --git a/ports/risc-v32/gnu/src/tx_timer_interrupt.S b/ports/risc-v32/gnu/src/tx_timer_interrupt.S
index d3b2fc60..8b5d7df3 100644
--- a/ports/risc-v32/gnu/src/tx_timer_interrupt.S
+++ b/ports/risc-v32/gnu/src/tx_timer_interrupt.S
@@ -88,7 +88,7 @@ _tx_timer_interrupt:
/* Check for expiration. */
/* if (_tx_timer_time_slice == 0) */
- bgtz t3, _tx_timer_no_time_slice // If not 0, has not expired yet
+ bnez t3, _tx_timer_no_time_slice // If not 0, has not expired yet
li t1, 1 // Build expired flag
/* Set the time-slice expired flag. */
@@ -181,7 +181,7 @@ _tx_timer_dont_activate:
/* if (_tx_timer_expired_time_slice)
{ */
- andi t2, t6, 1 // Is the timer expired bit set?
+ andi t2, t6, 1 // Is the time-slice expired bit set?
beqz t2, _tx_timer_not_ts_expiration // If not, skip time slice processing
/* Time slice interrupted thread. */
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-23 21:10:57 +0000