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| author | Tiejun Zhou <[email protected]> | 2023-03-08 08:26:22 +0000 |
|---|---|---|
| committer | Tiejun Zhou <[email protected]> | 2023-03-08 08:26:22 +0000 |
| commit | 2aa19f3de0b6cf09bb9dca78c8a53fe337b8f0f7 (patch) | |
| tree | 8ec91a64e0831e3100a6ad9a5dec41d9fd7fc74f /ports/risc-v64/gnu/src/tx_initialize_low_level.S | |
| parent | 745395d6a2f931c85c4428425db21eb7d03b4324 (diff) | |
Release 6.2.1 on 08 Mar 2023. Expand to see details.v6.2.1_rel
cee19603d Include tx_user.h conditionally.
e40e08007 Update owners
d69641273 Update release date and version
394aee52f Add tx_user.h to GNU port assembly files
5cca2ddd0 RISC-V 64 bit port for Microchip
e0f2c373c Link Winmm.lib that required by the high-resolution timer.
6af472a68 Update Win32 port with high resolution timer.
aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler
19091a262 Add .section .preamble to m3 m4 m7 module ports
ced60e1b7 Add missing parenthesis in ports assembly file
309dc77ca Modules Cortex-A7 IAR new port
c752a4063 Modules Cortex-A7 GNU new port
dc224b90f Fix race condition in tx_thread_wait_abort and update regression test
6e261f5b7 create threadx cmsis-pack
Diffstat (limited to 'ports/risc-v64/gnu/src/tx_initialize_low_level.S')
| -rw-r--r-- | ports/risc-v64/gnu/src/tx_initialize_low_level.S | 111 |
1 files changed, 111 insertions, 0 deletions
diff --git a/ports/risc-v64/gnu/src/tx_initialize_low_level.S b/ports/risc-v64/gnu/src/tx_initialize_low_level.S new file mode 100644 index 00000000..d99ec144 --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_initialize_low_level.S @@ -0,0 +1,111 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .data + .global __tx_free_memory_start +__tx_free_memory_start: + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level +_tx_initialize_low_level: + sd sp, _tx_thread_system_stack_ptr, t0 // Save system stack pointer + + la t0, __tx_free_memory_start // Pickup first free address + sd t0, _tx_initialize_unused_memory, t1 // Save unused memory address + +#ifdef __riscv_flen + fscsr x0 +#endif + + ret + + + /* Define the actual timer interrupt/exception handler. */ + + .global timer1_plic_IRQHandler + //.global __minterrupt_000007 + //EXTWEAK __require_minterrupt_vector_table +timer1_plic_IRQHandler: +//__minterrupt_000007: + //REQUIRE __require_minterrupt_vector_table + + + /* Before calling _tx_thread_context_save, we have to allocate an interrupt + stack frame and save the current value of x1 (ra). */ +//#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) +// addi sp, sp, -520 // Allocate space for all registers - with floating point enabled +//#else +// addi sp, sp, -256 // Allocate space for all registers - without floating point enabled +//#endif +// sd x1, 224(sp) // Store RA +// call _tx_thread_context_save // Call ThreadX context save + + /* Call the ThreadX timer routine. */ + call _tx_timer_interrupt // Call timer interrupt handler + call timer1_interrupt + ret + /* Timer interrupt processing is done, jump to ThreadX context restore. */ +// j _tx_thread_context_restore // Jump to ThreadX context restore function. Note: this does not return! |