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| author | Frédéric Desbiens <[email protected]> | 2026-10-02 10:42:44 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-10-02 10:42:44 -0400 |
| commit | 93387b0a60382a29579bbad5045c68328e3751df (patch) | |
| tree | 42be790d602cb76f55090e5a7c418df7ea2b3428 /ports/risc-v64/gnu/src/tx_initialize_low_level.S | |
| parent | 44d7c95c582d415c4ad84527180b29c93c3bf664 (diff) | |
| parent | 28281cd5647d4671236ca08d19bd18ed15b2265a (diff) | |
Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel
Merged changes ahead of the v6.5.2.202603 release
Diffstat (limited to 'ports/risc-v64/gnu/src/tx_initialize_low_level.S')
| -rw-r--r-- | ports/risc-v64/gnu/src/tx_initialize_low_level.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/ports/risc-v64/gnu/src/tx_initialize_low_level.S b/ports/risc-v64/gnu/src/tx_initialize_low_level.S index 6a35272f..952be957 100644 --- a/ports/risc-v64/gnu/src/tx_initialize_low_level.S +++ b/ports/risc-v64/gnu/src/tx_initialize_low_level.S @@ -79,10 +79,26 @@ _tx_initialize_low_level: /* Initialize floating point control/status register if floating point is enabled. */ #ifdef __riscv_flen +#ifdef TX_RISCV_SMODE + li t0, 0x2000 // Set sstatus.FS to Initial (bits 14:13 = 01) so the fcsr write cannot trap + csrrs zero, sstatus, t0 +#else + li t0, 0x2000 // Set mstatus.FS to Initial (bits 14:13 = 01) so the fcsr write cannot trap + csrrs zero, mstatus, t0 +#endif li t0, 0 csrw fcsr, t0 // Clear FP control/status register #endif +#ifdef __riscv_vector + li t0, 0x200 // Set VS=Initial before a vector restore +#ifdef TX_RISCV_SMODE + csrrs zero, sstatus, t0 +#else + csrrs zero, mstatus, t0 +#endif +#endif + ret /* Timer Interrupt Handler Note: |