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authorFrédéric Desbiens <[email protected]>2026-03-06 19:27:49 +0100
committerGitHub <[email protected]>2026-03-06 19:27:49 +0100
commit3726d7906b4808bfec7855fc088e073199df9120 (patch)
tree8789bfd03d1d49e1967e80d04aa4ff606fda43eb /ports/risc-v64/gnu/src/tx_thread_context_save.S
parent4b6e8100d932a3a67b34c6eb17f84f3bffb9e2ae (diff)
parentc3259a216026372e3833dd8996a68f77e8595fbd (diff)
Merge pull request #510 from eclipse-threadx/devv6.5.0.202601_rel
Merge changes ahead of the v6.5.0.202601 release
Diffstat (limited to 'ports/risc-v64/gnu/src/tx_thread_context_save.S')
-rw-r--r--ports/risc-v64/gnu/src/tx_thread_context_save.S293
1 files changed, 144 insertions, 149 deletions
diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S
index a1f2a9b6..df6f2c9a 100644
--- a/ports/risc-v64/gnu/src/tx_thread_context_save.S
+++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S
@@ -1,10 +1,11 @@
/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- *
+ * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (c) 2026-present Eclipse ThreadX contributors
+ *
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
- *
+ *
* SPDX-License-Identifier: MIT
**************************************************************************/
@@ -19,8 +20,6 @@
/**************************************************************************/
/**************************************************************************/
-#include "tx_port.h"
-
.section .text
/**************************************************************************/
/* */
@@ -54,12 +53,6 @@
/* */
/* ISRs */
/* */
-/* RELEASE HISTORY */
-/* */
-/* DATE NAME DESCRIPTION */
-/* */
-/* 03-08-2023 Scott Larson Initial Version 6.2.1 */
-/* */
/**************************************************************************/
/* VOID _tx_thread_context_save(VOID)
{ */
@@ -67,90 +60,90 @@
_tx_thread_context_save:
/* Upon entry to this routine, it is assumed that interrupts are locked
- out and the interrupt stack fame has been allocated and x1 (ra) has
+ out and the interrupt stack frame has been allocated and ra has
been saved on the stack. */
- STORE x5, 19*REGBYTES(sp) // First store t0 and t1
- STORE x6, 18*REGBYTES(sp)
+ sd t0, 19*8(sp) // First store t0 and t1
+ sd t1, 18*8(sp)
- la x5, _tx_thread_system_state // Pickup address of system state
- LOAD x6, 0(x5) // Pickup system state
+ la t0, _tx_thread_system_state // Pickup address of system state
+ ld t1, 0(t0) // Pickup system state
/* Check for a nested interrupt condition. */
/* if (_tx_thread_system_state++)
{ */
- beqz x6, _tx_thread_not_nested_save // If 0, first interrupt condition
- addi x6, x6, 1 // Increment the interrupt counter
- STORE x6, 0(x5) // Store the interrupt counter
+ beqz t1, _tx_thread_not_nested_save // If 0, first interrupt condition
+ addi t1, t1, 1 // Increment the interrupt counter
+ sd t1, 0(t0) // Store the interrupt counter
/* Nested interrupt condition.
- Save the reset of the scratch registers on the stack and return to the
+ Save the rest of the scratch registers on the stack and return to the
calling ISR. */
- STORE x7, 17*REGBYTES(sp) // Store t2
- STORE x8, 12*REGBYTES(sp) // Store s0
- STORE x10, 27*REGBYTES(sp) // Store a0
- STORE x11, 26*REGBYTES(sp) // Store a1
- STORE x12, 25*REGBYTES(sp) // Store a2
- STORE x13, 24*REGBYTES(sp) // Store a3
- STORE x14, 23*REGBYTES(sp) // Store a4
- STORE x15, 22*REGBYTES(sp) // Store a5
- STORE x16, 21*REGBYTES(sp) // Store a6
- STORE x17, 20*REGBYTES(sp) // Store a7
- STORE x28, 16*REGBYTES(sp) // Store t3
- STORE x29, 15*REGBYTES(sp) // Store t4
- STORE x30, 14*REGBYTES(sp) // Store t5
- STORE x31, 13*REGBYTES(sp) // Store t6
+ sd t2, 17*8(sp) // Store t2
+ sd s0, 12*8(sp) // Store s0
+ sd a0, 27*8(sp) // Store a0
+ sd a1, 26*8(sp) // Store a1
+ sd a2, 25*8(sp) // Store a2
+ sd a3, 24*8(sp) // Store a3
+ sd a4, 23*8(sp) // Store a4
+ sd a5, 22*8(sp) // Store a5
+ sd a6, 21*8(sp) // Store a6
+ sd a7, 20*8(sp) // Store a7
+ sd t3, 16*8(sp) // Store t3
+ sd t4, 15*8(sp) // Store t4
+ sd t5, 14*8(sp) // Store t5
+ sd t6, 13*8(sp) // Store t6
csrr t0, mepc // Load exception program counter
- STORE t0, 30*REGBYTES(sp) // Save it on the stack
+ sd t0, 30*8(sp) // Save it on the stack
- /* Save floating point scratch registers. */
-#if defined(__riscv_float_abi_single)
- fsw f0, 31*REGBYTES(sp) // Store ft0
- fsw f1, 32*REGBYTES(sp) // Store ft1
- fsw f2, 33*REGBYTES(sp) // Store ft2
- fsw f3, 34*REGBYTES(sp) // Store ft3
- fsw f4, 35*REGBYTES(sp) // Store ft4
- fsw f5, 36*REGBYTES(sp) // Store ft5
- fsw f6, 37*REGBYTES(sp) // Store ft6
- fsw f7, 38*REGBYTES(sp) // Store ft7
- fsw f10,41*REGBYTES(sp) // Store fa0
- fsw f11,42*REGBYTES(sp) // Store fa1
- fsw f12,43*REGBYTES(sp) // Store fa2
- fsw f13,44*REGBYTES(sp) // Store fa3
- fsw f14,45*REGBYTES(sp) // Store fa4
- fsw f15,46*REGBYTES(sp) // Store fa5
- fsw f16,47*REGBYTES(sp) // Store fa6
- fsw f17,48*REGBYTES(sp) // Store fa7
- fsw f28,59*REGBYTES(sp) // Store ft8
- fsw f29,60*REGBYTES(sp) // Store ft9
- fsw f30,61*REGBYTES(sp) // Store ft10
- fsw f31,62*REGBYTES(sp) // Store ft11
+ /* Save floating point scratch registers if floating point is enabled. */
+#ifdef __riscv_float_abi_single
+ fsw f0, 31*8(sp) // Store ft0
+ fsw f1, 32*8(sp) // Store ft1
+ fsw f2, 33*8(sp) // Store ft2
+ fsw f3, 34*8(sp) // Store ft3
+ fsw f4, 35*8(sp) // Store ft4
+ fsw f5, 36*8(sp) // Store ft5
+ fsw f6, 37*8(sp) // Store ft6
+ fsw f7, 38*8(sp) // Store ft7
+ fsw f10,41*8(sp) // Store fa0
+ fsw f11,42*8(sp) // Store fa1
+ fsw f12,43*8(sp) // Store fa2
+ fsw f13,44*8(sp) // Store fa3
+ fsw f14,45*8(sp) // Store fa4
+ fsw f15,46*8(sp) // Store fa5
+ fsw f16,47*8(sp) // Store fa6
+ fsw f17,48*8(sp) // Store fa7
+ fsw f28,59*8(sp) // Store ft8
+ fsw f29,60*8(sp) // Store ft9
+ fsw f30,61*8(sp) // Store ft10
+ fsw f31,62*8(sp) // Store ft11
csrr t0, fcsr
- STORE t0, 63*REGBYTES(sp) // Store fcsr
+ sd t0, 63*8(sp) // Store fcsr
#elif defined(__riscv_float_abi_double)
- fsd f0, 31*REGBYTES(sp) // Store ft0
- fsd f1, 32*REGBYTES(sp) // Store ft1
- fsd f2, 33*REGBYTES(sp) // Store ft2
- fsd f3, 34*REGBYTES(sp) // Store ft3
- fsd f4, 35*REGBYTES(sp) // Store ft4
- fsd f5, 36*REGBYTES(sp) // Store ft5
- fsd f6, 37*REGBYTES(sp) // Store ft6
- fsd f7, 38*REGBYTES(sp) // Store ft7
- fsd f10,41*REGBYTES(sp) // Store fa0
- fsd f11,42*REGBYTES(sp) // Store fa1
- fsd f12,43*REGBYTES(sp) // Store fa2
- fsd f13,44*REGBYTES(sp) // Store fa3
- fsd f14,45*REGBYTES(sp) // Store fa4
- fsd f15,46*REGBYTES(sp) // Store fa5
- fsd f16,47*REGBYTES(sp) // Store fa6
- fsd f17,48*REGBYTES(sp) // Store fa7
- fsd f28,59*REGBYTES(sp) // Store ft8
- fsd f29,60*REGBYTES(sp) // Store ft9
- fsd f30,61*REGBYTES(sp) // Store ft10
- fsd f31,62*REGBYTES(sp) // Store ft11
+ fsd f0, 31*8(sp) // Store ft0
+ fsd f1, 32*8(sp) // Store ft1
+ fsd f2, 33*8(sp) // Store ft2
+ fsd f3, 34*8(sp) // Store ft3
+ fsd f4, 35*8(sp) // Store ft4
+ fsd f5, 36*8(sp) // Store ft5
+ fsd f6, 37*8(sp) // Store ft6
+ fsd f7, 38*8(sp) // Store ft7
+ fsd f10,41*8(sp) // Store fa0
+ fsd f11,42*8(sp) // Store fa1
+ fsd f12,43*8(sp) // Store fa2
+ fsd f13,44*8(sp) // Store fa3
+ fsd f14,45*8(sp) // Store fa4
+ fsd f15,46*8(sp) // Store fa5
+ fsd f16,47*8(sp) // Store fa6
+ fsd f17,48*8(sp) // Store fa7
+ fsd f28,59*8(sp) // Store ft8
+ fsd f29,60*8(sp) // Store ft9
+ fsd f30,61*8(sp) // Store ft10
+ fsd f31,62*8(sp) // Store ft11
csrr t0, fcsr
- STORE t0, 63*REGBYTES(sp) // Store fcsr
+ sd t0, 63*8(sp) // Store fcsr
#endif
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@@ -165,81 +158,82 @@ _tx_thread_not_nested_save:
/* Otherwise, not nested, check to see if a thread was running. */
/* else if (_tx_thread_current_ptr)
{ */
- addi x6, x6, 1 // Increment the interrupt counter
- STORE x6, 0(x5) // Store the interrupt counter
+ addi t1, t1, 1 // Increment the interrupt counter
+ sd t1, 0(t0) // Store the interrupt counter
/* Not nested: Find the user thread that was running and load our SP */
- LOAD x5, _tx_thread_current_ptr // Pickup current thread pointer
- beqz x5, _tx_thread_idle_system_save // If NULL, idle system was interrupted
+ la t0, _tx_thread_current_ptr // Pickup current thread pointer address
+ ld t0, 0(t0) // Pickup current thread pointer
+ beqz t0, _tx_thread_idle_system_save // If NULL, idle system was interrupted
/* Save the standard scratch registers. */
- STORE x7, 17*REGBYTES(sp) // Store t2
- STORE x8, 12*REGBYTES(sp) // Store s0
- STORE x10, 27*REGBYTES(sp) // Store a0
- STORE x11, 26*REGBYTES(sp) // Store a1
- STORE x12, 25*REGBYTES(sp) // Store a2
- STORE x13, 24*REGBYTES(sp) // Store a3
- STORE x14, 23*REGBYTES(sp) // Store a4
- STORE x15, 22*REGBYTES(sp) // Store a5
- STORE x16, 21*REGBYTES(sp) // Store a6
- STORE x17, 20*REGBYTES(sp) // Store a7
- STORE x28, 16*REGBYTES(sp) // Store t3
- STORE x29, 15*REGBYTES(sp) // Store t4
- STORE x30, 14*REGBYTES(sp) // Store t5
- STORE x31, 13*REGBYTES(sp) // Store t6
+ sd t2, 17*8(sp) // Store t2
+ sd s0, 12*8(sp) // Store s0
+ sd a0, 27*8(sp) // Store a0
+ sd a1, 26*8(sp) // Store a1
+ sd a2, 25*8(sp) // Store a2
+ sd a3, 24*8(sp) // Store a3
+ sd a4, 23*8(sp) // Store a4
+ sd a5, 22*8(sp) // Store a5
+ sd a6, 21*8(sp) // Store a6
+ sd a7, 20*8(sp) // Store a7
+ sd t3, 16*8(sp) // Store t3
+ sd t4, 15*8(sp) // Store t4
+ sd t5, 14*8(sp) // Store t5
+ sd t6, 13*8(sp) // Store t6
- csrr t0, mepc // Load exception program counter
- STORE t0, 30*REGBYTES(sp) // Save it on the stack
+ csrr t1, mepc // Load exception program counter
+ sd t1, 30*8(sp) // Save it on the stack
- /* Save floating point scratch registers. */
-#if defined(__riscv_float_abi_single)
- fsw f0, 31*REGBYTES(sp) // Store ft0
- fsw f1, 32*REGBYTES(sp) // Store ft1
- fsw f2, 33*REGBYTES(sp) // Store ft2
- fsw f3, 34*REGBYTES(sp) // Store ft3
- fsw f4, 35*REGBYTES(sp) // Store ft4
- fsw f5, 36*REGBYTES(sp) // Store ft5
- fsw f6, 37*REGBYTES(sp) // Store ft6
- fsw f7, 38*REGBYTES(sp) // Store ft7
- fsw f10,41*REGBYTES(sp) // Store fa0
- fsw f11,42*REGBYTES(sp) // Store fa1
- fsw f12,43*REGBYTES(sp) // Store fa2
- fsw f13,44*REGBYTES(sp) // Store fa3
- fsw f14,45*REGBYTES(sp) // Store fa4
- fsw f15,46*REGBYTES(sp) // Store fa5
- fsw f16,47*REGBYTES(sp) // Store fa6
- fsw f17,48*REGBYTES(sp) // Store fa7
- fsw f28,59*REGBYTES(sp) // Store ft8
- fsw f29,60*REGBYTES(sp) // Store ft9
- fsw f30,61*REGBYTES(sp) // Store ft10
- fsw f31,62*REGBYTES(sp) // Store ft11
+ /* Save floating point scratch registers if floating point is enabled. */
+#ifdef __riscv_float_abi_single
+ fsw f0, 31*8(sp) // Store ft0
+ fsw f1, 32*8(sp) // Store ft1
+ fsw f2, 33*8(sp) // Store ft2
+ fsw f3, 34*8(sp) // Store ft3
+ fsw f4, 35*8(sp) // Store ft4
+ fsw f5, 36*8(sp) // Store ft5
+ fsw f6, 37*8(sp) // Store ft6
+ fsw f7, 38*8(sp) // Store ft7
+ fsw f10,41*8(sp) // Store fa0
+ fsw f11,42*8(sp) // Store fa1
+ fsw f12,43*8(sp) // Store fa2
+ fsw f13,44*8(sp) // Store fa3
+ fsw f14,45*8(sp) // Store fa4
+ fsw f15,46*8(sp) // Store fa5
+ fsw f16,47*8(sp) // Store fa6
+ fsw f17,48*8(sp) // Store fa7
+ fsw f28,59*8(sp) // Store ft8
+ fsw f29,60*8(sp) // Store ft9
+ fsw f30,61*8(sp) // Store ft10
+ fsw f31,62*8(sp) // Store ft11
csrr t0, fcsr
- STORE t0, 63*REGBYTES(sp) // Store fcsr
+ sd t0, 63*8(sp) // Store fcsr
#elif defined(__riscv_float_abi_double)
- fsd f0, 31*REGBYTES(sp) // Store ft0
- fsd f1, 32*REGBYTES(sp) // Store ft1
- fsd f2, 33*REGBYTES(sp) // Store ft2
- fsd f3, 34*REGBYTES(sp) // Store ft3
- fsd f4, 35*REGBYTES(sp) // Store ft4
- fsd f5, 36*REGBYTES(sp) // Store ft5
- fsd f6, 37*REGBYTES(sp) // Store ft6
- fsd f7, 38*REGBYTES(sp) // Store ft7
- fsd f10,41*REGBYTES(sp) // Store fa0
- fsd f11,42*REGBYTES(sp) // Store fa1
- fsd f12,43*REGBYTES(sp) // Store fa2
- fsd f13,44*REGBYTES(sp) // Store fa3
- fsd f14,45*REGBYTES(sp) // Store fa4
- fsd f15,46*REGBYTES(sp) // Store fa5
- fsd f16,47*REGBYTES(sp) // Store fa6
- fsd f17,48*REGBYTES(sp) // Store fa7
- fsd f28,59*REGBYTES(sp) // Store ft8
- fsd f29,60*REGBYTES(sp) // Store ft9
- fsd f30,61*REGBYTES(sp) // Store ft10
- fsd f31,62*REGBYTES(sp) // Store ft11
+ fsd f0, 31*8(sp) // Store ft0
+ fsd f1, 32*8(sp) // Store ft1
+ fsd f2, 33*8(sp) // Store ft2
+ fsd f3, 34*8(sp) // Store ft3
+ fsd f4, 35*8(sp) // Store ft4
+ fsd f5, 36*8(sp) // Store ft5
+ fsd f6, 37*8(sp) // Store ft6
+ fsd f7, 38*8(sp) // Store ft7
+ fsd f10,41*8(sp) // Store fa0
+ fsd f11,42*8(sp) // Store fa1
+ fsd f12,43*8(sp) // Store fa2
+ fsd f13,44*8(sp) // Store fa3
+ fsd f14,45*8(sp) // Store fa4
+ fsd f15,46*8(sp) // Store fa5
+ fsd f16,47*8(sp) // Store fa6
+ fsd f17,48*8(sp) // Store fa7
+ fsd f28,59*8(sp) // Store ft8
+ fsd f29,60*8(sp) // Store ft9
+ fsd f30,61*8(sp) // Store ft10
+ fsd f31,62*8(sp) // Store ft11
csrr t0, fcsr
- STORE t0, 63*REGBYTES(sp) // Store fcsr
+ sd t0, 63*8(sp) // Store fcsr
#endif
/* Save the current stack pointer in the thread's control block. */
@@ -248,16 +242,17 @@ _tx_thread_not_nested_save:
/* Switch to the system stack. */
/* sp = _tx_thread_system_stack_ptr; */
- LOAD t1, _tx_thread_current_ptr // Pickup current thread pointer
- STORE sp, 2*REGBYTES(t1) // Save stack pointer
+ la t1, _tx_thread_current_ptr // Pickup current thread pointer address
+ ld t1, 0(t1) // Pickup current thread pointer
+ sd sp, 16(t1) // Save stack pointer
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
/* _tx_execution_isr_enter is called with thread stack pointer */
call _tx_execution_isr_enter // Call the ISR execution enter function
#endif
-
- LOAD sp, _tx_thread_system_stack_ptr // Switch to system stack
+ la t0, _tx_thread_system_stack_ptr // Pickup system stack pointer address
+ ld sp, 0(t0) // Switch to system stack
ret // Return to calling ISR
/* }
@@ -276,8 +271,8 @@ _tx_thread_idle_system_save:
/* }
} */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point enabled
+ addi sp, sp, 65*8 // Recover stack frame - with floating point enabled
#else
- addi sp, sp, 32*REGBYTES // Recover the reserved stack space
+ addi sp, sp, 32*8 // Recover the reserved stack space
#endif
ret // Return to calling ISR
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-13 09:37:49 +0000