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authorFrédéric Desbiens <[email protected]>2026-06-08 10:01:32 +0200
committerGitHub <[email protected]>2026-06-08 10:01:32 +0200
commit87ab09cce305eb9cd4aacac4e8c62af72f665bff (patch)
treedd062ebbea5235d1921c64b396bf7e4ce79e9e15 /ports/risc-v64/gnu/src/tx_thread_interrupt_control.S
parent9ab0cf9683f832cdb48e2099533a5b06a3afcd64 (diff)
parent730b61874bc5cf40768987605ae5187fde0fa1e2 (diff)
Merge pull request #544 from eclipse-threadx/devv6.5.1.202602_rel
Merging changes for the v.6.5.1.202602 release
Diffstat (limited to 'ports/risc-v64/gnu/src/tx_thread_interrupt_control.S')
-rw-r--r--ports/risc-v64/gnu/src/tx_thread_interrupt_control.S19
1 files changed, 12 insertions, 7 deletions
diff --git a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S
index dfcb6b47..b43d9558 100644
--- a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S
+++ b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S
@@ -59,20 +59,25 @@
.global _tx_thread_interrupt_control
_tx_thread_interrupt_control:
/* Pickup current interrupt lockout posture. */
- /* old_mstatus = mstatus; */
+#ifdef TX_RISCV_SMODE
+ csrr t0, sstatus
+ mv t1, t0 // Save original sstatus for return
+ li t2, ~0x02 // Build mask to clear SIE (bit 1)
+ and t0, t0, t2 // Clear SIE bit
+ andi a0, a0, 0x02 // Mask incoming to only SIE bit
+ or t0, t0, a0 // Set requested SIE state
+ csrw sstatus, t0
+ andi a0, t1, 0x02 // Return original SIE bit
+#else
csrr t0, mstatus
mv t1, t0 // Save original mstatus for return
-
- /* Apply the new interrupt posture while preserving unrelated mstatus bits. */
- /* Only modify the MIE bit (bit 3) */
- /* mstatus = (mstatus & ~MIE) | (new_posture & MIE); */
-
li t2, ~0x08 // Build mask to clear MIE
and t0, t0, t2 // Clear MIE bit
- and a0, a0, 0x08 // Mask incoming to only MIE bit
+ andi a0, a0, 0x08 // Mask incoming to only MIE bit
or t0, t0, a0 // Set requested MIE state
csrw mstatus, t0
andi a0, t1, 0x08 // Return original MIE bit
+#endif
ret
/* } */