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| author | Frédéric Desbiens <[email protected]> | 2025-02-24 15:43:49 -0500 |
|---|---|---|
| committer | GitHub <[email protected]> | 2025-02-24 15:43:49 -0500 |
| commit | 06dabb0ad0403f59889ce85eeb3d48dbd9d3759b (patch) | |
| tree | 55c635ef6650198af9edf00e063c916124cfa816 /ports/risc-v64/gnu/src | |
| parent | 98c9172d01dcfdd0026ee3f5c6259dea6a12f253 (diff) | |
| parent | f0a44ad3914da1ce8429e55ff74f59eca11b6ec7 (diff) | |
Merge pull request #442 from eclipse-threadx/devv6.4.2_rel
Release ThreadX 6.4.2
Diffstat (limited to 'ports/risc-v64/gnu/src')
| -rw-r--r-- | ports/risc-v64/gnu/src/tx_initialize_low_level.S | 1 | ||||
| -rw-r--r-- | ports/risc-v64/gnu/src/tx_thread_context_restore.S | 8 | ||||
| -rw-r--r-- | ports/risc-v64/gnu/src/tx_thread_schedule.S | 4 |
3 files changed, 13 insertions, 0 deletions
diff --git a/ports/risc-v64/gnu/src/tx_initialize_low_level.S b/ports/risc-v64/gnu/src/tx_initialize_low_level.S index de6203a9..ccafd5e2 100644 --- a/ports/risc-v64/gnu/src/tx_initialize_low_level.S +++ b/ports/risc-v64/gnu/src/tx_initialize_low_level.S @@ -69,6 +69,7 @@ __tx_free_memory_start: /* VOID _tx_initialize_low_level(VOID) { */ .global _tx_initialize_low_level + .weak _tx_initialize_low_level _tx_initialize_low_level: sd sp, _tx_thread_system_stack_ptr, t0 // Save system stack pointer diff --git a/ports/risc-v64/gnu/src/tx_thread_context_restore.S b/ports/risc-v64/gnu/src/tx_thread_context_restore.S index 64da25b4..d805a59c 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_restore.S @@ -149,6 +149,10 @@ _tx_thread_context_restore: LOAD t0, 30*REGBYTES(sp) // Recover mepc csrw mepc, t0 // Setup mepc li t0, 0x1880 // Prepare MPIP +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t1, 1<<13 + or t0, t1, t0 +#endif csrw mstatus, t0 // Enable MPIP LOAD x1, 28*REGBYTES(sp) // Recover RA @@ -259,6 +263,10 @@ _tx_thread_no_preempt_restore: LOAD t0, 240(sp) // Recover mepc csrw mepc, t0 // Setup mepc li t0, 0x1880 // Prepare MPIP +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t1, 1<<13 + or t0, t1, t0 +#endif csrw mstatus, t0 // Enable MPIP LOAD x1, 28*REGBYTES(sp) // Recover RA diff --git a/ports/risc-v64/gnu/src/tx_thread_schedule.S b/ports/risc-v64/gnu/src/tx_thread_schedule.S index 343da393..c9be4c6f 100644 --- a/ports/risc-v64/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v64/gnu/src/tx_thread_schedule.S @@ -201,6 +201,10 @@ _tx_thread_schedule_loop: LOAD t0, 30*REGBYTES(sp) // Recover mepc csrw mepc, t0 // Store mepc li t0, 0x1880 // Prepare MPIP +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t1, 1<<13 + or t0, t1, t0 +#endif csrw mstatus, t0 // Enable MPIP LOAD x1, 28*REGBYTES(sp) // Recover RA |