diff options
| author | Frédéric Desbiens <[email protected]> | 2026-03-06 19:27:49 +0100 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-03-06 19:27:49 +0100 |
| commit | 3726d7906b4808bfec7855fc088e073199df9120 (patch) | |
| tree | 8789bfd03d1d49e1967e80d04aa4ff606fda43eb /ports/rxv3 | |
| parent | 4b6e8100d932a3a67b34c6eb17f84f3bffb9e2ae (diff) | |
| parent | c3259a216026372e3833dd8996a68f77e8595fbd (diff) | |
Merge pull request #510 from eclipse-threadx/devv6.5.0.202601_rel
Merge changes ahead of the v6.5.0.202601 release
Diffstat (limited to 'ports/rxv3')
31 files changed, 902 insertions, 1140 deletions
diff --git a/ports/rxv3/ccrx/CMakeLists.txt b/ports/rxv3/ccrx/CMakeLists.txt index fabadffe..f2269c51 100644 --- a/ports/rxv3/ccrx/CMakeLists.txt +++ b/ports/rxv3/ccrx/CMakeLists.txt @@ -2,7 +2,7 @@ target_sources(${PROJECT_NAME} PRIVATE # {{BEGIN_TARGET_SOURCES}} - ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.src + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.src ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.src ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.src ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.src diff --git a/ports/rxv3/ccrx/inc/tx_port.h b/ports/rxv3/ccrx/inc/tx_port.h index 62c637e3..a56636bd 100644 --- a/ports/rxv3/ccrx/inc/tx_port.h +++ b/ports/rxv3/ccrx/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,45 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RXv3/CCRX */ /* 6.1.11 */ /* */ -/* AUTHOR */ +/* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), and */ -/* added FPU support, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), removed */ -/* system state macro, and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -68,13 +53,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -83,8 +68,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ @@ -116,8 +103,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif #ifndef TX_TRACE_TIME_SOURCE @@ -141,7 +128,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -153,13 +140,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_fpu_enable; /* FPU Register Save Flag. */ -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -173,11 +160,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -185,8 +172,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -213,16 +200,16 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* UINT _tx_thread_interrupt_control(UINT new_posture); */ -#pragma inline_asm _tx_thread_interrupt_disable +#pragma inline_asm _tx_thread_interrupt_disable static UINT _tx_thread_interrupt_disable(void){ MVFC PSW,R1 ; CLRPSW I ; @@ -277,8 +264,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv3/CCRX Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/CCRX Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/ccrx/readme_threadx.txt b/ports/rxv3/ccrx/readme_threadx.txt index cbc8149d..06e306e1 100644 --- a/ports/rxv3/ccrx/readme_threadx.txt +++ b/ports/rxv3/ccrx/readme_threadx.txt @@ -16,25 +16,25 @@ for the RXv3 3. System Initialization -The system entry point using Renesas tools is at the label _PowerON_Reset_PC. -Use the resetprg.c file that comes with your release. Most notable is that Threadx -applications run in supervisor mode and do not use user mode. Hence switching to +The system entry point using Renesas tools is at the label _PowerON_Reset_PC. +Use the resetprg.c file that comes with your release. Most notable is that Threadx +applications run in supervisor mode and do not use user mode. Hence switching to user mode has been commented out. The vector area is set up using either intprg.c or in the file tx_initialize_low_level.src. -The file tx_initialize_low_level.src is responsible for setting up various system data -structures, interrupt vectors, and a periodic timer. This is the ideal place add +The file tx_initialize_low_level.src is responsible for setting up various system data +structures, interrupt vectors, and a periodic timer. This is the ideal place add application specific hardware initialization code. -ThreadX utilizes CMT0 as a periodic timer interrupt source. The CMT0 interrupt is -typically setup for 10ms periodic interrupts and the interrupt priority level is set to +ThreadX utilizes CMT0 as a periodic timer interrupt source. The CMT0 interrupt is +typically setup for 10ms periodic interrupts and the interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in r_cmt_rx_config.h of Renesas CMT timer module (r_cmt_rx). You may change any of the timer parameters to suit your needs. -In addition, _tx_initialize_low_level determines the first available address for use by -the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define(). The mechanism is implemented by creating the -FREEMEM section, this section should be linked last in the RAM area. tx_initialize_low_level +In addition, _tx_initialize_low_level determines the first available address for use by +the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define(). The mechanism is implemented by creating the +FREEMEM section, this section should be linked last in the RAM area. tx_initialize_low_level will pick up the starting label of this section and put it in the global variable: _tx_initialize_unused_memory @@ -42,15 +42,15 @@ _tx_initialize_unused_memory 4. Context Switch, Register Usage and Stack Frames The RXv3 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Stack Frame without DFPU Register @@ -75,7 +75,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x44 R2 0x48 PC - return address 0x4C PSW - + Offset Stack Frame with DFPU Register 0x00 DPSW @@ -118,7 +118,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x94 R2 0x98 PC - return address 0x9C PSW - + Note: By default ccrx does not save the state of the accumulator registers ACC0 and ACC1 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of those registers could be corrupted. Saving and restoring of the accumulators @@ -127,29 +127,29 @@ can be enabled by adding the -save_acc command line option. 5. Double Precision FPU Instructions Support -The RXv3 architecture supports an optional set of double precision instructions which -makes use of a new set of registers that must be saved and restored during context -switches. This feature can be accessed by adding the -dfpu compiler switch. +The RXv3 architecture supports an optional set of double precision instructions which +makes use of a new set of registers that must be saved and restored during context +switches. This feature can be accessed by adding the -dfpu compiler switch. To reduce the overhead of saving and restoring the FPU registers for all threads -the RXv3 port allows each thread to enable and disable saving and restoring the DFPU -registers. By default the feature is disabled for new threads. To enable the feature -tx_thread_fpu_enable() must be called within the context of every thread that will +the RXv3 port allows each thread to enable and disable saving and restoring the DFPU +registers. By default the feature is disabled for new threads. To enable the feature +tx_thread_fpu_enable() must be called within the context of every thread that will perform FPU operation. The saving and restoring of DFPU registers can be disabled again by calling tx_thread_fpu_disable(). This can be useful if a thread only makes occasional use of the FPU. - + 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make ThreadX run faster, you can change the ThreadX Library -project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the ThreadX Library +project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 7. Timer Processing @@ -161,18 +161,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 8. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effects but doing so may slightly reduce +priority 1 won't cause any negative side effects but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 9. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv3 release make the following modifications: @@ -191,7 +191,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) @@ -214,7 +214,7 @@ information associated with this specific port of ThreadX: tx_thread_schedule.src Added low power support 01-31-2022 Release 6.1.10 changes: - tx_port.h Removed system state macro, and added + tx_port.h Removed system state macro, and added missing interrupt control defines tx_timer_interrupt.src Added missing thread preemption logic diff --git a/ports/rxv3/ccrx/src/tx_initialize_low_level.src b/ports/rxv3/ccrx/src/tx_initialize_low_level.src index bec6521c..172144ff 100644 --- a/ports/rxv3/ccrx/src/tx_initialize_low_level.src +++ b/ports/rxv3/ccrx/src/tx_initialize_low_level.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -26,55 +26,55 @@ IEN03 .EQU 87203H .SECTION P,CODE - + ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ .GLB __tx_initialize_low_level __tx_initialize_low_level: @@ -97,7 +97,7 @@ __tx_initialize_low_level: OR #(1 << 3), r2 MOV.B r2, [r1] - RTS + RTS .SECTION FREEMEM ,DATA, ALIGN=4 free_mem_start: diff --git a/ports/rxv3/ccrx/src/tx_thread_context_restore.src b/ports/rxv3/ccrx/src/tx_thread_context_restore.src index d64f15e1..2a5b2217 100644 --- a/ports/rxv3/ccrx/src/tx_thread_context_restore.src +++ b/ports/rxv3/ccrx/src/tx_thread_context_restore.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,53 +39,53 @@ .GLB __tx_thread_preempt_disable ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), and */ +;/* added FPU support, */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ .GLB __tx_thread_context_restore @@ -103,7 +103,7 @@ __tx_thread_context_restore: MOV.L [R1], R2 SUB #1, R2 MOV.L R2,[R1] - BEQ __tx_thread_not_nested_restore + BEQ __tx_thread_not_nested_restore ; ; /* Interrupts are nested. */ @@ -112,7 +112,7 @@ __tx_thread_context_restore: ; and return to the point of interrupt. */ ; __tx_thread_nested_restore: - POPC FPSW ; Restore FPU status + POPC FPSW ; Restore FPU status POPM R14-R15 ; Restore R14-R15 POPM R3-R5 ; Restore R3-R5 POPM R1-R2 ; Restore R1-R2 @@ -125,17 +125,17 @@ __tx_thread_not_nested_restore: ; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { - + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address MOV.L [R1], R2 CMP #0, R2 - BEQ __tx_thread_idle_system_restore - + BEQ __tx_thread_idle_system_restore + MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag MOV.L [R3], R3 CMP #0, R3 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless - + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) CMP [R3], R2 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring diff --git a/ports/rxv3/ccrx/src/tx_thread_context_save.src b/ports/rxv3/ccrx/src/tx_thread_context_save.src index 0e4dce94..69bbd670 100644 --- a/ports/rxv3/ccrx/src/tx_thread_context_save.src +++ b/ports/rxv3/ccrx/src/tx_thread_context_save.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,51 +34,51 @@ .GLB __tx_thread_system_stack_ptr .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ .GLB __tx_thread_context_save @@ -104,7 +104,7 @@ __tx_thread_context_save: BEQ __tx_thread_not_nested_save ; ; /* Nested interrupt condition. */ -; +; ADD #1, r2 ; _tx_thread_system_state++ MOV.L r2, [r1] @@ -130,7 +130,7 @@ __tx_thread_not_nested_save: MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer MOV.L [R2], R2 - CMP #0,R2 ; Is it NULL? + CMP #0,R2 ; Is it NULL? BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore ; ; /* Move stack frame over to the current threads stack. */ @@ -142,9 +142,9 @@ __tx_thread_not_nested_save: MOV.L 12[R0], R2 MOV.L R2, [-R1] ; Save PC on thread stack MOV.L 8[R0], R2 - MOV.L R2, [-R1] ; Save R2 on thread stack + MOV.L R2, [-R1] ; Save R2 on thread stack MOV.L 4[R0], R2 - MOV.L R2, [-R1] ; Save R1 on thread stack + MOV.L R2, [-R1] ; Save R1 on thread stack MOV.L R5, [-R1] ; Save R5 on thread stack MOV.L R4, [-R1] ; Save R4 on thread stack MOV.L R3, [-R1] ; Save R3 on thread stack @@ -152,9 +152,9 @@ __tx_thread_not_nested_save: MOV.L R14, [-R1] ; Save R14 on thread stack MVFC FPSW, R3 MOV.L R3, [-R1] ; Save FPSW on thread stack - + POP R2 ; Pick up return address from interrupt stack - ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom + ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom MVTC R1, USP ; Set user/thread stack pointer JMP R2 ; Return to ISR diff --git a/ports/rxv3/ccrx/src/tx_thread_interrupt_control.src b/ports/rxv3/ccrx/src/tx_thread_interrupt_control.src index e3d1d640..ec4208ec 100644 --- a/ports/rxv3/ccrx/src/tx_thread_interrupt_control.src +++ b/ports/rxv3/ccrx/src/tx_thread_interrupt_control.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,50 +29,50 @@ ; ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ @@ -81,20 +81,20 @@ __tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ ; - + MVFC PSW, R2 ; Save PSW to R2 MOV.L R2, R3 ; Make a copy of PSW in r3 - + ; ; /* Apply the new interrupt posture. */ ; - + BTST #16, R1 ; Test I bit of PSW of "new posture" - BMNE #16, R2 ; Conditionally set I bit of intermediate posture - + BMNE #16, R2 ; Conditionally set I bit of intermediate posture + MVTC R2, PSW ; Save intermediate posture to PSW - - MOV.L R3,R1 ; Get original SR + + MOV.L R3,R1 ; Get original SR RTS ; Return to caller ;} .END diff --git a/ports/rxv3/ccrx/src/tx_thread_schedule.src b/ports/rxv3/ccrx/src/tx_thread_schedule.src index abbd6cbf..116281ee 100644 --- a/ports/rxv3/ccrx/src/tx_thread_schedule.src +++ b/ports/rxv3/ccrx/src/tx_thread_schedule.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,55 +41,55 @@ ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_schedule RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), and */ +;/* added FPU support, */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), and */ -;/* added low power support, */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* 04-25-2022 William E. Lamie Modified comment(s), and */ +;/* added low power support, */ +;/* resulting in version 6.1.11 */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ .GLB __tx_thread_schedule @@ -106,7 +106,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready .IF TX_LOW_POWER==1 MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -135,7 +135,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ @@ -147,7 +147,7 @@ __tx_thread_thread_ready: ; /* Increment the run count for this thread. */ ; _tx_thread_current_ptr -> tx_thread_run_count++; ; - MOV.L 4[R2],R3 ; Pickup run count + MOV.L 4[R2],R3 ; Pickup run count ADD #1,R3 ; Increment run counter MOV.L R3,4[R2] ; Store it back in control block ; @@ -156,7 +156,7 @@ __tx_thread_thread_ready: ; MOV.L 24[R2],R3 ; Pickup thread time-slice MOV.L #__tx_timer_time_slice,R4 ; Pickup pointer to time-slice - MOV.L R3, [R4] ; Setup time-slice + MOV.L R3, [R4] ; Setup time-slice ; ; /* Switch to the thread's stack. */ ; SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; @@ -184,12 +184,12 @@ __tx_thread_schedule_fpu_skip: MVTACGU R1, A1 POPM R6-R13 ; Recover interrupt stack frame - POPC FPSW + POPC FPSW POPM R14-R15 POPM R3-R5 - POPM R1-R2 + POPM R1-R2 RTE ; Return to point of interrupt, this restores PC and PSW - + ; ;} diff --git a/ports/rxv3/ccrx/src/tx_thread_stack_build.src b/ports/rxv3/ccrx/src/tx_thread_stack_build.src index 6738fef3..749d459d 100644 --- a/ports/rxv3/ccrx/src/tx_thread_stack_build.src +++ b/ports/rxv3/ccrx/src/tx_thread_stack_build.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -30,61 +30,61 @@ ; ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_stack_build RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ +;/* */ +;/* CALLED BY */ +;/* */ ;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ .GLB __tx_thread_stack_build __tx_thread_stack_build: ; -; +; ; /* Build an interrupt frame. The form of the fake interrupt stack ; on the Renesas RX should look like the following after it is built: -; +; ; Stack Top: ACC0 ; ACC1 ; R6 @@ -120,22 +120,22 @@ __tx_thread_stack_build: MOV.L R2, [-R3] ; Initial PC MOV.L #0, R4 MOV.L R4,[-R3] ; Initial R2 ... - MOV.L R4,[-R3] ; Initial R1 ... + MOV.L R4,[-R3] ; Initial R1 ... MOV.L R4,[-R3] ; Initial R5 ... MOV.L R4,[-R3] ; Initial R4 ... - MOV.L R4,[-R3] ; Initial R3 ... + MOV.L R4,[-R3] ; Initial R3 ... MOV.L R4,[-R3] ; Initial R15 ... MOV.L R4,[-R3] ; Initial R14 ... MVFC FPSW, r4 MOV.L R4, [-R3] ; Initial FPSW MOV.L #0, R4 - MOV.L R4,[-R3] ; Initial R13 ... + MOV.L R4,[-R3] ; Initial R13 ... MOV.L R4,[-R3] ; Initial R12 ... MOV.L R4,[-R3] ; Initial R11 ... - MOV.L R4,[-R3] ; Initial R10 ... + MOV.L R4,[-R3] ; Initial R10 ... MOV.L R4,[-R3] ; Initial R9 ... MOV.L R4,[-R3] ; Initial R8 ... - MOV.L R4,[-R3] ; Initial R7 ... + MOV.L R4,[-R3] ; Initial R7 ... MOV.L R4,[-R3] ; Initial R6 ... MOV.L R4,[-R3] ; Accumulator 1 @@ -147,11 +147,11 @@ __tx_thread_stack_build: MOV.L R4,[-R3] ; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} .END diff --git a/ports/rxv3/ccrx/src/tx_thread_system_return.src b/ports/rxv3/ccrx/src/tx_thread_system_return.src index a3e41c9a..8614ab58 100644 --- a/ports/rxv3/ccrx/src/tx_thread_system_return.src +++ b/ports/rxv3/ccrx/src/tx_thread_system_return.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,43 +34,43 @@ .GLB __tx_thread_schedule .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_system_return RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the system. Only a minimal context */ -;/* is saved since the compiler assumes temp registers are going to get */ -;/* slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the system. Only a minimal context */ +;/* is saved since the compiler assumes temp registers are going to get */ +;/* slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ ;/* 10-15-2021 William E. Lamie Modified comment(s), and */ ;/* removed unused code, */ @@ -79,8 +79,8 @@ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ .GLB __tx_thread_system_return diff --git a/ports/rxv3/ccrx/src/tx_timer_interrupt.src b/ports/rxv3/ccrx/src/tx_timer_interrupt.src index 3d5d1a36..a0edaa6f 100644 --- a/ports/rxv3/ccrx/src/tx_timer_interrupt.src +++ b/ports/rxv3/ccrx/src/tx_timer_interrupt.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -50,58 +50,58 @@ .GLB __tx_thread_current_ptr ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_timer_interrupt RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_context_save Save interrupted context */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_thread_context_restore Restore interrupted context */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_context_save Save interrupted context */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_restore Restore interrupted context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), and */ ;/* added missing thread */ ;/* preemption logic, */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ .GLB __tx_timer_interrupt @@ -164,14 +164,14 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; Pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; ; MOV.L #__tx_timer_expired,R2 ; Build address of expired flag MOV.L #1, R1 ; Build expired value - MOV.L R1, [R2] + MOV.L R1, [R2] BRA __tx_timer_done ; Finished with timer processing ; ; } @@ -182,7 +182,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -201,9 +201,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 - MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + MOV.L #__tx_timer_current_ptr,R1 + MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -237,14 +237,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing diff --git a/ports/rxv3/gnu/inc/tx_port.h b/ports/rxv3/gnu/inc/tx_port.h index 765d7061..52da26d8 100644 --- a/ports/rxv3/gnu/inc/tx_port.h +++ b/ports/rxv3/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,44 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RXv3/GNURX */ /* 6.1.11 */ /* */ -/* AUTHOR */ -/* */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), and */ -/* added FPU support, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -70,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -85,8 +71,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ @@ -118,8 +106,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -144,7 +132,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -156,13 +144,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_fpu_enable; /* FPU Register Save Flag. */ -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -176,11 +164,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -188,8 +176,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -215,9 +203,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -273,8 +261,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv3/GNURX Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/GNURX Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/gnu/readme_threadx.txt b/ports/rxv3/gnu/readme_threadx.txt index 3d68313c..2a812d62 100644 --- a/ports/rxv3/gnu/readme_threadx.txt +++ b/ports/rxv3/gnu/readme_threadx.txt @@ -18,40 +18,40 @@ for the RXv3. 3. System Initialization -The system entry point using the GNU tools is at the label _PowerON_Reset. +The system entry point using the GNU tools is at the label _PowerON_Reset. -The vector area is setup in the file tx_initialize_low_level.S. This file is also -responsible for setting up various system data structures, interrupt vectors, and -the periodic timer interrupt. This file is also an ideal place to add additional hardware +The vector area is setup in the file tx_initialize_low_level.S. This file is also +responsible for setting up various system data structures, interrupt vectors, and +the periodic timer interrupt. This file is also an ideal place to add additional hardware initialization code. -The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt -source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the -interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in -r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer +The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt +source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the +interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in +r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer parameters as needed. Increasing the timer interrupt frequency increases the overhead of the timer handling code on the system. -In addition, _tx_initialize_low_level determines the first available address for use -by the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define. The first available memory is determined +In addition, _tx_initialize_low_level determines the first available address for use +by the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define. The first available memory is determined by the location of the '_end' label the is defined in the linker script. -'_end' should reference the first memory AFTER all other RAM +'_end' should reference the first memory AFTER all other RAM sections in your linker control file. 4. Context Switch, Register Usage and Stack Frames The RXv3 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Stack Frame without DFPU Register @@ -76,7 +76,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x44 R2 0x48 PC - return address 0x4C PSW - + Offset Stack Frame with DFPU Register 0x00 DPSW @@ -119,7 +119,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x94 R2 0x98 PC - return address 0x9C PSW - + Note: By default GNURX does not save the state of the accumulator registers ACC0 and ACC1 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of those registers could be corrupted. Saving and restoring of the accumulators @@ -127,27 +127,27 @@ can be enabled by adding the -msave-acc-in-interrupts command line option. 5. Double Precision FPU Instructions Support -The RXv3 architecture supports an optional set of double precision instructions which -makes use of a new set of registers that must be saved and restored during context -switches. This feature can be accessed by adding the -mdfpu -m64bit-doubles compiler switches. +The RXv3 architecture supports an optional set of double precision instructions which +makes use of a new set of registers that must be saved and restored during context +switches. This feature can be accessed by adding the -mdfpu -m64bit-doubles compiler switches. To reduce the overhead of saving and restoring the FPU registers for all threads -the RXv3 port allows each thread to enable and disable saving and restoring the DFPU -registers. By default the feature is disabled for new threads. To enable the feature -tx_thread_fpu_enable() must be called within the context of every thread that will +the RXv3 port allows each thread to enable and disable saving and restoring the DFPU +registers. By default the feature is disabled for new threads. To enable the feature +tx_thread_fpu_enable() must be called within the context of every thread that will perform FPU operation. The saving and restoring of DFPU registers can be disabled again by calling tx_thread_fpu_disable(). This can be useful if a thread only makes occasional use of the FPU. - + 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. This -makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. -Of course, this costs some performance. To make ThreadX run faster, you can change the -ThreadX Library project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler optimizations. This +makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. +Of course, this costs some performance. To make ThreadX run faster, you can change the +ThreadX Library project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by compiling your -application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h -is included. +In addition, you can eliminate the ThreadX basic API error checking by compiling your +application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h +is included. 7. Timer Processing @@ -159,18 +159,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 8. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effects but doing so may slightly reduce +priority 1 won't cause any negative side effects but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 9. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv3 release make the following modifications: @@ -189,7 +189,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) diff --git a/ports/rxv3/gnu/src/tx_initialize_low_level.S b/ports/rxv3/gnu/src/tx_initialize_low_level.S index e0f89d99..3512d9c3 100644 --- a/ports/rxv3/gnu/src/tx_initialize_low_level.S +++ b/ports/rxv3/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -57,18 +57,6 @@ ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ .global __tx_initialize_low_level __tx_initialize_low_level: diff --git a/ports/rxv3/gnu/src/tx_thread_context_restore.S b/ports/rxv3/gnu/src/tx_thread_context_restore.S index 2090fc48..8c8b42f0 100644 --- a/ports/rxv3/gnu/src/tx_thread_context_restore.S +++ b/ports/rxv3/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,19 +73,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ diff --git a/ports/rxv3/gnu/src/tx_thread_context_save.S b/ports/rxv3/gnu/src/tx_thread_context_save.S index eb4caee0..3fbfc3a1 100644 --- a/ports/rxv3/gnu/src/tx_thread_context_save.S +++ b/ports/rxv3/gnu/src/tx_thread_context_save.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -66,18 +66,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ diff --git a/ports/rxv3/gnu/src/tx_thread_interrupt_control.S b/ports/rxv3/gnu/src/tx_thread_interrupt_control.S index 1111dc97..4dba35ef 100644 --- a/ports/rxv3/gnu/src/tx_thread_interrupt_control.S +++ b/ports/rxv3/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -60,18 +60,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/rxv3/gnu/src/tx_thread_schedule.S b/ports/rxv3/gnu/src/tx_thread_schedule.S index f01b22bf..6165d7ef 100644 --- a/ports/rxv3/gnu/src/tx_thread_schedule.S +++ b/ports/rxv3/gnu/src/tx_thread_schedule.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -75,20 +75,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), and */ -;/* added low power support, */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ @@ -106,7 +92,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready #if (TX_LOW_POWER == 1) MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -135,7 +121,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ diff --git a/ports/rxv3/gnu/src/tx_thread_stack_build.S b/ports/rxv3/gnu/src/tx_thread_stack_build.S index a1398c51..5908e00f 100644 --- a/ports/rxv3/gnu/src/tx_thread_stack_build.S +++ b/ports/rxv3/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -63,18 +63,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/rxv3/gnu/src/tx_thread_system_return.S b/ports/rxv3/gnu/src/tx_thread_system_return.S index ecd7b205..c1106461 100644 --- a/ports/rxv3/gnu/src/tx_thread_system_return.S +++ b/ports/rxv3/gnu/src/tx_thread_system_return.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -67,19 +67,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unused code, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/rxv3/gnu/src/tx_timer_interrupt.S b/ports/rxv3/gnu/src/tx_timer_interrupt.S index 5fd09f8f..bc09965d 100644 --- a/ports/rxv3/gnu/src/tx_timer_interrupt.S +++ b/ports/rxv3/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -85,20 +85,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/rxv3/iar/inc/tx_port.h b/ports/rxv3/iar/inc/tx_port.h index 1408a93e..e40be831 100644 --- a/ports/rxv3/iar/inc/tx_port.h +++ b/ports/rxv3/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,45 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RXv3/IAR */ /* 6.1.11 */ /* */ -/* AUTHOR */ -/* */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), and */ -/* added FPU support, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), removed */ -/* system state macro, and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -71,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -86,8 +71,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ @@ -119,8 +106,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -145,7 +132,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -157,13 +144,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_fpu_enable; /* FPU Register Save Flag. */ -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -177,11 +164,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -189,8 +176,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -216,9 +203,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -274,8 +261,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv3/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/IAR Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/iar/readme_threadx.txt b/ports/rxv3/iar/readme_threadx.txt index 2100d92d..e0564ae9 100644 --- a/ports/rxv3/iar/readme_threadx.txt +++ b/ports/rxv3/iar/readme_threadx.txt @@ -17,38 +17,38 @@ for the RXv3. 3. System Initialization -The system entry point using the IAR tools is at the label __iar_program_start. +The system entry point using the IAR tools is at the label __iar_program_start. -The vector area is setup in the file tx_initialize_low_level.s. This file is also -responsible for setting up various system data structures, interrupt vectors, and -the periodic timer interrupt. This file is also an ideal place add hardware +The vector area is setup in the file tx_initialize_low_level.s. This file is also +responsible for setting up various system data structures, interrupt vectors, and +the periodic timer interrupt. This file is also an ideal place add hardware initialization code. -The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt -source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the -interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in -r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the +The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt +source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the +interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in +r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer parameters as needed. -In addition, _tx_initialize_low_level determines the first available address for use -by the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define. The first available memory is determined -by the location of the FREEMEM section so it should be placed AFTER all other RAM +In addition, _tx_initialize_low_level determines the first available address for use +by the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define. The first available memory is determined +by the location of the FREEMEM section so it should be placed AFTER all other RAM sections in your linker control file. 4. Context Switch, Register Usage and Stack Frames The RXv3 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Stack Frame @@ -73,7 +73,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x44 R2 0x48 PC - return address 0x4C PSW - + Offset Stack Frame with DFPU Register 0x00 DPSW @@ -116,38 +116,38 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x94 R2 0x98 PC - return address 0x9C PSW - - + + Note: By default IAR does not save the state of the accumulator registers ACC0 and ACC1 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of those registers could be corrupted. Saving and restoring of the acummulators can be enabled by adding the --save_acc command line option. - + 5. Double Precision FPU Instructions Support -The RXv3 architecture supports an optional set of double precision instructions which -makes use of a new set of registers that must be saved and restored during context +The RXv3 architecture supports an optional set of double precision instructions which +makes use of a new set of registers that must be saved and restored during context switches. This feature can be accessed by setting the size of double to 64 bit in the -compiler options. To reduce the overhead of saving and restoring the FPU registers -for all threads the RXv3 port allows each thread to enable and disable saving and -restoring the DFPU registers. By default the feature is disabled for new threads. -To enable the feature tx_thread_fpu_enable() must be called within the context of every +compiler options. To reduce the overhead of saving and restoring the FPU registers +for all threads the RXv3 port allows each thread to enable and disable saving and +restoring the DFPU registers. By default the feature is disabled for new threads. +To enable the feature tx_thread_fpu_enable() must be called within the context of every thread that will perform FPU operation. The saving and restoring of DFPU registers can -be disabled again by calling tx_thread_fpu_disable(). This can be useful if a thread +be disabled again by calling tx_thread_fpu_disable(). This can be useful if a thread only makes occasional use of the FPU. 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. This -makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. -Of course, this costs some performance. To make ThreadX run faster, you can change the -ThreadX Library project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler optimizations. This +makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. +Of course, this costs some performance. To make ThreadX run faster, you can change the +ThreadX Library project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by compiling your -application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h -is included. +In addition, you can eliminate the ThreadX basic API error checking by compiling your +application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h +is included. 7. Timer Processing @@ -159,18 +159,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 8. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effectd but doing so may slightly reduce +priority 1 won't cause any negative side effectd but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 9. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv3 release make the following modifications: @@ -189,7 +189,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) @@ -208,7 +208,7 @@ information associated with this specific port of ThreadX: tx_thread_schedule.s Added low power support 01-31-2022 Release 6.1.10 changes: - tx_port.h Removed system state macro, and added + tx_port.h Removed system state macro, and added missing interrupt control defines tx_timer_interrupt.s Added missing thread preemption logic diff --git a/ports/rxv3/iar/src/tx_initialize_low_level.s b/ports/rxv3/iar/src/tx_initialize_low_level.s index 5b0c04e5..c40b4300 100644 --- a/ports/rxv3/iar/src/tx_initialize_low_level.s +++ b/ports/rxv3/iar/src/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -25,53 +25,41 @@ section .text:CODE:ROOT ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/**************************************************************************/ public __tx_initialize_low_level __tx_initialize_low_level: @@ -80,7 +68,7 @@ __tx_initialize_low_level: ; _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; ; MOV.L #__tx_free_memory_start, R1 ; Pickup unused memory address - MOV.L #__tx_initialize_unused_memory,R2 + MOV.L #__tx_initialize_unused_memory,R2 MOV.L R1,[R2] ; Save first free memory address ; /* Set priority of SWINT to 1. */ diff --git a/ports/rxv3/iar/src/tx_thread_context_restore.s b/ports/rxv3/iar/src/tx_thread_context_restore.s index 9306d159..f6d0e605 100644 --- a/ports/rxv3/iar/src/tx_thread_context_restore.s +++ b/ports/rxv3/iar/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,53 +39,40 @@ section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/**************************************************************************/ public __tx_thread_context_restore __tx_thread_context_restore: @@ -102,7 +89,7 @@ __tx_thread_context_restore: MOV.L [R1], R2 SUB #1, R2 MOV.L R2,[R1] - BEQ __tx_thread_not_nested_restore + BEQ __tx_thread_not_nested_restore ; ; /* Interrupts are nested. */ @@ -111,7 +98,7 @@ __tx_thread_context_restore: ; and return to the point of interrupt. */ ; __tx_thread_nested_restore: - POPC FPSW ; Restore FPU status + POPC FPSW ; Restore FPU status POPM R14-R15 ; Restore R14-R15 POPM R3-R5 ; Restore R3-R5 POPM R1-R2 ; Restore R1-R2 @@ -124,17 +111,17 @@ __tx_thread_not_nested_restore: ; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { - + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address MOV.L [R1], R2 CMP #0, R2 - BEQ __tx_thread_idle_system_restore - + BEQ __tx_thread_idle_system_restore + MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag MOV.L [R3], R3 CMP #0, R3 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless - + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) CMP [R3], R2 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring @@ -175,7 +162,7 @@ __tx_thread_dont_save_ts: SETPSW U ; User stack PUSHM R6-R13 - + MVFACGU #0, A1, R4 ; Save accumulators. MVFACHI #0, A1, R5 MVFACLO #0, A1, R6 @@ -184,7 +171,7 @@ __tx_thread_dont_save_ts: MVFACHI #0, A0, R5 MVFACLO #0, A0, R6 PUSHM R4-R6 - + #if (__DPFPU == 1) MOV.L 144[R2], R4 ; Get tx_thread_fpu_enable. CMP #0, R4 diff --git a/ports/rxv3/iar/src/tx_thread_context_save.s b/ports/rxv3/iar/src/tx_thread_context_save.s index f6128347..91ac51a1 100644 --- a/ports/rxv3/iar/src/tx_thread_context_save.s +++ b/ports/rxv3/iar/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,51 +33,39 @@ extern __tx_thread_current_ptr section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ public __tx_thread_context_save @@ -104,7 +92,7 @@ __tx_thread_context_save: BEQ __tx_thread_not_nested_save ; ; /* Nested interrupt condition. */ -; +; ADD #1, r2 ; _tx_thread_system_state++ MOV.L r2, [r1] @@ -130,7 +118,7 @@ __tx_thread_not_nested_save: MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer MOV.L [R2], R2 - CMP #0,R2 ; Is it NULL? + CMP #0,R2 ; Is it NULL? BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore ; ; /* Move stack frame over to the current threads stack. */ @@ -142,9 +130,9 @@ __tx_thread_not_nested_save: MOV.L 12[R0], R2 MOV.L R2, [-R1] ; Save PC on thread stack MOV.L 8[R0], R2 - MOV.L R2, [-R1] ; Save R2 on thread stack + MOV.L R2, [-R1] ; Save R2 on thread stack MOV.L 4[R0], R2 - MOV.L R2, [-R1] ; Save R1 on thread stack + MOV.L R2, [-R1] ; Save R1 on thread stack MOV.L R5, [-R1] ; Save R5 on thread stack MOV.L R4, [-R1] ; Save R4 on thread stack MOV.L R3, [-R1] ; Save R3 on thread stack @@ -152,9 +140,9 @@ __tx_thread_not_nested_save: MOV.L R14, [-R1] ; Save R14 on thread stack MVFC FPSW, R3 MOV.L R3, [-R1] ; Save FPSW on thread stack - + POP R2 ; Pick up return address from interrupt stack - ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom + ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom MVTC R1, USP ; Set user/thread stack pointer JMP R2 ; Return to ISR @@ -171,6 +159,6 @@ __tx_thread_idle_system_save: JMP R1 ; Return to caller ; ; } -;} +;} END diff --git a/ports/rxv3/iar/src/tx_thread_interrupt_control.s b/ports/rxv3/iar/src/tx_thread_interrupt_control.s index 9db56216..b642cd22 100644 --- a/ports/rxv3/iar/src/tx_thread_interrupt_control.s +++ b/ports/rxv3/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,50 +28,38 @@ ;#include "tx_thread.h" ; section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ public __tx_thread_interrupt_control @@ -79,20 +67,20 @@ __tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ ; - + MVFC PSW, R2 ; Save PSW to R2 MOV.L R2, R3 ; Make a copy of PSW in r3 - + ; ; /* Apply the new interrupt posture. */ ; - + BTST #16, R1 ; Test I bit of PSW of "new posture" - BMNE #16, R2 ; Conditionally set I bit of intermediate posture - + BMNE #16, R2 ; Conditionally set I bit of intermediate posture + MVTC R2, PSW ; Save intermediate posture to PSW - - MOV.L R3,R1 ; Get original SR + + MOV.L R3,R1 ; Get original SR RTS ; Return to caller ;} END diff --git a/ports/rxv3/iar/src/tx_thread_schedule.s b/ports/rxv3/iar/src/tx_thread_schedule.s index 37f82438..5df75776 100644 --- a/ports/rxv3/iar/src/tx_thread_schedule.s +++ b/ports/rxv3/iar/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,52 +41,41 @@ section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_schedule RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ public __tx_thread_schedule @@ -104,7 +93,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready #if (TX_LOW_POWER == 1) MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -133,7 +122,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ @@ -145,7 +134,7 @@ __tx_thread_thread_ready: ; /* Increment the run count for this thread. */ ; _tx_thread_current_ptr -> tx_thread_run_count++; ; - MOV.L 4[R2],R3 ; Pickup run count + MOV.L 4[R2],R3 ; Pickup run count ADD #1,R3 ; Increment run counter MOV.L R3,4[R2] ; Store it back in control block ; @@ -154,7 +143,7 @@ __tx_thread_thread_ready: ; MOV.L 24[R2],R3 ; Pickup thread time-slice MOV.L #__tx_timer_time_slice,R4 ; Pickup pointer to time-slice - MOV.L R3, [R4] ; Setup time-slice + MOV.L R3, [R4] ; Setup time-slice ; ; /* Switch to the thread's stack. */ ; SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; @@ -180,12 +169,12 @@ __tx_thread_schedule_fpu_skip: MVTACLO R3, A1 MVTACHI R2, A1 MVTACGU R1, A1 - + POPM R6-R13 ; Recover interrupt stack frame - POPC FPSW + POPC FPSW POPM R14-R15 POPM R3-R5 - POPM R1-R2 + POPM R1-R2 RTE ; Return to point of interrupt, this restores PC and PSW ; diff --git a/ports/rxv3/iar/src/tx_thread_stack_build.s b/ports/rxv3/iar/src/tx_thread_stack_build.s index a5872e63..6a1064b0 100644 --- a/ports/rxv3/iar/src/tx_thread_stack_build.s +++ b/ports/rxv3/iar/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -55,28 +55,16 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_thread_stack_build __tx_thread_stack_build: ; -; +; ; /* Build an interrupt frame. The form of the fake interrupt stack ; on the Renesas RX should look like the following after it is built: -; +; ; Stack Top: ACC0 ; ACC1 ; R6 @@ -112,22 +100,22 @@ __tx_thread_stack_build: MOV.L R2, [-R3] ; Initial PC MOV.L #0, R4 MOV.L R4,[-R3] ; Initial R2 ... - MOV.L R4,[-R3] ; Initial R1 ... + MOV.L R4,[-R3] ; Initial R1 ... MOV.L R4,[-R3] ; Initial R5 ... MOV.L R4,[-R3] ; Initial R4 ... - MOV.L R4,[-R3] ; Initial R3 ... + MOV.L R4,[-R3] ; Initial R3 ... MOV.L R4,[-R3] ; Initial R15 ... MOV.L R4,[-R3] ; Initial R14 ... MVFC FPSW, r4 MOV.L R4, [-R3] ; Initial FPSW MOV.L #0, R4 - MOV.L R4,[-R3] ; Initial R13 ... + MOV.L R4,[-R3] ; Initial R13 ... MOV.L R4,[-R3] ; Initial R12 ... MOV.L R4,[-R3] ; Initial R11 ... - MOV.L R4,[-R3] ; Initial R10 ... + MOV.L R4,[-R3] ; Initial R10 ... MOV.L R4,[-R3] ; Initial R9 ... MOV.L R4,[-R3] ; Initial R8 ... - MOV.L R4,[-R3] ; Initial R7 ... + MOV.L R4,[-R3] ; Initial R7 ... MOV.L R4,[-R3] ; Initial R6 ... MOV.L R4,[-R3] ; Accumulator 1 @@ -139,11 +127,11 @@ __tx_thread_stack_build: MOV.L R4,[-R3] ; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} END diff --git a/ports/rxv3/iar/src/tx_thread_system_return.s b/ports/rxv3/iar/src/tx_thread_system_return.s index 160d90c3..05d20217 100644 --- a/ports/rxv3/iar/src/tx_thread_system_return.s +++ b/ports/rxv3/iar/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,7 +20,7 @@ ;/**************************************************************************/ section .text:CODE:ROOT - + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ @@ -54,18 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_thread_system_return diff --git a/ports/rxv3/iar/src/tx_timer_interrupt.s b/ports/rxv3/iar/src/tx_timer_interrupt.s index 78f0cf98..f96c2317 100644 --- a/ports/rxv3/iar/src/tx_timer_interrupt.s +++ b/ports/rxv3/iar/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -74,20 +74,6 @@ SWI0 EQU 0x872E0 ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_timer_interrupt @@ -150,14 +136,14 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; ; MOV.L #__tx_timer_expired,R2 ; Build address of expired flag MOV.L #1, R1 ; Build expired value - MOV.L R1, [R2] + MOV.L R1, [R2] BRA __tx_timer_done ; Finished with timer processing ; ; } @@ -168,7 +154,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -187,9 +173,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 - MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + MOV.L #__tx_timer_current_ptr,R1 + MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -223,14 +209,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing @@ -249,7 +235,7 @@ __tx_timer_dont_activate: MOV.L #SWI0, R1 MOV.L #1, [R1] - + ; } ; __tx_timer_not_ts_expiration: |