Merge pull request #510 from eclipse-threadx/devv6.5.0.202601_rel

Merge changes ahead of the v6.5.0.202601 release

18 files changed, 133 insertions, 245 deletions

diff --git a/ports/xtensa/xcc/src/tx_clib_lock.c b/ports/xtensa/xcc/src/tx_clib_lock.c
index b95bf12b..9e308720 100644
--- a/ports/xtensa/xcc/src/tx_clib_lock.c
+++ b/ports/xtensa/xcc/src/tx_clib_lock.c
@@ -30,16 +30,6 @@
 /*    operation of the C library. Both newlib and the Xtensa C Library    */
 /*    are supported.                                                      */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*  12-31-2023     Xiuwen Cai               Modified comment(s), and      */
-/*                                            added error handling in     */
-/*                                            lock initialization,        */
-/*                                            resulting in version 6.4.0  */
-/*                                                                        */
 /**************************************************************************/
 
 #include "tx_api.h"     /* TX_THREAD_SAFE_CLIB may be defined by tx_port.h */
@@ -137,7 +127,7 @@ __env_unlock (struct _reent * ptr)
 
 #include <errno.h>
 #include <sys/reent.h>
-    
+
 #define XT_NUM_CLIB_LOCKS      (_MAX_LOCK + FOPEN_MAX)
 
 typedef TX_MUTEX * _Rmtx;
diff --git a/ports/xtensa/xcc/src/tx_initialize_low_level.c b/ports/xtensa/xcc/src/tx_initialize_low_level.c
index eebae217..de2c2b93 100644
--- a/ports/xtensa/xcc/src/tx_initialize_low_level.c
+++ b/ports/xtensa/xcc/src/tx_initialize_low_level.c
@@ -48,15 +48,6 @@ int32_t xt_timer_intnum = -1;
 /*    available RAM memory address for tx_application_define.             */
 /*    It also sets the default heap region for the optional C library.    */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020      Cadence Design Systems  Initial Version 6.1.3         */
-/*  04-25-2022      Scott Larson            Modified comments and updated */
-/*                                            function names,             */
-/*                                            resulting in version 6.1.11 */
-/*                                                                        */
 /**************************************************************************/
 VOID   _tx_initialize_low_level(VOID)
 {
@@ -123,8 +114,8 @@ VOID   _tx_initialize_low_level(VOID)
     Initialize co-processor management for threads. Leave CPENABLE alone.
     This is called from a normal Xtensa single-threaded run-time environment
     before multi-threading has commenced. All co-processors are enabled.
-    It is important NOT to clear CPENABLE yet because tx_application_define() 
-    is user code which might use a co-processor. The co-processor exception 
+    It is important NOT to clear CPENABLE yet because tx_application_define()
+    is user code which might use a co-processor. The co-processor exception
     handler does not expect to be called outside a thread.
     */
     _xt_coproc_init();
diff --git a/ports/xtensa/xcc/src/tx_thread_context_restore.S b/ports/xtensa/xcc/src/tx_thread_context_restore.S
index c36f0a5c..89a66b35 100644
--- a/ports/xtensa/xcc/src/tx_thread_context_restore.S
+++ b/ports/xtensa/xcc/src/tx_thread_context_restore.S
@@ -1,10 +1,11 @@
 /***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation 
- * 
+ * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (c) 2026-present Eclipse ThreadX contributors
+ *
  * This program and the accompanying materials are made available under the
  * terms of the MIT License which is available at
  * https://opensource.org/licenses/MIT.
- * 
+ *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
@@ -59,11 +60,6 @@
 /*    preemption is necessary.  Otherwise, if preemption is necessary or  */
 /*    if no thread was running, the function returns to the scheduler.    */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*  12-31-2020      Cadence Design Systems  Initial Version 6.1.3         */
-/*  10-31-2022      Scott Larson            Updated EPK definitions,      */
-/*                                            resulting in version 6.2.0  */
-/*                                                                        */
 /**************************************************************************/
 
 //  VOID   _tx_thread_context_restore(VOID)
diff --git a/ports/xtensa/xcc/src/tx_thread_context_save.S b/ports/xtensa/xcc/src/tx_thread_context_save.S
index 109b954f..397ea822 100644
--- a/ports/xtensa/xcc/src/tx_thread_context_save.S
+++ b/ports/xtensa/xcc/src/tx_thread_context_save.S
@@ -1,10 +1,11 @@
 /***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation 
- * 
+ * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (c) 2026-present Eclipse ThreadX contributors
+ *
  * This program and the accompanying materials are made available under the
  * terms of the MIT License which is available at
  * https://opensource.org/licenses/MIT.
- * 
+ *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
@@ -33,8 +34,8 @@
 
 /**************************************************************************/
 /**************************************************************************/
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
+/**                                                                       */
+/** ThreadX Component                                                     */
 /**                                                                       */
 /**   Thread                                                              */
 /**                                                                       */
@@ -49,23 +50,17 @@
 
     .text
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  DESCRIPTION                                                           */ 
-/*                                                                        */ 
-/*    This function saves the context of an executing thread in the       */ 
-/*    beginning of interrupt processing.  The function also ensures that  */ 
-/*    the system stack is used upon return to the calling ISR.            */ 
-/*                                                                        */ 
-/*    Interrupts remain disabled and no exceptions are triggered!         */ 
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
-/*    DATE              NAME                      DESCRIPTION             */ 
-/*                                                                        */ 
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */ 
-/**************************************************************************/ 
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function saves the context of an executing thread in the       */
+/*    beginning of interrupt processing.  The function also ensures that  */
+/*    the system stack is used upon return to the calling ISR.            */
+/*                                                                        */
+/*    Interrupts remain disabled and no exceptions are triggered!         */
+/*                                                                        */
+/**************************************************************************/
 
 //  VOID   _tx_thread_context_save(VOID)
 //  {
@@ -77,13 +72,13 @@ _tx_thread_context_save:
     /*
     Please note: Control flow might seem strange. This is because it has been
     optimized to avoid taken branches in the longest normal path (the critical
-    one for worst-case latency), presumed to be a non-nested interrupt and 
+    one for worst-case latency), presumed to be a non-nested interrupt and
     non-idle) and to hide pipeline interlock cycles where possible.
     */
 
     /*
     Save a couple of scratch regs to work with that are preserved over the
-    call to _xt_context_save. The latter assumes the interruptee's values 
+    call to _xt_context_save. The latter assumes the interruptee's values
     of these are already saved and these regs contain different data to be
     preserved, so doesn't save them in the stack frame, and thereby requires
     that its caller have already saved them in the interrupt stack frame.
@@ -107,7 +102,7 @@ _tx_thread_context_save:
 .Ln_tx_thread_not_nested_save:
 
     /* Otherwise, not nested, check to see if a thread was running. */
-    //  else 
+    //  else
     //  {
     //      if (_tx_thread_current_ptr)
     //      {
@@ -127,10 +122,10 @@ _tx_thread_context_save:
 
 .L_tx_thread_idle_system_save:
 
-    /* 
+    /*
     If interrupted in the idle state, it's not necessary to save any context.
-    But even in the idle case where we are already on the system stack, it is 
-    necessary to reset the (system) stack pointer so a series of consecutive 
+    But even in the idle case where we are already on the system stack, it is
+    necessary to reset the (system) stack pointer so a series of consecutive
     interrupts in the idle state do not keep moving the SP downward.
     */
 
@@ -146,7 +141,7 @@ _tx_thread_context_save:
     /* Nested interrupt condition. */
     /* Save the rest of the interrupted context and return to ISR. */
     call0   _xt_context_save
-    
+
     mov     a0,  a12                     /* retrieve return address */
     ret
 
diff --git a/ports/xtensa/xcc/src/tx_thread_interrupt_control.c b/ports/xtensa/xcc/src/tx_thread_interrupt_control.c
index dfc9552d..3a0cae27 100644
--- a/ports/xtensa/xcc/src/tx_thread_interrupt_control.c
+++ b/ports/xtensa/xcc/src/tx_thread_interrupt_control.c
@@ -1,10 +1,11 @@
 /***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation 
- * 
+ * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (c) 2026-present Eclipse ThreadX contributors
+ *
  * This program and the accompanying materials are made available under the
  * terms of the MIT License which is available at
  * https://opensource.org/licenses/MIT.
- * 
+ *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
@@ -33,8 +34,8 @@
 
 /**************************************************************************/
 /**************************************************************************/
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
+/**                                                                       */
+/** ThreadX Component                                                     */
 /**                                                                       */
 /**   Thread                                                              */
 /**                                                                       */
@@ -46,21 +47,15 @@
 #include "xtensa_rtos.h"
 
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  DESCRIPTION                                                           */ 
-/*                                                                        */ 
-/*    This function is responsible for changing the interrupt lockout     */ 
-/*    posture of the system.                                              */ 
-/*    NOTE: In earlier versions this was implemented in assembly.         */ 
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
-/*    DATE              NAME                      DESCRIPTION             */ 
-/*                                                                        */ 
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */ 
-/**************************************************************************/ 
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for changing the interrupt lockout     */
+/*    posture of the system.                                              */
+/*    NOTE: In earlier versions this was implemented in assembly.         */
+/*                                                                        */
+/**************************************************************************/
 
 UINT   _tx_thread_interrupt_control(UINT new_posture)
 {
diff --git a/ports/xtensa/xcc/src/tx_thread_schedule.S b/ports/xtensa/xcc/src/tx_thread_schedule.S
index a98d7495..448dc6d7 100644
--- a/ports/xtensa/xcc/src/tx_thread_schedule.S
+++ b/ports/xtensa/xcc/src/tx_thread_schedule.S
@@ -1,10 +1,11 @@
 /***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation 
- * 
+ * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (c) 2026-present Eclipse ThreadX contributors
+ *
  * This program and the accompanying materials are made available under the
  * terms of the MIT License which is available at
  * https://opensource.org/licenses/MIT.
- * 
+ *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
@@ -56,14 +57,6 @@
 /*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
 /*    in the variable, the corresponding thread is resumed.               */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020      Cadence Design Systems  Initial Version 6.1.3         */
-/*  10-31-2022      Scott Larson            Updated EPK definitions,      */
-/*                                            resulting in version 6.2.0  */
-/*                                                                        */
 /**************************************************************************/
 
 //  VOID   _tx_thread_schedule(VOID)
diff --git a/ports/xtensa/xcc/src/tx_thread_stack_build.S b/ports/xtensa/xcc/src/tx_thread_stack_build.S
index 53d7e1c6..a52fc35e 100644
--- a/ports/xtensa/xcc/src/tx_thread_stack_build.S
+++ b/ports/xtensa/xcc/src/tx_thread_stack_build.S
@@ -1,10 +1,11 @@
 /***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation 
- * 
+ * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (c) 2026-present Eclipse ThreadX contributors
+ *
  * This program and the accompanying materials are made available under the
  * terms of the MIT License which is available at
  * https://opensource.org/licenses/MIT.
- * 
+ *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
@@ -33,8 +34,8 @@
 
 /**************************************************************************/
 /**************************************************************************/
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
+/**                                                                       */
+/** ThreadX Component                                                     */
 /**                                                                       */
 /**   Thread                                                              */
 /**                                                                       */
@@ -47,21 +48,15 @@
 
     .text
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  DESCRIPTION                                                           */ 
-/*                                                                        */ 
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
 /*    This function builds a stack frame on the supplied thread's stack.  */
 /*    The stack frame looks like an interrupt frame or a solicited frame  */
-/*    depending on the exception architecture of the target hardware.     */ 
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
-/*    DATE              NAME                      DESCRIPTION             */ 
-/*                                                                        */ 
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */ 
-/**************************************************************************/ 
+/*    depending on the exception architecture of the target hardware.     */
+/*                                                                        */
+/**************************************************************************/
 
 //  VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
 //  {
diff --git a/ports/xtensa/xcc/src/tx_thread_system_return.S b/ports/xtensa/xcc/src/tx_thread_system_return.S
index 38330082..d1fc4a9f 100644
--- a/ports/xtensa/xcc/src/tx_thread_system_return.S
+++ b/ports/xtensa/xcc/src/tx_thread_system_return.S
@@ -1,10 +1,11 @@
 /***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation 
- * 
+ * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (c) 2026-present Eclipse ThreadX contributors
+ *
  * This program and the accompanying materials are made available under the
  * terms of the MIT License which is available at
  * https://opensource.org/licenses/MIT.
- * 
+ *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
@@ -56,13 +57,6 @@
 /*    is saved since the compiler assumes temp registers are going to get */
 /*    slicked by a function call anyway.                                  */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*  12-31-2020      Cadence Design Systems  Initial Version 6.1.3         */
-/*  10-31-2022      Scott Larson            Updated EPK definitions,      */
-/*                                            resulting in version 6.2.0  */
-/*                                                                        */
 /**************************************************************************/
 
 //  VOID   _tx_thread_system_return(VOID)
diff --git a/ports/xtensa/xcc/src/tx_timer_interrupt.S b/ports/xtensa/xcc/src/tx_timer_interrupt.S
index 7cca247c..d09badde 100644
--- a/ports/xtensa/xcc/src/tx_timer_interrupt.S
+++ b/ports/xtensa/xcc/src/tx_timer_interrupt.S
@@ -1,10 +1,11 @@
 /***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation 
- * 
+ * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (c) 2026-present Eclipse ThreadX contributors
+ *
  * This program and the accompanying materials are made available under the
  * terms of the MIT License which is available at
  * https://opensource.org/licenses/MIT.
- * 
+ *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
@@ -33,8 +34,8 @@
 
 /**************************************************************************/
 /**************************************************************************/
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
+/**                                                                       */
+/** ThreadX Component                                                     */
 /**                                                                       */
 /**   Timer                                                               */
 /**                                                                       */
@@ -49,26 +50,17 @@
 
     .text
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  DESCRIPTION                                                           */ 
-/*                                                                        */ 
-/*    This function processes the hardware timer interrupt.  This         */ 
-/*    processing includes incrementing the system clock and checking for  */ 
-/*    time slice and/or timer expiration.  If either is found, the        */ 
-/*    interrupt context save/restore functions are called along with the  */ 
-/*    expiration functions.                                               */ 
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
-/*    DATE              NAME                      DESCRIPTION             */ 
-/*                                                                        */ 
-/*  12-31-2020      Cadence Design Systems  Initial Version 6.1.3         */
-/*  04-25-2022      Scott Larson            Modified comments and updated */
-/*                                            function name,              */
-/*                                            resulting in version 6.1.11 */
-/*                                                                        */ 
-/**************************************************************************/ 
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function processes the hardware timer interrupt.  This         */
+/*    processing includes incrementing the system clock and checking for  */
+/*    time slice and/or timer expiration.  If either is found, the        */
+/*    interrupt context save/restore functions are called along with the  */
+/*    expiration functions.                                               */
+/*                                                                        */
+/**************************************************************************/
 
 //  VOID   _tx_timer_interrupt(VOID)
 //  {
@@ -99,13 +91,13 @@ _tx_timer_interrupt:
 
     /*
     Xtensa timers work by comparing a cycle counter with a preset value.
-    Once the match occurs an interrupt is generated, and the handler has 
+    Once the match occurs an interrupt is generated, and the handler has
     to set a new cycle count into the comparator. To avoid clock drift
     due to interrupt latency, the new cycle count is computed from the old,
-    not the time the interrupt was serviced. However if a timer interrupt 
+    not the time the interrupt was serviced. However if a timer interrupt
     is ever serviced more than one tick late, it is necessary to process
-    multiple ticks until the new cycle count is in the future, otherwise 
-    the next timer interrupt would not occur until after the cycle counter 
+    multiple ticks until the new cycle count is in the future, otherwise
+    the next timer interrupt would not occur until after the cycle counter
     had wrapped (2^32 cycles later).
 
     do {
diff --git a/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c b/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c
index 012b3612..a46f65cc 100644
--- a/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c
+++ b/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c
@@ -1,10 +1,11 @@
 /***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation 
- * 
+ * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (c) 2026-present Eclipse ThreadX contributors
+ *
  * This program and the accompanying materials are made available under the
  * terms of the MIT License which is available at
  * https://opensource.org/licenses/MIT.
- * 
+ *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
@@ -33,8 +34,8 @@
 
 /**************************************************************************/
 /**************************************************************************/
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
+/**                                                                       */
+/** ThreadX Component                                                     */
 /**                                                                       */
 /**   Support for Xtensa applications                                     */
 /**                                                                       */
@@ -65,10 +66,10 @@
 #include <unistd.h>
 
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  DESCRIPTION                                                           */ 
-/*                                                                        */ 
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
 /*    Callback to notify of a stack overflow when registered with         */
 /*    tx_stack_error_notify and stack checking is enabled (ThreadX        */
 /*    is compiled with TX_ENABLE_STACK_CHECKING defined).                 */
@@ -85,20 +86,14 @@
 /*    - Passes control to the debugger (if attached).                     */
 /*    - Terminates the simulation (simulator only).                       */
 /*    - Panics.                                                           */
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
-/*    DATE              NAME                      DESCRIPTION             */ 
-/*                                                                        */ 
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */ 
-/**************************************************************************/ 
+/*                                                                        */
+/**************************************************************************/
 
 VOID  _tx_xtensa_stack_error_handler(TX_THREAD * thread)
 {
     #ifdef XT_SIMULATOR
     register int32_t sc  __asm__ ("a2") = SYS_log_msg;
-    register char *  msg __asm__ ("a3") 
+    register char *  msg __asm__ ("a3")
         = "**** Stack overflow in thread 0x%08x.\n";
     register TX_THREAD * thd __asm__ ("a4") = thread;
     __asm__ volatile ("simcall" :: "a" (sc), "a" (msg), "a" (thd) );
diff --git a/ports/xtensa/xcc/src/xtensa_context.S b/ports/xtensa/xcc/src/xtensa_context.S
index af3138aa..e4b9aa0a 100644
--- a/ports/xtensa/xcc/src/xtensa_context.S
+++ b/ports/xtensa/xcc/src/xtensa_context.S
@@ -41,12 +41,6 @@
 /* anyway, and are always restored even in Call0 ABI. Only A14, A15 are   */
 /* truly handled as callee-save regs.                                     */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */
 /**************************************************************************/
 
 
@@ -71,7 +65,7 @@ interrupt stack frame defined in xtensa_rtos.h.
 Its counterpart is _xt_context_restore (which also restores A12, A13).
 
 Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
-This function preserves A12 & A13 in order to provide the caller with 2 scratch 
+This function preserves A12 & A13 in order to provide the caller with 2 scratch
 regs that need not be saved over the call to this function. The choice of which
 2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
 to avoid moving data more than necessary. Caller can assign regs accordingly.
@@ -80,7 +74,7 @@ Entry Conditions:
     A0  = Return address in caller.
     A1  = Stack pointer of interrupted thread or handler ("interruptee").
     Original A12, A13 have already been saved in the interrupt stack frame.
-    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the 
+    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
     point of interruption.
     If windowed ABI, PS.EXCM = 1 (exceptions disabled).
 
@@ -156,8 +150,8 @@ _xt_context_save:
     and underflow exceptions disabled (assured by PS.EXCM == 1).
     */
     s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
-    s32i    a13, sp, XT_STK_TMP1    
-    s32i    a9,  sp, XT_STK_TMP2    
+    s32i    a13, sp, XT_STK_TMP1
+    s32i    a9,  sp, XT_STK_TMP2
 
     /*
     Save the overlay state if we are supporting overlays. Since we just saved
@@ -177,12 +171,12 @@ _xt_context_save:
     call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
     addi    sp,  sp, -XT_STK_FRMSZ
     l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
-    l32i    a13, sp, XT_STK_TMP1    
-    l32i    a9,  sp, XT_STK_TMP2    
+    l32i    a13, sp, XT_STK_TMP1
+    l32i    a9,  sp, XT_STK_TMP2
     #endif
 
     #if XCHAL_EXTRA_SA_SIZE > 0
-    /*  
+    /*
     NOTE: Normally the xthal_save_extra_nw macro only affects address
     registers a2-a5. It is theoretically possible for Xtensa processor
     designers to write TIE that causes more address registers to be
@@ -212,7 +206,7 @@ _xt_context_restore
     !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
 
 Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
-ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt 
+ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
 stack frame defined in xtensa_rtos.h .
 Its counterpart is _xt_context_save (whose caller saved A12, A13).
 
@@ -225,7 +219,7 @@ Entry Conditions:
 Exit conditions:
     A0  = Return address in caller.
     A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    Other processor state except PC, PS, A0, A1 (SP), is as at the point 
+    Other processor state except PC, PS, A0, A1 (SP), is as at the point
     of interruption.
 
 *******************************************************************************/
@@ -236,7 +230,7 @@ Exit conditions:
 _xt_context_restore:
 
     #if XCHAL_EXTRA_SA_SIZE > 0
-    /*  
+    /*
     NOTE: Normally the xthal_restore_extra_nw macro only affects address
     registers a2-a5. It is theoretically possible for Xtensa processor
     designers to write TIE that causes more address registers to be
@@ -312,7 +306,7 @@ _xt_context_restore:
 
     /*
     Call0 ABI callee-saved regs a12-15 do not need to be restored here.
-    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), 
+    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
     so need to be restored anyway, despite being callee-saved in Call0.
     */
     l32i    a12, sp, XT_STK_A12
@@ -337,7 +331,7 @@ to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
 Called during initialization of the RTOS, before any threads run.
 
 This may be called from normal Xtensa single-threaded application code which
-might use co-processors. The Xtensa run-time initialization enables all 
+might use co-processors. The Xtensa run-time initialization enables all
 co-processors. They must remain enabled here, else a co-processor exception
 might occur outside of a thread, which the exception handler doesn't expect.
 
@@ -378,13 +372,13 @@ _xt_coproc_init:
 
 _xt_coproc_release
 
-Releases any and all co-processors owned by a given thread. The thread is 
+Releases any and all co-processors owned by a given thread. The thread is
 identified by it's co-processor state save area defined in xtensa_context.h .
 
 Must be called before a thread's co-proc save area is deleted to avoid
 memory corruption when the exception handler tries to save the state.
 May be called when a thread terminates or completes but does not delete
-the co-proc save area, to avoid the exception handler having to save the 
+the co-proc save area, to avoid the exception handler having to save the
 thread's co-proc state before another thread can use it (optimization).
 
 Entry Conditions:
diff --git a/ports/xtensa/xcc/src/xtensa_coproc_handler.S b/ports/xtensa/xcc/src/xtensa_coproc_handler.S
index 33de2070..0540d633 100644
--- a/ports/xtensa/xcc/src/xtensa_coproc_handler.S
+++ b/ports/xtensa/xcc/src/xtensa_coproc_handler.S
@@ -28,12 +28,6 @@
 /*    Xtensa coprocessor handling routines. This code is only active if   */
 /*    one or more coprocessors are present.                               */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */
 /**************************************************************************/
 
 
@@ -225,7 +219,7 @@ _xt_coproc_handler:
 
 _tx_thread_coproc_state:
 
-        // return ( _tx_thread_system_state == 0 && _tx_thread_current_ptr != 0 
+        // return ( _tx_thread_system_state == 0 && _tx_thread_current_ptr != 0
         //          ? (&_tx_thread_current_ptr->tx_thread_cp_state) : 0 )
 
         movi    a15, _tx_thread_system_state    // check if interrupt state
@@ -512,15 +506,15 @@ _xt_coproc_exc:
         .global     _xt_coproc_exc
         .type       _xt_coproc_exc,@function
         .align      4
-  
+
 _xt_coproc_exc:
-    
+
         mov     a0, sp                          // Allocate stack frame
         addi    sp, sp, -XT_STK_FRMSZ
         s32i    a0, sp, XT_STK_A1               // save SP
 #if XCHAL_HAVE_WINDOWED
         s32e    a0, sp, -12                     // for debug backtrace
-#endif  
+#endif
         rsr     a0, PS
         s32i    a0, sp, XT_STK_PS               // save PS
         rsr     a0, EPC_1
diff --git a/ports/xtensa/xcc/src/xtensa_init.c b/ports/xtensa/xcc/src/xtensa_init.c
index 298ca28d..d153ad35 100644
--- a/ports/xtensa/xcc/src/xtensa_init.c
+++ b/ports/xtensa/xcc/src/xtensa_init.c
@@ -27,12 +27,6 @@
 /*                                                                        */
 /*    Xtensa initialization routines.                                     */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */
 /**************************************************************************/
 
 
@@ -49,7 +43,7 @@
 uint32_t xt_tick_divisor = 0;  /* cached number of cycles per tick */
 
 /*
-Compute and initialize at run-time the tick divisor (the number of 
+Compute and initialize at run-time the tick divisor (the number of
 processor clock cycles in an RTOS tick, used to set the tick timer).
 Called when the processor clock frequency is not known at compile-time.
 */
diff --git a/ports/xtensa/xcc/src/xtensa_intr_asm.S b/ports/xtensa/xcc/src/xtensa_intr_asm.S
index 78fd8a70..e972378a 100644
--- a/ports/xtensa/xcc/src/xtensa_intr_asm.S
+++ b/ports/xtensa/xcc/src/xtensa_intr_asm.S
@@ -28,12 +28,6 @@
 /*    Xtensa interrupt handling data and assembly routines.               */
 /*    Also see xtensa_intr.c.                                             */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */
 /**************************************************************************/
 
 
diff --git a/ports/xtensa/xcc/src/xtensa_intr_wrapper.c b/ports/xtensa/xcc/src/xtensa_intr_wrapper.c
index ff70f4ea..4ccb29f5 100644
--- a/ports/xtensa/xcc/src/xtensa_intr_wrapper.c
+++ b/ports/xtensa/xcc/src/xtensa_intr_wrapper.c
@@ -27,12 +27,6 @@
 /*                                                                        */
 /*  Xtensa-specific interrupt handler wrapper.                            */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */
 /**************************************************************************/
 
 
diff --git a/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c b/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c
index 8fd92701..4a63479c 100644
--- a/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c
+++ b/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c
@@ -27,12 +27,6 @@
 /*                                                                        */
 /*  Xtensa overlay manager OS hooks for ThreadX. XEA2 only.               */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */
 /**************************************************************************/
 
 
@@ -45,7 +39,7 @@
 /* Required to work around a bug in the overlay header. */
 #ifdef XT_DISABLE_OVERLAYS
 #undef  xt_overlay_fatal_error
-#define xt_overlay_fatal_error(id)    
+#define xt_overlay_fatal_error(id)
 #endif
 
 
@@ -67,7 +61,7 @@ xt_overlay_init_os(void)
     /* Create the mutex for overlay access. Priority inheritance is
      * required.
      */
-    UINT status = 
+    UINT status =
         tx_mutex_create (&xt_overlay_mutex, "xt_overlay_lock", TX_INHERIT);
 
     if (status != TX_SUCCESS) {
diff --git a/ports/xtensa/xcc/src/xtensa_vectors.S b/ports/xtensa/xcc/src/xtensa_vectors.S
index b115abf5..7b09638e 100644
--- a/ports/xtensa/xcc/src/xtensa_vectors.S
+++ b/ports/xtensa/xcc/src/xtensa_vectors.S
@@ -64,12 +64,6 @@
 /*  changes to the saved state in the exception frame, the changes will   */
 /*  be applied when restoring the context.                                */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */
 /**************************************************************************/
 
 
@@ -297,7 +291,7 @@
 /*
 --------------------------------------------------------------------------------
   Panic handler.
-  Should be reached by call0 (preferable) or jump only. If call0, a0 says where 
+  Should be reached by call0 (preferable) or jump only. If call0, a0 says where
   from. If on simulator, display panic message and abort, else loop indefinitely.
 --------------------------------------------------------------------------------
 */
@@ -331,7 +325,7 @@ _xt_panic_message:
 --------------------------------------------------------------------------------
     Hooks to dynamically install handlers for exceptions and interrupts.
     Allows automated regression frameworks to install handlers per test.
-    Consists of an array of function pointers indexed by interrupt level, 
+    Consists of an array of function pointers indexed by interrupt level,
     with index 0 containing the entry for user exceptions.
     Initialized with all 0s, meaning no handler is installed at each level.
     See comment in xtensa_rtos.h for more details.
@@ -363,7 +357,7 @@ _xt_intexc_hooks:
   the appropriate stack frame, saves a few vector-specific registers and
   calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
   and enter the RTOS, then sets up a C environment. It then calls the
-  user's interrupt handler code (which may be coded in C) and finally 
+  user's interrupt handler code (which may be coded in C) and finally
   calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
 
   While XT_RTOS_INT_EXIT does not return directly to the interruptee,
@@ -742,7 +736,7 @@ _xt_syscall_exc:
 -------------------------------------------------------------------------------
 */
 
-    .text   
+    .text
     .type       _xt_lowint1,@function
     .align      4
 
@@ -762,12 +756,12 @@ _xt_lowint1:
     /* Save rest of interrupt context and enter RTOS. */
     call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
 
-    /* !! We are now on the RTOS system stack !! */ 
+    /* !! We are now on the RTOS system stack !! */
 
     /* Set up PS for C, enable interrupts above this level and clear EXCM. */
     #ifdef __XTENSA_CALL0_ABI__
     movi    a0, PS_INTLEVEL(1) | PS_UM
-    #else 
+    #else
     movi    a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
     #endif
     wsr     a0, PS
@@ -799,7 +793,7 @@ _xt_lowint1:
   the appropriate stack frame, saves a few vector-specific registers and
   calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
   and enter the RTOS, then sets up a C environment. It then calls the
-  user's interrupt handler code (which may be coded in C) and finally 
+  user's interrupt handler code (which may be coded in C) and finally
   calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
 
   While XT_RTOS_INT_EXIT does not return directly to the interruptee,
@@ -1181,7 +1175,7 @@ and used for purposes requiring very short service times.
 
 Here are templates for high priority (level 2+) interrupt vectors.
 They assume only one interrupt per level to avoid the burden of identifying
-which interrupts at this level are pending and enabled. This allows for 
+which interrupts at this level are pending and enabled. This allows for
 minimum latency and avoids having to save/restore a2 in addition to a0.
 If more than one interrupt per high priority level is configured, this burden
 is on the handler which in any case must provide a way to save and restore
@@ -1444,12 +1438,12 @@ _xt_nmi:
 
 WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
 
-Here is the code for each window overflow/underflow exception vector and 
+Here is the code for each window overflow/underflow exception vector and
 (interspersed) efficient code for handling the alloca exception cause.
 Window exceptions are handled entirely in the vector area and are very
-tight for performance. The alloca exception is also handled entirely in 
+tight for performance. The alloca exception is also handled entirely in
 the window vector area so comes at essentially no cost in code size.
-Users should never need to modify them and Cadence Design Systems recommends 
+Users should never need to modify them and Cadence Design Systems recommends
 they do not.
 
 Window handlers go at predetermined vector locations according to the
diff --git a/ports/xtensa/xcc/src/xtensa_vectors_xea3.S b/ports/xtensa/xcc/src/xtensa_vectors_xea3.S
index 9a25dcee..22d9db89 100644
--- a/ports/xtensa/xcc/src/xtensa_vectors_xea3.S
+++ b/ports/xtensa/xcc/src/xtensa_vectors_xea3.S
@@ -52,12 +52,6 @@
 /*  changes to the saved state in the exception frame, the changes will   */
 /*  be applied when restoring the context.                                */
 /*                                                                        */
-/*  RELEASE HISTORY                                                       */
-/*                                                                        */
-/*    DATE              NAME                      DESCRIPTION             */
-/*                                                                        */
-/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
-/*                                                                        */
 /**************************************************************************/