Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

16 files changed, 116 insertions, 325 deletions

diff --git a/ports_arch/ARMv8-M/threadx/ac6/CMakeLists.txt b/ports_arch/ARMv8-M/threadx/ac6/CMakeLists.txt
index 5ad3b8e7..81b479e0 100644
--- a/ports_arch/ARMv8-M/threadx/ac6/CMakeLists.txt
+++ b/ports_arch/ARMv8-M/threadx/ac6/CMakeLists.txt
@@ -16,6 +16,8 @@ target_sources(${PROJECT_NAME} PRIVATE
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
 )
 
-target_include_directories(${PROJECT_NAME} PUBLIC
+target_include_directories(${PROJECT_NAME}
+    SYSTEM
+    PUBLIC
     inc
 )
diff --git a/ports_arch/ARMv8-M/threadx/ac6/readme_threadx.txt b/ports_arch/ARMv8-M/threadx/ac6/readme_threadx.txt
index 87556be5..e835b109 100644
--- a/ports_arch/ARMv8-M/threadx/ac6/readme_threadx.txt
+++ b/ports_arch/ARMv8-M/threadx/ac6/readme_threadx.txt
@@ -218,7 +218,12 @@ information associated with this specific port of ThreadX:
 03-02-2021  The following files were changed/added for version 6.1.5:
             tx_port.h                       Added ULONG64_DEFINED
 
-09-30-2020  Initial ThreadX 6.1 version for Cortex-Mxx using AC6 tools.
+09-30-2020  Initial ThreadX 6.1 version of this Armv8-M port using AC6 tools.
+
+            The dates above belong to this shared port, which every Armv8-M
+            core is generated from. They are not the date a particular core
+            gained a ThreadX port: that is when its name was added to
+            scripts/copy_armv8_m.sh.
 
 
 Copyright(c) 1996-2020 Microsoft Corporation
diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S
index 9332b7e1..4e81ac67 100644
--- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S
+++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -87,25 +88,17 @@ _tx_initialize_low_level:
     ADD     r1, r1, #4                              //
     STR     r1, [r0]                                // Setup first unused memory pointer
 
-    /* Setup Vector Table Offset Register.  */
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    LDR     r1, =__Vectors                          // Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        // Set vector table address
-
     /* Enable the cycle count register.  */
     LDR     r0, =0xE0001000                         // Build address of DWT register
     LDR     r1, [r0]                                // Pickup the current value
     ORR     r1, r1, #1                              // Set the CYCCNTENA bit
     STR     r1, [r0]                                // Enable the cycle count register
 
-    /* Set system stack pointer from vector value.  */
-    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
-    LDR     r1, =__Vectors                          // Pickup address of vector table
-    LDR     r1, [r1]                                // Pickup reset stack pointer
-    STR     r1, [r0]                                // Save system stack pointer
-
     /* Configure SysTick.  */
     MOV     r0, #0xE000E000                         // Build address of NVIC registers
+    MOV     r1, #0                                  // Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         // Reset SysTick Control
+    STR     r1, [r0, #0x18]                         // Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
     MOV     r1, #0x7                                // Build SysTick Control Enable Value
diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_schedule.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_schedule.S
index 40d3282b..ba34803a 100644
--- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_schedule.S
+++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_schedule.S
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -129,7 +130,7 @@ __tx_ts_handler:
     BL      _tx_execution_thread_exit               // Call the thread exit function
     POP     {r0, lr}                                // Recover LR
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -278,9 +279,19 @@ __tx_ts_wait:
 #endif
 
 #ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+    CPSID   i                                       // Mask every interrupt with PRIMASK, which WFI ignores
+    MOV     r1, #0                                  // Clear BASEPRI so that an interrupt masked by it
+    MSR     BASEPRI, r1                             //   is still able to wake the processor
+#endif
     DSB                                             // Ensure no outstanding memory transactions
     WFI                                             // Wait for interrupt
     ISB                                             // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+    LDR     r1, =TX_PORT_BASEPRI                    // Restore the BASEPRI mask
+    MSR     BASEPRI, r1
+    CPSIE   i                                       // Clear PRIMASK; a pending interrupt is taken here
+#endif
 #endif
 
 #ifdef TX_LOW_POWER
diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S
index e31c4a55..c188969c 100644
--- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S
+++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv8-M/threadx/gnu/CMakeLists.txt b/ports_arch/ARMv8-M/threadx/gnu/CMakeLists.txt
index 5ad3b8e7..a8e45b82 100644
--- a/ports_arch/ARMv8-M/threadx/gnu/CMakeLists.txt
+++ b/ports_arch/ARMv8-M/threadx/gnu/CMakeLists.txt
@@ -1,7 +1,8 @@
-target_sources(${PROJECT_NAME} PRIVATE
+target_sources(${PROJECT_NAME}
+    PRIVATE
+    # {{BEGIN_TARGET_SOURCES}}
     ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
     ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
-    ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
@@ -14,8 +15,11 @@ target_sources(${PROJECT_NAME} PRIVATE
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
+    # {{END_TARGET_SOURCES}}
 )
 
-target_include_directories(${PROJECT_NAME} PUBLIC
-    inc
+target_include_directories(${PROJECT_NAME}
+    SYSTEM
+    PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}/inc
 )
diff --git a/ports_arch/ARMv8-M/threadx/gnu/readme_threadx.txt b/ports_arch/ARMv8-M/threadx/gnu/readme_threadx.txt
index 2cce95a4..907d6335 100644
--- a/ports_arch/ARMv8-M/threadx/gnu/readme_threadx.txt
+++ b/ports_arch/ARMv8-M/threadx/gnu/readme_threadx.txt
@@ -200,7 +200,12 @@ information associated with this specific port of ThreadX:
 03-02-2021  The following files were changed/added for version 6.1.5:
             tx_port.h                       Added ULONG64_DEFINED
 
-09-30-2020  Initial ThreadX 6.1 version for Cortex-Mxx using GNU tools.
+09-30-2020  Initial ThreadX 6.1 version of this Armv8-M port using GNU tools.
+
+            The dates above belong to this shared port, which every Armv8-M
+            core is generated from. They are not the date a particular core
+            gained a ThreadX port: that is when its name was added to
+            scripts/copy_armv8_m.sh.
 
 
 Copyright(c) 1996-2020 Microsoft Corporation
diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S
deleted file mode 100644
index 842dcdf4..00000000
--- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S
+++ /dev/null
@@ -1,273 +0,0 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
-
-
-/**************************************************************************/
-/**************************************************************************/
-/**                                                                       */
-/** ThreadX Component                                                     */
-/**                                                                       */
-/**   Initialize                                                          */
-/**                                                                       */
-/**************************************************************************/
-/**************************************************************************/
-
-#ifdef TX_INCLUDE_USER_DEFINE_FILE
-#include "tx_user.h"
-#endif
-
-SYSTEM_CLOCK        =     6000000
-SYSTICK_CYCLES      =     ((SYSTEM_CLOCK / 100) -1)
-
-/* Setup the stack and heap areas.  */
-
-STACK_SIZE          =     0x00000400
-HEAP_SIZE           =     0x00000000
-
-/**************************************************************************/
-/*                                                                        */
-/*  FUNCTION                                               RELEASE        */
-/*                                                                        */
-/*    _tx_initialize_low_level                          Cortex-Mxx/GNU    */
-/*                                                           6.2.1        */
-/*  AUTHOR                                                                */
-/*                                                                        */
-/*    Scott Larson, Microsoft Corporation                                 */
-/*                                                                        */
-/*  DESCRIPTION                                                           */
-/*                                                                        */
-/*    This function is responsible for any low-level processor            */
-/*    initialization, including setting up interrupt vectors, setting     */
-/*    up a periodic timer interrupt source, saving the system stack       */
-/*    pointer for use in ISR processing later, and finding the first      */
-/*    available RAM memory address for tx_application_define.             */
-/*                                                                        */
-/*  INPUT                                                                 */
-/*                                                                        */
-/*    None                                                                */
-/*                                                                        */
-/*  OUTPUT                                                                */
-/*                                                                        */
-/*    None                                                                */
-/*                                                                        */
-/*  CALLS                                                                 */
-/*                                                                        */
-/*    None                                                                */
-/*                                                                        */
-/*  CALLED BY                                                             */
-/*                                                                        */
-/*    _tx_initialize_kernel_enter           ThreadX entry function        */
-/*                                                                        */
-/**************************************************************************/
-// VOID   _tx_initialize_low_level(VOID)
-// {
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  _tx_initialize_low_level
-    .thumb_func
-.type _tx_initialize_low_level, function
-_tx_initialize_low_level:
-
-    /* Disable interrupts during ThreadX initialization.  */
-    CPSID   i
-
-    /* Set base of available memory to end of non-initialised RAM area.  */
-    LDR     r0, =_tx_initialize_unused_memory       // Build address of unused memory pointer
-    LDR     r1, =__RAM_segment_used_end__           // Build first free address
-    ADD     r1, r1, #4                              //
-    STR     r1, [r0]                                // Setup first unused memory pointer
-
-    /* Setup Vector Table Offset Register.  */
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    LDR     r1, =_vectors                           // Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        // Set vector table address
-
-    /* Enable the cycle count register.  */
-    LDR     r0, =0xE0001000                         // Build address of DWT register
-    LDR     r1, [r0]                                // Pickup the current value
-    ORR     r1, r1, #1                              // Set the CYCCNTENA bit
-    STR     r1, [r0]                                // Enable the cycle count register
-
-    /* Set system stack pointer from vector value.  */
-    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
-    LDR     r1, =_vectors                           // Pickup address of vector table
-    LDR     r1, [r1]                                // Pickup reset stack pointer
-    STR     r1, [r0]                                // Save system stack pointer
-
-    /* Configure SysTick.  */
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    LDR     r1, =SYSTICK_CYCLES
-    STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
-    MOV     r1, #0x7                                // Build SysTick Control Enable Value
-    STR     r1, [r0, #0x10]                         // Setup SysTick Control
-
-    /* Configure handler priorities.  */
-    LDR     r1, =0x00000000                         // Rsrv, UsgF, BusF, MemM
-    STR     r1, [r0, #0xD18]                        // Setup System Handlers 4-7 Priority Registers
-    LDR     r1, =0xFF000000                         // SVCl, Rsrv, Rsrv, Rsrv
-    STR     r1, [r0, #0xD1C]                        // Setup System Handlers 8-11 Priority Registers
-                                                    // Note: SVC must be lowest priority, which is 0xFF
-    LDR     r1, =0x40FF0000                         // SysT, PnSV, Rsrv, DbgM
-    STR     r1, [r0, #0xD20]                        // Setup System Handlers 12-15 Priority Registers
-                                                    // Note: PnSV must be lowest priority, which is 0xFF
-
-    /* Return to caller.  */
-    BX      lr
-// }
-
-
-/* Define shells for each of the unused vectors.  */
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  __tx_BadHandler
-    .thumb_func
-.type __tx_BadHandler, function
-__tx_BadHandler:
-    B       __tx_BadHandler
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  __tx_IntHandler
-    .thumb_func
-.type __tx_IntHandler, function
-__tx_IntHandler:
-// VOID InterruptHandler (VOID)
-// {
-    PUSH    {r0,lr}     // Save LR (and dummy r0 to maintain stack alignment)
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    BL      _tx_execution_isr_enter             // Call the ISR enter function
-#endif
-    /* Do interrupt handler work here */
-    /* .... */
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    BL      _tx_execution_isr_exit              // Call the ISR exit function
-#endif
-    POP     {r0,lr}
-    BX      lr
-// }
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  SysTick_Handler
-    .thumb_func
-.type SysTick_Handler, function
-SysTick_Handler:
-// VOID TimerInterruptHandler (VOID)
-// {
-    PUSH    {r0,lr}     // Save LR (and dummy r0 to maintain stack alignment)
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    BL      _tx_execution_isr_enter             // Call the ISR enter function
-#endif
-    BL      _tx_timer_interrupt
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    BL      _tx_execution_isr_exit              // Call the ISR exit function
-#endif
-    POP     {r0,lr}
-    BX      lr
-// }
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  HardFault_Handler
-    .thumb_func
-.type HardFault_Handler, function
-HardFault_Handler:
-    B       HardFault_Handler
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  UsageFault_Handler
-    .thumb_func
-.type UsageFault_Handler, function
-UsageFault_Handler:
-    CPSID   i                                       // Disable interrupts
-    // Check for stack limit fault
-    LDR     r0, =0xE000ED28                         // CFSR address
-    LDR     r1,[r0]                                 // Pick up CFSR
-    TST     r1, #0x00100000                         // Check for Stack Overflow
-_unhandled_usage_loop:
-    BEQ     _unhandled_usage_loop                   // If not stack overflow then loop
-
-    // Handle stack overflow
-    STR     r1, [r0]                                // Clear CFSR flag(s)
-
-#ifdef __ARM_FP
-    LDR     r0, =0xE000EF34                         // Cleanup FPU context: Load FPCCR address
-    LDR     r1, [r0]                                // Load FPCCR
-    BIC     r1, r1, #1                              // Clear the lazy preservation active bit
-    STR     r1, [r0]                                // Store the value
-#endif
-
-    LDR     r0, =_tx_thread_current_ptr             // Build current thread pointer address
-    LDR     r0,[r0]                                 // Pick up current thread pointer
-    PUSH    {r0,lr}                                 // Save LR (and r0 to maintain stack alignment)
-    BL      _tx_thread_stack_error_handler          // Call ThreadX/user handler
-    POP     {r0,lr}                                 // Restore LR and dummy reg
-
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    // Call the thread exit function to indicate the thread is no longer executing.
-    PUSH    {r0, lr}                                // Save LR (and r0 just for alignment)
-    BL      _tx_execution_thread_exit               // Call the thread exit function
-    POP     {r0, lr}                                // Recover LR
-#endif
-
-    MOV     r1, #0                                  // Build NULL value
-    LDR     r0, =_tx_thread_current_ptr             // Pickup address of current thread pointer
-    STR     r1, [r0]                                // Clear current thread pointer
-
-    // Return from UsageFault_Handler exception
-    LDR     r0, =0xE000ED04                         // Load ICSR
-    LDR     r1, =0x10000000                         // Set PENDSVSET bit
-    STR     r1, [r0]                                // Store ICSR
-    DSB                                             // Wait for memory access to complete
-    CPSIE   i                                       // Enable interrupts
-    BX      lr                                      // Return from exception
-
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  __tx_NMIHandler
-    .thumb_func
-.type __tx_NMIHandler, function
-__tx_NMIHandler:
-    B       __tx_NMIHandler
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  __tx_DBGHandler
-    .thumb_func
-.type __tx_DBGHandler, function
-__tx_DBGHandler:
-    B       __tx_DBGHandler
-
-    .end
diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_schedule.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_schedule.S
index 0a30ab36..28548246 100644
--- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_schedule.S
+++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_schedule.S
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -125,7 +126,7 @@ __tx_ts_handler:
     BL      _tx_execution_thread_exit               // Call the thread exit function
     POP     {r0, lr}                                // Recover LR
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -274,9 +275,19 @@ __tx_ts_wait:
 #endif
 
 #ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+    CPSID   i                                       // Mask every interrupt with PRIMASK, which WFI ignores
+    MOV     r1, #0                                  // Clear BASEPRI so that an interrupt masked by it
+    MSR     BASEPRI, r1                             //   is still able to wake the processor
+#endif
     DSB                                             // Ensure no outstanding memory transactions
     WFI                                             // Wait for interrupt
     ISB                                             // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+    LDR     r1, =TX_PORT_BASEPRI                    // Restore the BASEPRI mask
+    MSR     BASEPRI, r1
+    CPSIE   i                                       // Clear PRIMASK; a pending interrupt is taken here
+#endif
 #endif
 
 #ifdef TX_LOW_POWER
diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S
index 1e84582e..433b16ad 100644
--- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S
+++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv8-M/threadx/iar/readme_threadx.txt b/ports_arch/ARMv8-M/threadx/iar/readme_threadx.txt
index e0f46665..0cd743bd 100644
--- a/ports_arch/ARMv8-M/threadx/iar/readme_threadx.txt
+++ b/ports_arch/ARMv8-M/threadx/iar/readme_threadx.txt
@@ -211,7 +211,12 @@ information associated with this specific port of ThreadX:
 03-02-2021  The following files were changed/added for version 6.1.5:
             tx_port.h                       Added ULONG64_DEFINED
 
-09-30-2020  Initial ThreadX 6.1 version for Cortex-Mxx using IAR's ARM tools.
+09-30-2020  Initial ThreadX 6.1 version of this Armv8-M port using IAR's ARM tools.
+
+            The dates above belong to this shared port, which every Armv8-M
+            core is generated from. They are not the date a particular core
+            gained a ThreadX port: that is when its name was added to
+            scripts/copy_armv8_m.sh.
 
 
 Copyright(c) 1996-2020 Microsoft Corporation
diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_iar.c b/ports_arch/ARMv8-M/threadx/iar/src/tx_iar.c
index 238b485e..ab6c209c 100644
--- a/ports_arch/ARMv8-M/threadx/iar/src/tx_iar.c
+++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_iar.c
@@ -9,6 +9,7 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
 
 /**************************************************************************/
 /**************************************************************************/
@@ -270,7 +271,7 @@ TX_MUTEX    *mutex_ptr;
         mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
 
         /* Check for wrap-around on the next free mutex.  */
-        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK)
         {
 
             /* Yes, set the free index back to 0.  */
@@ -287,7 +288,7 @@ TX_MUTEX    *mutex_ptr;
     }
 
     /* Determine if a free mutex was found.   */
-    if (i >= _MAX_LOCK)
+    if (i >= _MAX_FLOCK)
     {
 
         /* Error!  No more free mutexes!  */
@@ -678,7 +679,7 @@ TX_MUTEX    *mutex_ptr;
         mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
 
         /* Check for wrap-around on the next free mutex.  */
-        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK)
         {
 
             /* Yes, set the free index back to 0.  */
@@ -695,7 +696,7 @@ TX_MUTEX    *mutex_ptr;
     }
 
     /* Determine if a free mutex was found.   */
-    if (i >= _MAX_LOCK)
+    if (i >= _MAX_FLOCK)
     {
 
         /* Error!  No more free mutexes!  */
diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s
index 6d8e07e8..9802be78 100644
--- a/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s
+++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -24,11 +25,9 @@
 #include "tx_user.h"
 #endif
 
-    EXTERN  _tx_thread_system_stack_ptr
     EXTERN  _tx_initialize_unused_memory
     EXTERN  _tx_timer_interrupt
     EXTERN  __main
-    EXTERN  __vector_table
     EXTERN  _tx_thread_current_ptr
     EXTERN  _tx_thread_stack_error_handler
 
@@ -89,25 +88,17 @@ _tx_initialize_low_level:
     LDR     r1, =__tx_free_memory_start             // Build first free address
     STR     r1, [r0]                                // Setup first unused memory pointer
 
-    /* Setup Vector Table Offset Register.  */
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    LDR     r1, =__vector_table                     // Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        // Set vector table address
-
     /* Enable the cycle count register.  */
 //    LDR     r0, =0xE0001000                         // Build address of DWT register
 //    LDR     r1, [r0]                                // Pickup the current value
 //    ORR     r1, r1, #1                              // Set the CYCCNTENA bit
 //    STR     r1, [r0]                                // Enable the cycle count register
 
-    /* Set system stack pointer from vector value.  */
-    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
-    LDR     r1, =__vector_table                     // Pickup address of vector table
-    LDR     r1, [r1]                                // Pickup reset stack pointer
-    STR     r1, [r0]                                // Save system stack pointer
-
     /* Configure SysTick.  */
     MOV     r0, #0xE000E000                         // Build address of NVIC registers
+    MOV     r1, #0                                  // Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         // Reset SysTick Control
+    STR     r1, [r0, #0x18]                         // Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
     MOV     r1, #0x7                                // Build SysTick Control Enable Value
diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_schedule.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_schedule.s
index 84f2043f..4fa3a10e 100644
--- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_schedule.s
+++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_schedule.s
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -129,7 +131,7 @@ __tx_ts_handler:
     BL      _tx_execution_thread_exit               // Call the thread exit function
     POP     {r0, lr}                                // Recover LR
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -278,9 +280,19 @@ __tx_ts_wait:
 #endif
 
 #ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+    CPSID   i                                       // Mask every interrupt with PRIMASK, which WFI ignores
+    MOV     r1, #0                                  // Clear BASEPRI so that an interrupt masked by it
+    MSR     BASEPRI, r1                             //   is still able to wake the processor
+#endif
     DSB                                             // Ensure no outstanding memory transactions
     WFI                                             // Wait for interrupt
     ISB                                             // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+    LDR     r1, =TX_PORT_BASEPRI                    // Restore the BASEPRI mask
+    MSR     BASEPRI, r1
+    CPSIE   i                                       // Clear PRIMASK; a pending interrupt is taken here
+#endif
 #endif
 
 #ifdef TX_LOW_POWER
diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s
index f2a187ea..461d411a 100644
--- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s
+++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s
@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Portions of this file were generated with AI assistance.
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -69,6 +72,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -77,10 +82,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv8-M/threadx/inc/tx_port.h b/ports_arch/ARMv8-M/threadx/inc/tx_port.h
index 316da65b..c59feb71 100644
--- a/ports_arch/ARMv8-M/threadx/inc/tx_port.h
+++ b/ports_arch/ARMv8-M/threadx/inc/tx_port.h
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -541,7 +543,7 @@ UINT posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +556,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -579,6 +582,7 @@ UINT interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb sy \n isb sy " : : : "memory");
     if (_tx_ipsr_get() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -588,6 +592,7 @@ UINT interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb sy " : : : "memory");
     }
 }
 
@@ -613,7 +618,7 @@ VOID                                            _tx_thread_interrupt_restore(UIN
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mxx Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mxx Version 6.5.2.202603 *";
 #else
 #ifdef TX_MISRA_ENABLE
 extern  CHAR                    _tx_version_id[100];