diff options
| author | Yuxin Zhou <[email protected]> | 2021-04-03 01:03:21 +0000 |
|---|---|---|
| committer | Yuxin Zhou <[email protected]> | 2021-04-03 01:03:21 +0000 |
| commit | b12bd44faaca46dbad4b06cb93a8669c6e36e02a (patch) | |
| tree | 033f9c24f940f39d8c4b1b40fcd0d388e80bf317 /ports_module/cortex-m7/iar/inc | |
| parent | 6ffaf848a06ce9dbf8948254ed806ed94ae58305 (diff) | |
Release 6.1.6v6.1.6_rel
Diffstat (limited to 'ports_module/cortex-m7/iar/inc')
| -rw-r--r-- | ports_module/cortex-m7/iar/inc/txm_module_port.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/ports_module/cortex-m7/iar/inc/txm_module_port.h b/ports_module/cortex-m7/iar/inc/txm_module_port.h index 496dc591..7d56647e 100644 --- a/ports_module/cortex-m7/iar/inc/txm_module_port.h +++ b/ports_module/cortex-m7/iar/inc/txm_module_port.h @@ -103,11 +103,17 @@ The following extensions must also be defined in tx_port.h: /* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) * to reflect your system memory attributes (cache, shareable, memory type). */ /* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL #define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif /* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL #define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif /* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif /* Define constants specific to the tools the module can be built with for this particular modules port. */ |