diff options
| author | Yuxin Zhou <[email protected]> | 2022-07-26 02:04:40 +0000 |
|---|---|---|
| committer | Yuxin Zhou <[email protected]> | 2022-07-26 02:04:40 +0000 |
| commit | 8c3c08f10826c4d5332a6d8e2fdf014b793a456a (patch) | |
| tree | c6c2528d7901b11ec5173bdd0bc38339ab18288f /ports_module/cortex_m0+ | |
| parent | 54cda6ee9e68cd9701d759df13e3f6e41429b9bc (diff) | |
Release 6.1.12v6.1.12_rel
Diffstat (limited to 'ports_module/cortex_m0+')
3 files changed, 12 insertions, 36 deletions
diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S index 8ccb9f7a..0e0c8f67 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M0+/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,6 +65,9 @@ /* 01-31-2022 Scott Larson Initial Version 6.1.10 */ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -345,17 +348,6 @@ __tx_ts_restore: CMP r2, #0 BEQ skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOVS r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 - LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - MOVS r6, #0x10 - BICS r2, r2, r6 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration - // Initialize loop to configure MPU registers MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S index f1f5872b..7e613c25 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M0+/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,6 +65,9 @@ /* 01-31-2022 Scott Larson Initial Version 6.1.10 */ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -345,17 +348,6 @@ __tx_ts_restore: CMP r2, #0 BEQ skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOVS r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 - LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - MOVS r6, #0x10 - BICS r2, r2, r6 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration - // Initialize loop to configure MPU registers MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S index bc498210..af30dffa 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M0+/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,6 +72,9 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* change handler name, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -330,17 +333,6 @@ __tx_ts_restore: CMP r2, #0 BEQ skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOVS r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 - LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - MOVS r6, #0x10 - BICS r2, r2, r6 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration - // Initialize loop to configure MPU registers MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block |