diff options
| author | Frédéric Desbiens <[email protected]> | 2026-03-06 19:27:49 +0100 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-03-06 19:27:49 +0100 |
| commit | 3726d7906b4808bfec7855fc088e073199df9120 (patch) | |
| tree | 8789bfd03d1d49e1967e80d04aa4ff606fda43eb /ports_module/cortex_m0+ | |
| parent | 4b6e8100d932a3a67b34c6eb17f84f3bffb9e2ae (diff) | |
| parent | c3259a216026372e3833dd8996a68f77e8595fbd (diff) | |
Merge pull request #510 from eclipse-threadx/devv6.5.0.202601_rel
Merge changes ahead of the v6.5.0.202601 release
Diffstat (limited to 'ports_module/cortex_m0+')
97 files changed, 2126 insertions, 2458 deletions
diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject index 22cf258d..8f5b0d96 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings/> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base"> - + <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath=""> - + <toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6"> - + <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-M0.Plus.NoFPU" valueType="string"/> - + <option id="com.arm.toolchain.v6.base.options.floatabi.2114828810" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/> - + <option id="com.arm.toolchain.v6.base.options.inst.867254844" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/> - + <option id="com.arm.toolchain.v6.base.options.debug.level.2012923809" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - + <targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371.1548806269" name=""/> - + <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1721512389" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.toolchain.v6.builder"/> - + <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.114782258" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.c.compiler.v6.base.option.target.1761409455" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="arm-arm-none-eabi" valueType="string"/> - + <option id="com.arm.tool.c.compiler.v6.base.option.cpu.1798518755" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-m0plus" valueType="string"/> - + <option id="com.arm.tool.c.compiler.v6.base.option.fpu.1125361312" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/> - + <option id="com.arm.tool.c.compiler.v6.base.option.floatabi.1070893797" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.c.compiler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/> - + <option id="com.arm.tool.c.compiler.v6.base.option.inst.1927884242" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498096289" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath"> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_port}""/> - + </option> - + <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.904753152" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - + <inputType id="com.arm.tool.c.compiler.v6.base.input.664809547" superClass="com.arm.tool.c.compiler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1069377025" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - + </tool> - + <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1555411179" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.assembler.v6.base.option.target.1007894450" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" useByScannerDiscovery="false" value="arm-arm-none-eabi" valueType="string"/> - + <option id="com.arm.tool.assembler.v6.base.option.cpu.1820500228" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-m0plus" valueType="string"/> - + <option id="com.arm.tool.assembler.v6.base.option.fpu.969773893" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/> - + <option id="com.arm.tool.assembler.v6.base.option.floatabi.776520171" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/> - + <option id="com.arm.tool.assembler.v6.base.option.inst.1333768272" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/> - + <option id="com.arm.tool.assembler.v6.base.options.debug.level.429021326" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.incpath.663104637" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath"/> - + <inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.c.linker.option.entry.1032206829" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="" valueType="string"/> - + <option id="com.arm.tool.c.linker.option.scatter.1463218579" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="../sample_threadx.scat" valueType="string"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.c.linker.libs.402211535" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs"/> - + <option id="com.arm.tool.linker.v6.option.suppress.1394753016" name="Suppress (--diag_suppress)" superClass="com.arm.tool.linker.v6.option.suppress" useByScannerDiscovery="false" value="" valueType="string"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.implicit.libs.2146903484" name="Implicit other library files" superClass="com.arm.tool.c.linker.implicit.libs" useByScannerDiscovery="false" valueType="libs"> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/Debug/tx.a}""/> - + </option> - + </tool> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c index ac700115..4723699c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 0a4f183b..0c6c1e74 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject index 3f9e781c..7388640f 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject @@ -1,218 +1,218 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 1fcc5d15..71914151 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section Init - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject index d89095b9..e3141bd8 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,172 +1,172 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings/> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base"> - 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+ <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic_modules}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_port}""/> - + </option> - + <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.904753152" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - + <inputType id="com.arm.tool.c.compiler.v6.base.input.664809547" superClass="com.arm.tool.c.compiler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1069377025" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - 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+ <option id="com.arm.tool.c.linker.option.entry.1032206829" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="" valueType="string"/> - + <option id="com.arm.tool.c.linker.option.scatter.1463218579" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="../sample_threadx.scat" valueType="string"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.c.linker.libs.402211535" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs"/> - + <option id="com.arm.tool.linker.v6.option.suppress.1394753016" name="Suppress (--diag_suppress)" superClass="com.arm.tool.linker.v6.option.suppress" useByScannerDiscovery="false" value="" valueType="string"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.implicit.libs.1923699585" name="Implicit other library files" superClass="com.arm.tool.c.linker.implicit.libs" useByScannerDiscovery="false" valueType="libs"> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/Debug/tx.a}""/> - + </option> - + </tool> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c index ac700115..4723699c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index a9202a6e..dcc369ae 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/example_build/tx/.cproject b/ports_module/cortex_m0+/ac6/example_build/tx/.cproject index 0516ff74..1f5d07d9 100644 --- a/ports_module/cortex_m0+/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/tx/.cproject @@ -1,166 +1,166 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings> - + <externalSetting> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - 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+ <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base"> - 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+ </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m0+/ac6/inc/tx_port.h b/ports_module/cortex_m0+/ac6/inc/tx_port.h index c25eeac5..374db939 100644 --- a/ports_module/cortex_m0+/ac6/inc/tx_port.h +++ b/ports_module/cortex_m0+/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -110,7 +102,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -121,8 +113,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -151,7 +143,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -163,7 +155,7 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -202,11 +194,11 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -214,8 +206,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #ifdef TX_ENABLE_FPU_SUPPORT @@ -268,13 +260,13 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -347,7 +339,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -375,7 +367,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE @@ -405,14 +397,14 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* This ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -431,9 +423,9 @@ ULONG _tx_misra_ipsr_get(VOID); #ifndef TX_DISABLE_INLINE -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -482,7 +474,7 @@ unsigned int interrupt_save; interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); - } + } } @@ -516,8 +508,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0+/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/ac6/inc/txm_module_port.h b/ports_module/cortex_m0+/ac6/inc/txm_module_port.h index 7eaf5a31..4ad075ee 100644 --- a/ports_module/cortex_m0+/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -375,6 +370,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S index dab2dc35..9e439c1f 100644 --- a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c index 09e323c0..13f57b8d 100644 --- a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _txm_module_initialize(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S index a2021a26..28245b55 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S index 24eeffb9..cfe953dc 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S index 6100ed57..43bc635a 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S index 73d5a537..7a69a31e 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S index 656abc16..972a7ea5 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S index a1559844..bc9e27f8 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S index a3892f1e..c8960eaf 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S index 0c426bfb..15035d55 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S index d0825135..3195b970 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index c215277c..84f75cdf 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 256. */ if(size <= 256) return 256; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 7cf1bf9b..ad1ceaeb 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -112,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -122,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -222,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -232,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -244,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 8cd0c9f5..7faeea6a 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 457734dc..84c26f46 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index bd14368c..83aae591 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -197,10 +192,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -212,7 +207,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -220,7 +215,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -319,16 +314,16 @@ UINT i; /* Set the attributes, size (256 bytes) and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(256) << 1) | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - + /* Initialize the MPU table index. */ mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -336,7 +331,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) { @@ -346,7 +341,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -354,7 +349,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -363,10 +358,10 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -374,29 +369,29 @@ UINT i; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -405,7 +400,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -413,7 +408,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) { @@ -423,7 +418,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(data_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -431,7 +426,7 @@ UINT i; data_size = data_size - (block_size << 1); block_size = _txm_power_of_two_block_size(data_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -440,10 +435,10 @@ UINT i; block_size = _txm_power_of_two_block_size(data_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -451,17 +446,17 @@ UINT i; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } - + /* Setup MPU for the remaining regions. */ while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) { /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - + /* Increment MPU table index. */ mpu_table_index++; } @@ -487,11 +482,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 256-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFF00) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - + /* Attributes: read only, write-back, shareable, size 256 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x0607000F; @@ -504,7 +499,7 @@ UINT i; /* Setup values for code area. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) @@ -516,7 +511,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { @@ -526,7 +521,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -534,7 +529,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -543,57 +538,57 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070000; - + /* Is there still some code? If so set the region enable bit. */ if (code_size) { @@ -602,13 +597,13 @@ UINT i; } /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -618,34 +613,34 @@ UINT i; { code_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Adjust indeces to pass over the shared memory entry. */ /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -654,46 +649,46 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ base_attribute_register = base_attribute_register | 0x1; } - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -703,10 +698,10 @@ UINT i; { data_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } @@ -768,7 +763,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 7e04f022..5e8190ae 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject index 63be6be1..f92a30da 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject @@ -1,166 +1,166 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S index f5090533..445f77cf 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s index 73692924..ef3d9314 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject index 9dc7b2bb..8ceaed84 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject @@ -1,178 +1,178 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ ldr r0, =__got_load_start__ subs r0,r0,r3 add r0,r0,r5 @@ -44,13 +44,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table adds r0, r0, #4 // Move to next entry - adds r1, r1, #4 // + adds r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ subs r0,r0,r3 add r0,r0,r5 @@ -61,9 +61,9 @@ got_setup_done: subs r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ subs r0,r0,r4 add r0,r0,r9 @@ -87,12 +87,12 @@ got_setup_done: str r2, [r0] adds r0, r0, #4 str r1, [r0] - + /* Store other preserved registers. */ pop {r3-r7} mov lr, r8 bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -128,4 +128,4 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - + diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld index 1efc6ca1..96320525 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld @@ -130,7 +130,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -140,7 +140,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S index dec92093..8ea214ba 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,8 +1,8 @@ .text .align 4 .syntax unified - .section .preamble - + .section .preamble, "ax" + // Define public symbols .global __txm_module_preamble .global __txm_module_preamble_two diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject index c243c1fd..d1a7a6cc 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject @@ -1,174 +1,174 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings/> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base"> - + <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath=""> - + <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi.1351701976" name="GCC 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi"> - + <targetPlatform binaryParser="" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi.1351701976.1801457245" name=""/> - + <builder buildPath="${workspace_loc:/sample_threadx_module_manager}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.629037601" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-10.2.1-arm-none-eabi.1023531190" name="GCC C Compiler 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-10.2.1-arm-none-eabi"> - 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+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </scannerConfigBuildInfo> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 283dc71a..f47155b8 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -72,8 +72,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -93,22 +93,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -117,11 +117,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 663c92ba..4928d596 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s index 60662fe3..452c8934 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word HardFaultException .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m0+/gnu/example_build/tx/.cproject b/ports_module/cortex_m0+/gnu/example_build/tx/.cproject index a1c0d7ab..4374ece6 100644 --- a/ports_module/cortex_m0+/gnu/example_build/tx/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m0+/gnu/example_build/txm/.cproject b/ports_module/cortex_m0+/gnu/example_build/txm/.cproject index f04340b4..fcae5c35 100644 --- a/ports_module/cortex_m0+/gnu/example_build/txm/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/txm/.cproject @@ -1,168 +1,168 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - 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+ <additionalInput kind="additionalinput" paths="$(LIBS)"/> - + <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/> - + </inputType> - + </tool> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-10.2.1-arm-none-eabi.854576146" name="GCC C++ Linker 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-10.2.1-arm-none-eabi"/> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-10.2.1-arm-none-eabi.706397807" name="GCC Archiver 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-10.2.1-arm-none-eabi"/> - + </toolChain> - + </folderInfo> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m0+/gnu/inc/tx_port.h b/ports_module/cortex_m0+/gnu/inc/tx_port.h index f2cc8240..0c2e90e5 100644 --- a/ports_module/cortex_m0+/gnu/inc/tx_port.h +++ b/ports_module/cortex_m0+/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -125,7 +117,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -136,8 +128,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -166,7 +158,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -178,7 +170,7 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -217,19 +209,19 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif /* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #ifdef TX_ENABLE_FPU_SUPPORT @@ -282,13 +274,13 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -361,7 +353,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -389,7 +381,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE @@ -419,14 +411,14 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* This ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -445,9 +437,9 @@ ULONG _tx_misra_ipsr_get(VOID); #ifndef TX_DISABLE_INLINE -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -496,7 +488,7 @@ unsigned int interrupt_save; interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); - } + } } @@ -530,8 +522,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0+/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/gnu/inc/txm_module_port.h b/ports_module/cortex_m0+/gnu/inc/txm_module_port.h index 46f2e60d..3ab998ae 100644 --- a/ports_module/cortex_m0+/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -375,6 +370,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c index db33fd67..2bb3bf7e 100644 --- a/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S index d68c6c76..dc04a44d 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S index beea2c1b..abd44ea0 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S index 4523a729..9ca7b3c7 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S index e7c45568..f0584738 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S index 7230fa3f..2aaaac2d 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S index 04d68a14..61865ee5 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S index 49c0a239..653a58a8 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S index 94b06b59..2c5c5274 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S index 4b7810ff..e1199f1c 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index c215277c..84f75cdf 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 256. */ if(size <= 256) return 256; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 7cf1bf9b..ad1ceaeb 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -112,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -122,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -222,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -232,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -244,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 8cd0c9f5..7faeea6a 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 457734dc..84c26f46 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index bd14368c..83aae591 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -197,10 +192,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -212,7 +207,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -220,7 +215,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -319,16 +314,16 @@ UINT i; /* Set the attributes, size (256 bytes) and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(256) << 1) | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - + /* Initialize the MPU table index. */ mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -336,7 +331,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) { @@ -346,7 +341,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -354,7 +349,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -363,10 +358,10 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -374,29 +369,29 @@ UINT i; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -405,7 +400,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -413,7 +408,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) { @@ -423,7 +418,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(data_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -431,7 +426,7 @@ UINT i; data_size = data_size - (block_size << 1); block_size = _txm_power_of_two_block_size(data_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -440,10 +435,10 @@ UINT i; block_size = _txm_power_of_two_block_size(data_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -451,17 +446,17 @@ UINT i; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } - + /* Setup MPU for the remaining regions. */ while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) { /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - + /* Increment MPU table index. */ mpu_table_index++; } @@ -487,11 +482,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 256-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFF00) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - + /* Attributes: read only, write-back, shareable, size 256 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x0607000F; @@ -504,7 +499,7 @@ UINT i; /* Setup values for code area. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) @@ -516,7 +511,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { @@ -526,7 +521,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -534,7 +529,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -543,57 +538,57 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070000; - + /* Is there still some code? If so set the region enable bit. */ if (code_size) { @@ -602,13 +597,13 @@ UINT i; } /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -618,34 +613,34 @@ UINT i; { code_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Adjust indeces to pass over the shared memory entry. */ /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -654,46 +649,46 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ base_attribute_register = base_attribute_register | 0x1; } - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -703,10 +698,10 @@ UINT i; { data_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } @@ -768,7 +763,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S index 726c6189..19fce081 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m0+/iar/example_build/cstartup_M.s b/ports_module/cortex_m0+/iar/example_build/cstartup_M.s index da53c200..3ae600b5 100644 --- a/ports_module/cortex_m0+/iar/example_build/cstartup_M.s +++ b/ports_module/cortex_m0+/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx.c index c67d75d0..a12160fa 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,7 +85,7 @@ CHAR *pointer = TX_NULL; #ifdef TX_ENABLE_EVENT_TRACE tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); #endif - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); @@ -96,42 +96,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -139,23 +139,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -258,11 +258,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -321,7 +321,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -374,7 +374,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c index 647dcced..a91c3b8c 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -105,7 +105,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -121,7 +121,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -133,42 +133,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -176,23 +176,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -237,7 +237,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -247,7 +247,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -295,19 +295,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)EXTERNAL_MEMORY = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c index e928709f..b944f46e 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c @@ -67,11 +67,11 @@ int main() void tx_application_define(void *first_unused_memory) { -CHAR *pointer = (CHAR*)module_manager_stack; +CHAR *pointer = (CHAR*)module_manager_stack; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -91,22 +91,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) MODULE_CODE); - + /* Enable 128 byte read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -115,11 +115,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf index 5e6f652e..92334d1e 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf @@ -18,8 +18,8 @@ define symbol __ICFEDIT_size_heap__ = 0x200; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; diff --git a/ports_module/cortex_m0+/iar/example_build/startup.s b/ports_module/cortex_m0+/iar/example_build/startup.s index 06de32fb..34ce08e8 100644 --- a/ports_module/cortex_m0+/iar/example_build/startup.s +++ b/ports_module/cortex_m0+/iar/example_build/startup.s @@ -6,10 +6,10 @@ ;* Description : STM32F2xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP -;* - Configure he external SRAM mounted on STM322xG-EVAL board +;* - Configure he external SRAM mounted on STM322xG-EVAL board ;* to be used as data memory (optional, to be enabled by user) ;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* After Reset the Cortex-M3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. @@ -72,86 +72,86 @@ __vector_table DC32 SysTick_Handler ; SysTick ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -164,7 +164,7 @@ __vector_table Reset_Handler CPSID i ; Disable interrupts LDR R0, =sfe(CSTACK) ; restore original stack pointer - MSR MSP, R0 + MSR MSP, R0 LDR R0, =__iar_program_start ; Jump to ThreadX start, which will call IAR startup code BX R0 @@ -215,47 +215,47 @@ SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT(2) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:NOROOT(2) -PVD_IRQHandler +PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT(2) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT(2) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT(2) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT(2) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -264,358 +264,358 @@ EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT(2) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT(2) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT(2) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT(2) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FSMC_IRQHandler SECTION .text:CODE:NOROOT(2) -FSMC_IRQHandler +FSMC_IRQHandler B FSMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:NOROOT(2) -SDIO_IRQHandler +SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT(2) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT(2) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT(2) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_FS_IRQHandler +OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT(2) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_HS_IRQHandler +OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT(2) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:NOROOT(2) -CRYP_IRQHandler +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT(2) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT(2) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler END diff --git a/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s index e26ea7f0..16404d63 100644 --- a/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -40,11 +40,11 @@ ; SYSTEM_CLOCK EQU 7200000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 ; ; SECTION `.text`:CODE:NOROOT(2) @@ -83,12 +83,6 @@ __tx_free_memory_start ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ @@ -178,7 +172,7 @@ __tx_SysTickHandler: MOV lr, r1 BX lr ; } - + END - + diff --git a/ports_module/cortex_m0+/iar/inc/tx_port.h b/ports_module/cortex_m0+/iar/inc/tx_port.h index f41b5a6f..2f4abd56 100644 --- a/ports_module/cortex_m0+/iar/inc/tx_port.h +++ b/ports_module/cortex_m0+/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -129,7 +121,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -140,8 +132,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -180,7 +172,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -194,7 +186,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -230,10 +222,10 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID *tx_thread_module_reserved; #endif #ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -255,11 +247,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif /* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, @@ -268,23 +260,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #ifdef TX_ENABLE_FPU_SUPPORT @@ -338,13 +330,13 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -417,7 +409,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -445,7 +437,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE /* @@ -479,14 +471,14 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* This ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -503,9 +495,9 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -566,8 +558,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0+/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m0+/iar/inc/txm_module_port.h b/ports_module/cortex_m0+/iar/inc/txm_module_port.h index 9d3ca242..8561f21e 100644 --- a/ports_module/cortex_m0+/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -375,6 +370,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c index 6d4b4f52..8983b832 100644 --- a/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s index ef9d5bea..236515eb 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -106,7 +107,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -1014,7 +1015,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR ;; return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -1029,7 +1030,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR ;; return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -1046,8 +1047,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 ; Build FPCCR address LDR r0, [r0] ; Load FPCCR value BX LR ;; return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -1061,10 +1062,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR ;; return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S index 1dd17d7c..229055e2 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S index 034a9c0a..3e9eebc7 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S index 7317efa0..434c52c6 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S index bdca7a0a..3ee1d914 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S index db969358..d7342b28 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S index 4eeeff3e..517d337a 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,20 +64,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* change handler name, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S index 925631ed..5ced33f6 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S index 23a71b4a..b485e12b 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S index cc2680cd..5210c308 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,12 +69,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c index c215277c..84f75cdf 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 256. */ if(size <= 256) return 256; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 7cf1bf9b..ad1ceaeb 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -112,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -122,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -222,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -232,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -244,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 8cd0c9f5..7faeea6a 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 457734dc..84c26f46 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c index bd14368c..83aae591 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -197,10 +192,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -212,7 +207,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -220,7 +215,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -319,16 +314,16 @@ UINT i; /* Set the attributes, size (256 bytes) and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(256) << 1) | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - + /* Initialize the MPU table index. */ mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -336,7 +331,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) { @@ -346,7 +341,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -354,7 +349,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -363,10 +358,10 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -374,29 +369,29 @@ UINT i; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -405,7 +400,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -413,7 +408,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) { @@ -423,7 +418,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(data_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -431,7 +426,7 @@ UINT i; data_size = data_size - (block_size << 1); block_size = _txm_power_of_two_block_size(data_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -440,10 +435,10 @@ UINT i; block_size = _txm_power_of_two_block_size(data_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -451,17 +446,17 @@ UINT i; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } - + /* Setup MPU for the remaining regions. */ while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) { /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - + /* Increment MPU table index. */ mpu_table_index++; } @@ -487,11 +482,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 256-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFF00) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - + /* Attributes: read only, write-back, shareable, size 256 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x0607000F; @@ -504,7 +499,7 @@ UINT i; /* Setup values for code area. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) @@ -516,7 +511,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { @@ -526,7 +521,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -534,7 +529,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -543,57 +538,57 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070000; - + /* Is there still some code? If so set the region enable bit. */ if (code_size) { @@ -602,13 +597,13 @@ UINT i; } /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -618,34 +613,34 @@ UINT i; { code_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Adjust indeces to pass over the shared memory entry. */ /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -654,46 +649,46 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ base_attribute_register = base_attribute_register | 0x1; } - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -703,10 +698,10 @@ UINT i; { data_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } @@ -768,7 +763,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S index cf911004..6271f32f 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { |