Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

5 files changed, 29 insertions, 15 deletions

diff --git a/ports_module/cortex_m23/gnu/inc/tx_port.h b/ports_module/cortex_m23/gnu/inc/tx_port.h
index 70dae581..fa33b766 100644
--- a/ports_module/cortex_m23/gnu/inc/tx_port.h
+++ b/ports_module/cortex_m23/gnu/inc/tx_port.h
@@ -465,7 +465,7 @@ unsigned int interrupt_save;
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M23/GNU Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors.  *  ThreadX Cortex-M23/GNU Version 6.5.2.202603 *";
 #else
 #ifdef TX_MISRA_ENABLE
 extern  CHAR                    _tx_version_id[100];
diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S
index d38525bf..7e73dc96 100644
--- a/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S
+++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S
@@ -8,6 +8,8 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
+
 
 
 /**************************************************************************/
@@ -85,11 +87,6 @@ _tx_initialize_low_level:
     ADDS    r1, r1, #4                              //
     STR     r1, [r0]                                // Setup first unused memory pointer
 
-    /* Setup Vector Table Offset Register.  */
-    LDR     r0, =0xE000ED08                         // Build address of NVIC registers
-    LDR     r1, =__Vectors                          // Pickup address of vector table
-    STR     r1, [r0]                                // Set vector table address
-
 //    /* Enable the cycle count register.  */
 //
 //    LDR     r0, =0xE0001000                         // Build address of DWT register
@@ -97,14 +94,11 @@ _tx_initialize_low_level:
 //    ORR     r1, r1, #1                              // Set the CYCCNTENA bit
 //    STR     r1, [r0]                                // Enable the cycle count register
 
-    /* Set system stack pointer from vector value.  */
-    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
-    LDR     r1, =__Vectors                          // Pickup address of vector table
-    LDR     r1, [r1]                                // Pickup reset stack pointer
-    STR     r1, [r0]                                // Save system stack pointer
-
     /* Configure SysTick.  */
     LDR     r0, =0xE000E000                         // Build address of NVIC registers
+    MOVS    r1, #0                                  // Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         // Reset SysTick Control
+    STR     r1, [r0, #0x18]                         // Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
     MOVW    r1, #0x7                                // Build SysTick Control Enable Value
diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S
index 2f9d7165..bf3d7a5b 100644
--- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S
+++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -69,7 +71,14 @@ _tx_thread_context_restore:
     /* Call the ISR exit function to indicate an ISR is complete.  */
     PUSH    {r0, lr}                                // Save return address
     BL      _tx_execution_isr_exit                  // Call the ISR exit function
-    POP     {r0, lr}                                // Recover return address
+    POP     {r0, r1}                                // Recover r0 and the return address
+    MOV     lr, r1                                  // This core cannot POP into LR: the
+                                                    //   16-bit Thumb POP takes r0-r7 and
+                                                    //   pc only.  MOV to a high register
+                                                    //   is permitted, so restore LR from
+                                                    //   a scratch register.  r1 is free --
+                                                    //   the BL above may clobber r0-r3,
+                                                    //   which is why r0 is saved at all.
 #endif
 
     BX      lr
diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S
index f51cff71..dc52d415 100644
--- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S
+++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -69,7 +71,14 @@ _tx_thread_context_save:
     /* Call the ISR enter function to indicate an ISR is starting.  */
     PUSH    {r0, lr}                                // Save return address
     BL      _tx_execution_isr_enter                 // Call the ISR enter function
-    POP     {r0, lr}                                // Recover return address
+    POP     {r0, r1}                                // Recover r0 and the return address
+    MOV     lr, r1                                  // This core cannot POP into LR: the
+                                                    //   16-bit Thumb POP takes r0-r7 and
+                                                    //   pc only.  MOV to a high register
+                                                    //   is permitted, so restore LR from
+                                                    //   a scratch register.  r1 is free --
+                                                    //   the BL above may clobber r0-r3,
+                                                    //   which is why r0 is saved at all.
 #endif
 
     BX      lr
diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S
index ae66a5c5..8e2bf2cd 100644
--- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S
+++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -67,7 +69,7 @@ _tx_thread_secure_stack_initialize:
     SVC     3
     CPSID   i               // Disable interrupts
 #else
-    MOV     r0, #0xFF       // Feature not enabled
+    MOVS    r0, #0xFF       // Feature not enabled
 #endif
     BX      lr
     .end