diff options
| author | Yuxin Zhou <[email protected]> | 2021-07-28 07:24:02 +0000 |
|---|---|---|
| committer | Yuxin Zhou <[email protected]> | 2021-07-28 07:24:02 +0000 |
| commit | d0dab582506f132690b35b36ffea129ad51110b0 (patch) | |
| tree | 13add80dd314dc38efc1830f3d1f36b5a2596e98 /ports_module/cortex_m23 | |
| parent | 244365fc6a937c754cfc6bb8e6895dc6f37bac0e (diff) | |
Release 6.1.8v6.1.8_rel
Diffstat (limited to 'ports_module/cortex_m23')
59 files changed, 1507 insertions, 1619 deletions
diff --git a/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx index cb51db51..2614df9e 100644 --- a/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx +++ b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx @@ -2947,6 +2947,18 @@ <RteFlg>0</RteFlg> <bShared>0</bShared> </File> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>232</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\module_manager\src\tx_thread_secure_stack_initialize.S</PathWithFileName> + <FilenameWithoutPath>tx_thread_secure_stack_initialize.S</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> </Group> <Group> diff --git a/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx index 56fc195b..cdf3f904 100644 --- a/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx +++ b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx @@ -1538,6 +1538,11 @@ <FileType>1</FileType> <FilePath>..\module_manager\src\txm_module_manager_port_dispatch.c</FilePath> </File> + <File> + <FileName>tx_thread_secure_stack_initialize.S</FileName> + <FileType>2</FileType> + <FilePath>..\module_manager\src\tx_thread_secure_stack_initialize.S</FilePath> + </File> </Files> </Group> <Group> diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c index 4d3bdc0f..bc55de5c 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -300,8 +300,8 @@ UINT status; while(1) { /* Test external memory sharing. */ - *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - *(ULONG *)0x20040004 = 0x01010101; + // *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; + // *(ULONG *)0x20040004 = 0x01010101; /* Increment the thread counter. */ thread_2_counter++; diff --git a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S index 3ea33abb..81dc7f36 100644 --- a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -29,7 +29,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) STACK_SIZE = 0x00000400 HEAP_SIZE = 0x00000000 - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -96,8 +95,7 @@ _tx_initialize_low_level: LDR r1, =__Vectors // Pickup address of vector table STR r1, [r0] // Set vector table address -// /* Enable the cycle count register. */ -// + /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit diff --git a/ports_module/cortex_m23/ac6/inc/tx_port.h b/ports_module/cortex_m23/ac6/inc/tx_port.h index 76a4444b..aa34ec45 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_port.h +++ b/ports_module/cortex_m23/ac6/inc/tx_port.h @@ -68,7 +68,6 @@ #include <stdlib.h> #include <string.h> #include <arm_compat.h> -#include "ARMCM23_TZ.h" /* For intrinsic functions. */ /* Define ThreadX basic types for this port. */ diff --git a/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h index c2779f40..0a2bdd67 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S index b2989990..5a1efa6f 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs Interrupt Service Routines */ /* */ /* RELEASE HISTORY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_restore, function _tx_thread_context_restore: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S index fefeb7b0..2b45d9dc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs */ /* */ /* RELEASE HISTORY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_save, function _tx_thread_context_save: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S index 7a24fffd..16aae2b6 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -68,11 +68,9 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller // } .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S index d99f1713..ca010871 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S index b03ad941..64a5c8ca 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S index 2a39b955..67fe291e 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S @@ -21,6 +21,10 @@ /**************************************************************************/ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -71,29 +75,24 @@ .thumb_func .type _tx_thread_schedule, function _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOVW r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR @@ -221,19 +220,18 @@ BusFault_Handler: PendSV_Handler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function POP {r0, r1} // Recover LR - MOV lr, r1 + MOV lr, r1 // CPSIE i // Enable interrupts #endif - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address - MOVW r3, #0 // Build NULL value LDR r1, [r0] // Pickup current thread pointer @@ -246,18 +244,18 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 // Allocate stack space - STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4, r8 // - MOV r5, r9 // - MOV r6, r10 // - MOV r7, r11 // + STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // Copy r8-r11 to multisave registers + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 SUBS r3, r3, #32 // Allocate stack space - STM r3!, {r4-r7} // + STM r3!, {r4-r7} // Save r8-r11 SUBS r3, r3, #20 // Allocate stack space - MOV r5, lr // - STR r5, [r3] // Save LR on the stack + MOV r5, lr // Copy lr to saveable register + STR r5, [r3] // Save lr on the stack STR r3, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, =0xC4 // Secure stack index offset @@ -339,7 +337,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -379,6 +377,8 @@ _skip_secure_restore: CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup // Initialize loop to configure MPU registers + // Order doesn't matter, so txm_module_instance_mpu_registers[0] + // will be in region 7 and txm_module_instance_mpu_registers[7] will be in region 0. MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block MOVS r5, #0 // Select region 0 @@ -416,7 +416,6 @@ skip_mpu_setup: BX lr // Return to thread! - /* SVC Handler. */ .section .text .balign 4 @@ -430,10 +429,10 @@ SVC_Handler: MOVS r1, #0x04 TST r1, r0 // Determine return stack from EXC_RETURN bit 2 BEQ _tx_load_msp - MRS r0, PSP // Get PSP + MRS r0, PSP // Get PSP if return stack is PSP B _tx_get_svc _tx_load_msp: - MRS r0, MSP // Get MSP + MRS r0, MSP // Get MSP if return stack is MSP _tx_get_svc: LDR r1, [r0,#24] // Load saved PC from stack LDR r3, =-2 @@ -554,14 +553,14 @@ _tx_exit_continue: MRS r3, PSP // Pickup kernel stack pointer /* Copy kernel hardware stack to module thread stack. */ - LDM r3!,{r1-r2} // Get r0, r1 from kernel stack - STM r0!,{r1-r2} // Insert r0, r1 into thread stack - LDM r3!,{r1-r2} // Get r2, r3 from kernel stack - STM r0!,{r1-r2} // Insert r2, r3 into thread stack - LDM r3!,{r1-r2} // Get r12, lr from kernel stack - STM r0!,{r1-r2} // Insert r12, lr into thread stack - LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack - STM r0!,{r1-r2} // Insert pc, xpsr into thread stack + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUBS r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -605,7 +604,7 @@ _tx_free_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c index b4679878..8941a705 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c @@ -29,7 +29,7 @@ #define TX_SOURCE_CODE -#include "ARMCM23_TZ.h" /* For intrinsic functions. */ +#include "cmsis_compiler.h" /* For intrinsic functions. */ #include "tx_secure_interface.h" /* Interface for NS code. */ /* Minimum size of secure stack. */ @@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */ -/* 6.1.1 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M23/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ @@ -98,21 +98,35 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 08-02-2021 Scott Larson Modified comment(s), and */ +/* changed name, execute in */ +/* handler mode, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +UINT _tx_thread_secure_mode_stack_initialize(void) { - - /* Set secure mode to use PSP. */ - __set_CONTROL(__get_CONTROL() | 2); - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - __set_PSPLIM(0); - __set_PSP(0); - - return; +UINT status; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + status = TX_SUCCESS; + } + return status; } @@ -294,7 +308,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -379,7 +393,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S index de7098e7..e43051dc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -66,7 +66,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_allocate + .global _tx_thread_secure_stack_allocate .global _tx_alloc_return .thumb_func .type _tx_thread_secure_stack_allocate, function @@ -80,7 +80,6 @@ _tx_alloc_return: BEQ _alloc_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _alloc_return_interrupt_enabled: diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S index 837dba7e..110bf0f5 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S @@ -55,7 +55,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -64,7 +64,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_free + .global _tx_thread_secure_stack_free .global _tx_free_return .thumb_func .type _tx_thread_secure_stack_free, function @@ -78,7 +78,6 @@ _tx_free_return: BEQ _free_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _free_return_interrupt_enabled: diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S new file mode 100644 index 00000000..c2f9bf31 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to initialize a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* none */ +/* */ +/* OUTPUT */ +/* */ +/* none */ +/* */ +/* CALLS */ +/* */ +/* SVC 3 */ +/* */ +/* CALLED BY */ +/* */ +/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_secure_stack_initialize(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_initialize + .thumb_func +.type _tx_thread_secure_stack_initialize, function +_tx_thread_secure_stack_initialize: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + CPSIE i // Enable interrupts for SVC call + SVC 3 + CPSID i // Disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif + BX lr + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S index 5a95a14f..4b4f443d 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c index ef98240c..8e3cff23 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c @@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c index ffd78d08..75ad1f32 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S index 175a9109..749b0fc1 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S @@ -71,7 +71,7 @@ .thumb_func .type _tx_thread_system_return, function _tx_thread_system_return: - /* Return to real scheduler via PendSV. Note that this routine is often + /* Return to real scheduler via PendSV. Note that this routine is often replaced with in-line assembly in tx_port.h to improved performance. */ LDR r0, =0x10000000 // Load PENDSVSET bit diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S index fdfcdcc5..81df88f7 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -80,8 +79,7 @@ _tx_timer_interrupt: /* Increment the system clock. */ // _tx_timer_system_clock++; - MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock - MOVT r1, #:upper16:_tx_timer_system_clock + LDR r1, =_tx_timer_system_clock // Pickup address of system clock LDR r0, [r1, #0] // Pickup system clock ADDS r0, r0, #1 // Increment system clock STR r0, [r1, #0] // Store new system clock @@ -90,28 +88,27 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice - MOVT r3, #:upper16:_tx_timer_time_slice + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUBS r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOVW r0, #1 // Build expired value STR r0, [r3, #0] // Set time-slice expiration flag @@ -123,18 +120,16 @@ __tx_timer_no_time_slice: // if (*_tx_timer_current_ptr) // { - MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address - MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address LDR r0, [r1, #0] // Pickup current timer LDR r2, [r0, #0] // Pickup timer list entry CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address - MOVT r3, #:upper16:_tx_timer_expired + LDR r3, =_tx_timer_expired // Pickup expiration flag address MOVW r2, #1 // Build expired value STR r2, [r3, #0] // Set expired flag B __tx_timer_done // Finished timer processing @@ -144,25 +139,23 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADDS r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) - MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end - MOVT r3, #:upper16:_tx_timer_list_end + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; - MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start - MOVT r3, #:upper16:_tx_timer_list_start + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start __tx_timer_skip_wrap: @@ -172,18 +165,15 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag LDR r2, [r3, #0] // Pickup time-slice expired flag CBNZ r2, __tx_something_expired // Did a time-slice expire? // If non-zero, time-slice expired - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_nothing_expired // Did a timer expire? // No, nothing expired @@ -197,14 +187,13 @@ __tx_something_expired: // if (_tx_timer_expired) // { - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -215,28 +204,21 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR r2, [r3, #0] // Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing - MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag - MOVT r0, #:upper16:_tx_thread_preempt_disable - + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag LDR r1, [r0] // Is the preempt disable flag set? CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic - MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address - MOVT r0, #:upper16:_tx_thread_current_ptr - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r1, [r0] // Pickup the current thread pointer - MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address - MOVT r2, #:upper16:_tx_thread_execute_ptr - + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register LDR r2, =0x10000000 // Build value for PendSV bit @@ -248,8 +230,8 @@ __tx_timer_skip_time_slice: __tx_timer_not_ts_expiration: - POP {r0, r1} // Recover lr register (r0 is just there for - MOV lr, r1 // the 8-byte stack alignment + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment // } @@ -257,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c index 35482b6c..9e985efa 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c index 950e8ec0..c3ef9577 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h index 976f32be..26a608a6 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S index 14d772fb..084635a3 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs Interrupt Service Routines */ /* */ /* RELEASE HISTORY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_restore, function _tx_thread_context_restore: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S index 25050678..cf58aabd 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs */ /* */ /* RELEASE HISTORY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_save, function _tx_thread_context_save: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S index 4f05f3ff..b80112b3 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -68,11 +68,9 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller // } .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S index 3a1fc9f6..2ee36199 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S index 696c227b..3812e0d3 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S index 98caf079..c60919ff 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S @@ -71,29 +71,24 @@ .thumb_func .type _tx_thread_schedule, function _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOVW r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR @@ -221,19 +216,18 @@ BusFault_Handler: PendSV_Handler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function POP {r0, r1} // Recover LR - MOV lr, r1 + MOV lr, r1 // CPSIE i // Enable interrupts #endif - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address - MOVW r3, #0 // Build NULL value LDR r1, [r0] // Pickup current thread pointer @@ -246,18 +240,18 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 // Allocate stack space - STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4, r8 // - MOV r5, r9 // - MOV r6, r10 // - MOV r7, r11 // + STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // Copy r8-r11 to multisave registers + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 SUBS r3, r3, #32 // Allocate stack space - STM r3!, {r4-r7} // + STM r3!, {r4-r7} // Save r8-r11 SUBS r3, r3, #20 // Allocate stack space - MOV r5, lr // - STR r5, [r3] // Save LR on the stack + MOV r5, lr // Copy lr to saveable register + STR r5, [r3] // Save lr on the stack STR r3, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, =0xC4 // Secure stack index offset @@ -339,7 +333,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -418,7 +412,6 @@ skip_mpu_setup: BX lr // Return to thread! - /* SVC Handler. */ .section .text .balign 4 @@ -432,10 +425,10 @@ SVC_Handler: MOVS r1, #0x04 TST r1, r0 // Determine return stack from EXC_RETURN bit 2 BEQ _tx_load_msp - MRS r0, PSP // Get PSP + MRS r0, PSP // Get PSP if return stack is PSP B _tx_get_svc _tx_load_msp: - MRS r0, MSP // Get MSP + MRS r0, MSP // Get MSP if return stack is MSP _tx_get_svc: LDR r1, [r0,#24] // Load saved PC from stack LDR r3, =-2 @@ -556,14 +549,14 @@ _tx_exit_continue: MRS r3, PSP // Pickup kernel stack pointer /* Copy kernel hardware stack to module thread stack. */ - LDM r3!,{r1-r2} // Get r0, r1 from kernel stack - STM r0!,{r1-r2} // Insert r0, r1 into thread stack - LDM r3!,{r1-r2} // Get r2, r3 from kernel stack - STM r0!,{r1-r2} // Insert r2, r3 into thread stack - LDM r3!,{r1-r2} // Get r12, lr from kernel stack - STM r0!,{r1-r2} // Insert r12, lr into thread stack - LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack - STM r0!,{r1-r2} // Insert pc, xpsr into thread stack + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUBS r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -607,7 +600,7 @@ _tx_free_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c index 72bc05f8..8f22bb90 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c @@ -61,8 +61,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M23/GNU */ -/* 6.1.3 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M23/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -77,7 +77,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ @@ -94,27 +94,40 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ -/* 12-31-2020 Scott Larson Modified comment(s), and */ -/* fixed M23 GCC build, */ -/* resulting in version 6.1.3 */ +/* 08-02-2021 Scott Larson Modified comment(s), changed */ +/* name, execute in handler */ +/* mode, disable optimization, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ -__attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +__attribute__((cmse_nonsecure_entry, optimize(0))) +UINT _tx_thread_secure_mode_stack_initialize(void) { - ULONG control; - - /* Set secure mode to use PSP. */ - asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ - control |= 2; /* Use PSP. */ - asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - asm volatile("MSR PSPLIM, %0" :: "r" (0)); - asm volatile("MSR PSP, %0" :: "r" (0)); - - return; +UINT status; +ULONG control; +ULONG ipsr; + + /* Make sure function is called from interrupt (threads should not call). */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ + control |= 2; /* Use PSP. */ + asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + asm volatile("MSR PSPLIM, %0" :: "r" (0)); + asm volatile("MSR PSP, %0" :: "r" (0)); + + status = TX_SUCCESS; + } + return status; } diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S index 1dfbc482..90427e36 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -80,7 +80,6 @@ _tx_alloc_return: BEQ _alloc_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _alloc_return_interrupt_enabled: diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S index cfe400fa..da5026d5 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S @@ -55,7 +55,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -78,7 +78,6 @@ _tx_free_return: BEQ _free_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _free_return_interrupt_enabled: diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S index 704c5dfd..bd9fe738 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c index ef98240c..8e3cff23 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c @@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c index ffd78d08..75ad1f32 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S index 7aa911b0..cf3536d5 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S @@ -71,7 +71,7 @@ .thumb_func .type _tx_thread_system_return, function _tx_thread_system_return: - /* Return to real scheduler via PendSV. Note that this routine is often + /* Return to real scheduler via PendSV. Note that this routine is often replaced with in-line assembly in tx_port.h to improved performance. */ LDR r0, =0x10000000 // Load PENDSVSET bit diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S index 0e2ea836..7b42d195 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -80,8 +79,7 @@ _tx_timer_interrupt: /* Increment the system clock. */ // _tx_timer_system_clock++; - MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock - MOVT r1, #:upper16:_tx_timer_system_clock + LDR r1, =_tx_timer_system_clock // Pickup address of system clock LDR r0, [r1, #0] // Pickup system clock ADDS r0, r0, #1 // Increment system clock STR r0, [r1, #0] // Store new system clock @@ -90,28 +88,27 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice - MOVT r3, #:upper16:_tx_timer_time_slice + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUBS r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOVW r0, #1 // Build expired value STR r0, [r3, #0] // Set time-slice expiration flag @@ -123,18 +120,16 @@ __tx_timer_no_time_slice: // if (*_tx_timer_current_ptr) // { - MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address - MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address LDR r0, [r1, #0] // Pickup current timer LDR r2, [r0, #0] // Pickup timer list entry CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address - MOVT r3, #:upper16:_tx_timer_expired + LDR r3, =_tx_timer_expired // Pickup expiration flag address MOVW r2, #1 // Build expired value STR r2, [r3, #0] // Set expired flag B __tx_timer_done // Finished timer processing @@ -144,25 +139,23 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADDS r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) - MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end - MOVT r3, #:upper16:_tx_timer_list_end + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; - MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start - MOVT r3, #:upper16:_tx_timer_list_start + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start __tx_timer_skip_wrap: @@ -172,18 +165,15 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag LDR r2, [r3, #0] // Pickup time-slice expired flag CBNZ r2, __tx_something_expired // Did a time-slice expire? // If non-zero, time-slice expired - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_nothing_expired // Did a timer expire? // No, nothing expired @@ -197,14 +187,13 @@ __tx_something_expired: // if (_tx_timer_expired) // { - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -215,28 +204,21 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR r2, [r3, #0] // Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing - MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag - MOVT r0, #:upper16:_tx_thread_preempt_disable - + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag LDR r1, [r0] // Is the preempt disable flag set? CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic - MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address - MOVT r0, #:upper16:_tx_thread_current_ptr - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r1, [r0] // Pickup the current thread pointer - MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address - MOVT r2, #:upper16:_tx_thread_execute_ptr - + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register LDR r2, =0x10000000 // Build value for PendSV bit @@ -248,8 +230,8 @@ __tx_timer_skip_time_slice: __tx_timer_not_ts_expiration: - POP {r0, r1} // Recover lr register (r0 is just there for - MOV lr, r1 // the 8-byte stack alignment + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment // } @@ -257,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c index 35482b6c..9e985efa 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c index 950e8ec0..c3ef9577 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s index 92a5f4d2..6f57db2f 100644 --- a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_timer_interrupt @@ -28,135 +27,123 @@ EXTERN __vector_table EXTERN _tx_thread_current_ptr EXTERN _tx_thread_stack_error_handler -; -; + SYSTEM_CLOCK EQU 96000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) -; -; + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start DS32 4 -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_initialize_low_level(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { PUBLIC _tx_initialize_low_level _tx_initialize_low_level: -; -; /* Disable interrupts during ThreadX initialization. */ -; + + /* Disable interrupts during ThreadX initialization. */ CPSID i -; -; /* Set base of available memory to end of non-initialised RAM area. */ -; - LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer - LDR r1, =__tx_free_memory_start ; Build first free address - STR r1, [r0] ; Setup first unused memory pointer -; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000ED08 ; Build address of NVIC registers - LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; -; /* Enable the cycle count register. */ -; -; LDR r0, =0xE0001000 ; Build address of DWT register -; LDR r1, [r0] ; Pickup the current value -; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__vector_table ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; -; /* Configure SysTick. */ -; - LDR r0, =0xE000E000 ; Build address of NVIC registers + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__tx_free_memory_start // Build first free address + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + LDR r0, =0xE000ED08 // Build address of NVIC registers + LDR r1, =__vector_table // Pickup address of vector table + STR r1, [r0] // Set vector table address + + /* Enable the cycle count register. */ +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + LDR r0, =0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] ; Setup SysTick Reload Value - MOV r1, #0x7 ; Build SysTick Control Enable Value - STR r1, [r0, #0x10] ; Setup SysTick Control -; -; /* Configure handler priorities. */ -; - LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD18 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD18 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 4-7 Priority Registers - LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD1C ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers - ; Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD1C // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF - LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD20 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers - ; Note: PnSV must be lowest priority, which is 0xFF -; -; /* Return to caller. */ -; + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD20 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ BX lr -;} -; -; -;/* Define shells for each of the unused vectors. */ -; +// } + + +/* Define shells for each of the unused vectors. */ + PUBLIC __tx_BadHandler __tx_BadHandler: B __tx_BadHandler @@ -164,40 +151,48 @@ __tx_BadHandler: PUBLIC __tx_IntHandler __tx_IntHandler: -; VOID InterruptHandler (VOID) -; { - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) - -; /* Do interrupt handler work here */ -; /* .... */ - +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + /* Do interrupt handler work here */ + /* .... */ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr -; } +// } PUBLIC __tx_SysTickHandler PUBLIC SysTick_Handler SysTick_Handler: __tx_SysTickHandler: -; VOID TimerInterruptHandler (VOID) -; { -; - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr -; } - +// } PUBLIC HardFault_Handler HardFault_Handler: - ; A stack overflow will trigger a hardfault. - ; There is no CFSR in M23, so we will not try to - ; determine if the fault is caused by a stack overflow - ; or some other condition. + // A stack overflow will trigger a hardfault. + // There is no CFSR in M23, so we will not try to + // determine if the fault is caused by a stack overflow + // or some other condition. B HardFault_Handler diff --git a/ports_module/cortex_m23/iar/inc/tx_secure_interface.h b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h index c2779f40..0a2bdd67 100644 --- a/ports_module/cortex_m23/iar/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_initialize_low_level.s b/ports_module/cortex_m23/iar/module_manager/src/tx_initialize_low_level.s deleted file mode 100644 index 92a5f4d2..00000000 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_initialize_low_level.s +++ /dev/null @@ -1,204 +0,0 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_initialize_unused_memory - EXTERN _tx_timer_interrupt - EXTERN __main - EXTERN __vector_table - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_stack_error_handler -; -; -SYSTEM_CLOCK EQU 96000000 -SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) -; -; - RSEG FREE_MEM:DATA - PUBLIC __tx_free_memory_start -__tx_free_memory_start - DS32 4 -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_initialize_low_level(VOID) -;{ - PUBLIC _tx_initialize_low_level -_tx_initialize_low_level: -; -; /* Disable interrupts during ThreadX initialization. */ -; - CPSID i -; -; /* Set base of available memory to end of non-initialised RAM area. */ -; - LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer - LDR r1, =__tx_free_memory_start ; Build first free address - STR r1, [r0] ; Setup first unused memory pointer -; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000ED08 ; Build address of NVIC registers - LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; -; /* Enable the cycle count register. */ -; -; LDR r0, =0xE0001000 ; Build address of DWT register -; LDR r1, [r0] ; Pickup the current value -; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__vector_table ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; -; /* Configure SysTick. */ -; - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] ; Setup SysTick Reload Value - MOV r1, #0x7 ; Build SysTick Control Enable Value - STR r1, [r0, #0x10] ; Setup SysTick Control -; -; /* Configure handler priorities. */ -; - LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD18 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers - - LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD1C ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers - ; Note: SVC must be lowest priority, which is 0xFF - - LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD20 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers - ; Note: PnSV must be lowest priority, which is 0xFF -; -; /* Return to caller. */ -; - BX lr -;} -; -; -;/* Define shells for each of the unused vectors. */ -; - PUBLIC __tx_BadHandler -__tx_BadHandler: - B __tx_BadHandler - - - PUBLIC __tx_IntHandler -__tx_IntHandler: -; VOID InterruptHandler (VOID) -; { - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) - -; /* Do interrupt handler work here */ -; /* .... */ - - POP {r0, r1} - MOV lr, r1 - BX lr -; } - - - PUBLIC __tx_SysTickHandler - PUBLIC SysTick_Handler -SysTick_Handler: -__tx_SysTickHandler: -; VOID TimerInterruptHandler (VOID) -; { -; - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) - BL _tx_timer_interrupt - POP {r0, r1} - MOV lr, r1 - BX lr -; } - - - PUBLIC HardFault_Handler -HardFault_Handler: - ; A stack overflow will trigger a hardfault. - ; There is no CFSR in M23, so we will not try to - ; determine if the fault is caused by a stack overflow - ; or some other condition. - B HardFault_Handler - - - END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s index 48300c4d..81fa6815 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s @@ -1,72 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN _tx_execution_isr_exit SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is not needed for Cortex-M. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* None */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_restore(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -; -; /* Return to interrupt processing. */ -; + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr -;} +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s index f666d4a4..2ad3e476 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s @@ -1,72 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN _tx_execution_isr_enter SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is not needed for Cortex-M. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* None */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_save(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { PUBLIC _tx_thread_context_save _tx_thread_context_save: -; -; /* Return to interrupt processing. */ -; + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + BX lr -;} +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s index 83381d72..d9ee6e88 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,77 +1,72 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_control(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: -; -; /* Pickup current interrupt lockout posture. */ -; - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr -; -;} + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s index 41ad894f..010d3331 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,76 +1,72 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts and returning */ -;/* the previous interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_disable(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { PUBLIC _tx_thread_interrupt_disable _tx_thread_interrupt_disable: -; -; /* Return current interrupt lockout posture. */ -; + /* Return current interrupt lockout posture. */ MRS r0, PRIMASK CPSID i BX lr -; -;} +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s index dd1c2985..054d3d8e 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,75 +1,71 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring the previous */ -;/* interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* previous_posture Previous interrupt posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_interrupt_restore(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { PUBLIC _tx_thread_interrupt_restore _tx_thread_interrupt_restore: -; -; /* Restore previous interrupt lockout posture. */ -; + /* Restore previous interrupt lockout posture. */ MSR PRIMASK, r0 BX lr -; -;} +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s index 53bda596..e523070f 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s @@ -81,29 +81,24 @@ // { PUBLIC _tx_thread_schedule _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOVW r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR @@ -222,19 +217,18 @@ BusFault_Handler: PendSV_Handler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function POP {r0, r1} // Recover LR - MOV lr, r1 + MOV lr, r1 // CPSIE i // Enable interrupts #endif - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address - MOVW r3, #0 // Build NULL value LDR r1, [r0] // Pickup current thread pointer @@ -247,18 +241,18 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 // Allocate stack space - STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4, r8 // - MOV r5, r9 // - MOV r6, r10 // - MOV r7, r11 // + STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // Copy r8-r11 to multisave registers + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 SUBS r3, r3, #32 // Allocate stack space - STM r3!, {r4-r7} // + STM r3!, {r4-r7} // Save r8-r11 SUBS r3, r3, #20 // Allocate stack space - MOV r5, lr // - STR r5, [r3] // Save LR on the stack + MOV r5, lr // Copy lr to saveable register + STR r5, [r3] // Save lr on the stack STR r3, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, =0xC4 // Secure stack index offset @@ -340,7 +334,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -419,7 +413,6 @@ skip_mpu_setup: BX lr // Return to thread! - /* SVC Handler. */ PUBLIC SVC_Handler SVC_Handler: @@ -427,10 +420,10 @@ SVC_Handler: MOVS r1, #0x04 TST r1, r0 // Determine return stack from EXC_RETURN bit 2 BEQ _tx_load_msp - MRS r0, PSP // Get PSP + MRS r0, PSP // Get PSP if return stack is PSP B _tx_get_svc _tx_load_msp: - MRS r0, MSP // Get MSP + MRS r0, MSP // Get MSP if return stack is MSP _tx_get_svc: LDR r1, [r0,#24] // Load saved PC from stack LDR r3, =-2 @@ -451,7 +444,7 @@ _tx_get_svc: /* At this point we have an SVC 3, which means we are entering the kernel from a module thread with user mode selected. */ - LDR r2, =_txm_module_priv // Load address of where we should have come from + LDR r2, =_txm_module_priv-1 // Load address of where we should have come from CMP r1, r2 // Did we come from user_mode_entry? BEQ _tx_entry_continue // If no (not equal), then... BX lr // return from where we came. @@ -514,7 +507,7 @@ _tx_skip_kernel_stack_enter: _tx_thread_user_return: - LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + LDR r2, =_txm_module_user_mode_exit-1 // Load address of where we should have come from CMP r1, r2 // Did we come from user_mode_exit? BEQ _tx_exit_continue // If no (not equal), then... BX lr // return from where we came. @@ -551,14 +544,14 @@ _tx_exit_continue: MRS r3, PSP // Pickup kernel stack pointer /* Copy kernel hardware stack to module thread stack. */ - LDM r3!,{r1-r2} // Get r0, r1 from kernel stack - STM r0!,{r1-r2} // Insert r0, r1 into thread stack - LDM r3!,{r1-r2} // Get r2, r3 from kernel stack - STM r0!,{r1-r2} // Insert r2, r3 into thread stack - LDM r3!,{r1-r2} // Get r12, lr from kernel stack - STM r0!,{r1-r2} // Insert r12, lr into thread stack - LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack - STM r0!,{r1-r2} // Insert pc, xpsr into thread stack + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUBS r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -576,7 +569,7 @@ _tx_skip_kernel_stack_exit: #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) _tx_svc_secure_alloc: - LDR r2, =_tx_alloc_return // Load address of where we should have come from + LDR r2, =_tx_alloc_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? BEQ _tx_alloc_continue // If no (not equal), then... BX lr // return from where we came. @@ -590,7 +583,7 @@ _tx_alloc_continue: BX lr _tx_svc_secure_free: - LDR r2, =_tx_free_return // Load address of where we should have come from + LDR r2, =_tx_free_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? BEQ _tx_free_continue // If no (not equal), then... BX lr // return from where we came. @@ -602,7 +595,7 @@ _tx_free_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c index d7e96333..1bb31a36 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c @@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M23/IAR */ -/* 6.1.1 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M23/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ @@ -98,21 +98,35 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 08-02-2021 Scott Larson Modified comment(s), changed */ +/* name, execute in handler */ +/* mode, disable optimization, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +UINT _tx_thread_secure_mode_stack_initialize(void) { - - /* Set secure mode to use PSP. */ - __set_CONTROL(__get_CONTROL() | 2); - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - __set_PSPLIM(0); - __set_PSP(0); - - return; +UINT status; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + status = TX_SUCCESS; + } + return status; } @@ -294,7 +308,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -379,7 +393,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s index 9ae3dcdb..b88e9f4c 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s @@ -1,82 +1,82 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_secure_stack_allocate Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function enters the SVC handler to allocate a secure stack. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Thread control block pointer */ -;/* stack_size Size of secure stack to */ -;/* allocate */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* status Actual completion status */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { EXPORT _tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate: #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) - MRS r3, PRIMASK ; Save interrupt mask - CPSIE i ; Enable interrupts for SVC call + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call SVC 1 - CMP r3, #0 ; If interrupts enabled, just return + EXPORT _tx_alloc_return +_tx_alloc_return: + CMP r3, #0 // If interrupts enabled, just return BEQ _alloc_return_interrupt_enabled - CPSID i ; Otherwise, disable interrupts + CPSID i // Otherwise, disable interrupts #else - MOV32 r0, #0xFF ; Feature not enabled + MOVS r0, #0xFF // Feature not enabled #endif -_alloc_return_interrupt_enabled +_alloc_return_interrupt_enabled: BX lr - END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s index b8e5bef8..f4606d46 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s @@ -1,79 +1,80 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_secure_stack_free Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function enters the SVC handler to free a secure stack. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Thread control block pointer */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* status Actual completion status */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 2 */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { EXPORT _tx_thread_secure_stack_free _tx_thread_secure_stack_free: #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) - MRS r3, PRIMASK ; Save interrupt mask - CPSIE i ; Enable interrupts for SVC call + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call SVC 2 - CMP r3, #0 ; If interrupts enabled, just return + EXPORT _tx_free_return +_tx_free_return: + CMP r3, #0 // If interrupts enabled, just return BEQ _free_return_interrupt_enabled - CPSID i ; Otherwise, disable interrupts + CPSID i // Otherwise, disable interrupts #else - MOV32 r0, #0xFF ; Feature not enabled + MOVS r0, #0xFF // Feature not enabled #endif -_free_return_interrupt_enabled +_free_return_interrupt_enabled: BX lr END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s index 6525df4a..204be424 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s @@ -1,138 +1,136 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M23/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { PUBLIC _tx_thread_stack_build _tx_thread_stack_build: -; -; /* Build a fake interrupt frame. The form of the fake interrupt stack -; on the Cortex-M23 should look like the following after it is built: -; -; Stack Top: -; LR Interrupted LR (LR at time of PENDSV) -; r8 Initial value for r8 -; r9 Initial value for r9 -; r10 Initial value for r10 -; r11 Initial value for r11 -; r4 Initial value for r4 -; r5 Initial value for r5 -; r6 Initial value for r6 -; r7 Initial value for r7 -; r0 Initial value for r0 (Hardware stack starts here!!) -; r1 Initial value for r1 -; r2 Initial value for r2 -; r3 Initial value for r3 -; r12 Initial value for r12 -; lr Initial value for lr -; pc Initial value for pc -; xPSR Initial value for xPSR -; -; Stack Bottom: (higher memory address) */ -; - LDR r2, [r0, #16] ; Pickup end of stack area - MOVS r3, #0x7 ; - BICS r2, r2, r3 ; Align frame for 8-byte alignment - SUBS r2, r2, #68 ; Subtract frame size + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M23 should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE - LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode #else - LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP #endif - STR r3, [r2, #0] ; Save on the stack -; -; /* Actually build the stack frame. */ -; - MOV r3, #0 ; Build initial register value - STR r3, [r2, #4] ; Store initial r8 - STR r3, [r2, #8] ; Store initial r9 - STR r3, [r2, #12] ; Store initial r10 - STR r3, [r2, #16] ; Store initial r11 - STR r3, [r2, #20] ; Store initial r4 - STR r3, [r2, #24] ; Store initial r5 - STR r3, [r2, #28] ; Store initial r6 - STR r3, [r2, #32] ; Store initial r7 -; -; /* Hardware stack follows. */ -; - STR r3, [r2, #36] ; Store initial r0 - STR r3, [r2, #40] ; Store initial r1 - STR r3, [r2, #44] ; Store initial r2 - STR r3, [r2, #48] ; Store initial r3 - STR r3, [r2, #52] ; Store initial r12 - LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value - STR r3, [r2, #56] ; Store initial lr - STR r1, [r2, #60] ; Store initial pc - LDR r3, =0x01000000 ; Only T-bit need be set - STR r3, [r2, #64] ; Store initial xPSR -; -; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = r2; -; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block - BX lr ; Return to caller -;} + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #8] // Store initial r9 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c index ef98240c..8e3cff23 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c @@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c index ffd78d08..75ad1f32 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s index 1afb41f6..4c977e88 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s @@ -1,87 +1,84 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_system_return(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { PUBLIC _tx_thread_system_return -_tx_thread_system_return??rA: _tx_thread_system_return: -; -; /* Return to real scheduler via PendSV. Note that this routine is often -; replaced with in-line assembly in tx_port.h to improved performance. */ -; - LDR r0, =0x10000000 ; Load PENDSVSET bit - LDR r1, =0xE000ED04 ; Load ICSR address - STR r0, [r1] ; Set PENDSVBIT in ICSR - MRS r0, IPSR ; Pickup IPSR - CMP r0, #0 ; Is it a thread returning? - BNE _isr_context ; If ISR, skip interrupt enable - MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK - CPSIE i ; Enable interrupts - MSR PRIMASK, r1 ; Restore original interrupt posture + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture _isr_context: - BX lr ; Return to caller -;} + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s index 89e185b3..df397a64 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock EXTERN _tx_timer_current_ptr @@ -33,224 +32,220 @@ EXTERN _tx_thread_current_ptr EXTERN _tx_thread_execute_ptr EXTERN _tx_thread_preempt_disable -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* the expiration functions are called. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_timer_interrupt(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* expiration functions are called. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { PUBLIC _tx_timer_interrupt _tx_timer_interrupt: -; -; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available -; for use. */ -; -; /* Increment the system clock. */ -; _tx_timer_system_clock++; -; - MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock - LDR r0, [r1, #0] ; Pickup system clock - ADDS r0, r0, #1 ; Increment system clock - STR r0, [r1, #0] ; Store new system clock -; -; /* Test for time-slice expiration. */ -; if (_tx_timer_time_slice) -; { -; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice - LDR r2, [r3, #0] ; Pickup time-slice - CBZ r2, __tx_timer_no_time_slice ; Is it non-active? - ; Yes, skip time-slice processing -; -; /* Decrement the time_slice. */ -; _tx_timer_time_slice--; -; - SUBS r2, r2, #1 ; Decrement the time-slice - STR r2, [r3, #0] ; Store new time-slice value -; -; /* Check for expiration. */ -; if (__tx_timer_time_slice == 0) -; - CBNZ r2, __tx_timer_no_time_slice ; Has it expired? -; -; /* Set the time-slice expired flag. */ -; _tx_timer_expired_time_slice = TX_TRUE; -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag - MOV r0, #1 ; Build expired value - STR r0, [r3, #0] ; Set time-slice expiration flag -; -; } -; + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADDS r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUBS r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOVW r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + __tx_timer_no_time_slice: -; -; /* Test for timer expiration. */ -; if (*_tx_timer_current_ptr) -; { -; - MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address - LDR r0, [r1, #0] ; Pickup current timer - LDR r2, [r0, #0] ; Pickup timer list entry - CBZ r2, __tx_timer_no_timer ; Is there anything in the list? - ; No, just increment the timer -; -; /* Set expiration flag. */ -; _tx_timer_expired = TX_TRUE; -; - MOV32 r3, _tx_timer_expired ; Pickup expiration flag address - MOV r2, #1 ; Build expired value - STR r2, [r3, #0] ; Set expired flag - B __tx_timer_done ; Finished timer processing -; -; } -; else -; { + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOVW r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { __tx_timer_no_timer: -; -; /* No timer expired, increment the timer pointer. */ -; _tx_timer_current_ptr++; -; - ADDS r0, r0, #4 ; Move to next timer -; -; /* Check for wrap-around. */ -; if (_tx_timer_current_ptr == _tx_timer_list_end) -; - MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end - LDR r2, [r3, #0] ; Pickup list end - CMP r0, r2 ; Are we at list end? - BNE __tx_timer_skip_wrap ; No, skip wrap-around logic -; -; /* Wrap to beginning of list. */ -; _tx_timer_current_ptr = _tx_timer_list_start; -; - MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start - LDR r0, [r3, #0] ; Set current pointer to list start -; + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADDS r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + __tx_timer_skip_wrap: -; - STR r0, [r1, #0] ; Store new current timer pointer -; } -; + + STR r0, [r1, #0] // Store new current timer pointer + // } + __tx_timer_done: -; -; -; /* See if anything has expired. */ -; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag - LDR r2, [r3, #0] ; Pickup time-slice expired flag - CBNZ r2, __tx_something_expired ; Did a time-slice expire? - ; If non-zero, time-slice expired - MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? - ; No, nothing expired -; + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + __tx_something_expired: -; -; - STMDB sp!, {r0, lr} ; Save the lr register on the stack - ; and save r0 just to keep 8-byte alignment -; -; /* Did a timer expire? */ -; if (_tx_timer_expired) -; { -; - MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_dont_activate ; Check for timer expiration - ; If not set, skip timer activation -; -; /* Process timer expiration. */ -; _tx_timer_expiration_process(); -; - BL _tx_timer_expiration_process ; Call the timer expiration handling routine -; -; } + + PUSH {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } __tx_timer_dont_activate: -; -; /* Did time slice expire? */ -; if (_tx_timer_expired_time_slice) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired - LDR r2, [r3, #0] ; Pickup the actual flag - CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set - ; No, skip time-slice processing -; -; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); - BL _tx_thread_time_slice ; Call time-slice processing - MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag - LDR r1, [r0] ; Is the preempt disable flag set? - CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - LDR r1, [r0] ; Pickup the current thread pointer - MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address - LDR r3, [r2] ; Pickup the execute thread pointer - MOV32 r0, 0xE000ED04 ; Build address of control register - MOV32 r2, 0x10000000 ; Build value for PendSV bit - CMP r1, r3 ; Are they the same? - BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed - STR r2, [r0] ; Not the same, issue the PendSV for preemption + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: -; -; } -; + // } + __tx_timer_not_ts_expiration: -; - POP {r0, r1} ; Recover lr register (r0 is just there for - MOV lr, r1 ; the 8-byte stack alignment -; -; } -; + + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment + + // } + __tx_timer_nothing_expired: - DSB ; Complete all memory access - BX lr ; Return to caller -; -;} + DSB // Complete all memory access + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c index 35482b6c..9e985efa 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c index 950e8ec0..c3ef9577 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) |