diff options
| author | Yuxin Zhou <[email protected]> | 2021-07-28 07:24:02 +0000 |
|---|---|---|
| committer | Yuxin Zhou <[email protected]> | 2021-07-28 07:24:02 +0000 |
| commit | d0dab582506f132690b35b36ffea129ad51110b0 (patch) | |
| tree | 13add80dd314dc38efc1830f3d1f36b5a2596e98 /ports_module/cortex_m3/ac6 | |
| parent | 244365fc6a937c754cfc6bb8e6895dc6f37bac0e (diff) | |
Release 6.1.8v6.1.8_rel
Diffstat (limited to 'ports_module/cortex_m3/ac6')
16 files changed, 165 insertions, 163 deletions
diff --git a/ports_module/cortex_m3/ac6/inc/txm_module_port.h b/ports_module/cortex_m3/ac6/inc/txm_module_port.h index 90975e6c..82b9721c 100644 --- a/ports_module/cortex_m3/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac6/inc/txm_module_port.h @@ -94,21 +94,16 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ + +/* Size of module heap. */ +#define TXM_MODULE_HEAP_SIZE 512 + + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif -/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) - * to reflect your system memory attributes (cache, shareable, memory type). */ -/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 -/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 -/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 - - /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -159,13 +154,13 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for ARM compiler. */ +/* Define INLINE_DECLARE to inline for AC6 compiler. */ #define INLINE_DECLARE inline -/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total - entries, since ThreadX uses one for access to the kernel dispatch function. */ - +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 #define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 @@ -217,18 +212,6 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_FAULT_INFO \ TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; -/* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ - ULONG stack_available; \ - __asm("MOV %0, SP" : "=r"(stack_available)); \ - stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ - if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ - (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ - { \ - return(TX_SIZE_ERROR); \ - } - - /* Define the macro to check the code alignment. */ #define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ @@ -344,7 +327,7 @@ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); ULONG _txm_module_manager_region_size_get(ULONG block_size); #define TXM_MODULE_MANAGER_VERSION_ID \ -CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC6 Version 6.1 *"; +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC6 Version 6.1.8 *"; #endif diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S index 455e86b5..cc4bdcc1 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S @@ -2,6 +2,7 @@ /* */ /* Copyright (c) Microsoft Corporation. All rights reserved. */ /* */ +/* This software is licensed under the Microsoft Software License */ /* Terms for Microsoft Azure RTOS. Full text of the license can be */ /* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ /* and in the root directory of this software. */ @@ -19,11 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - .global __use_two_region_memory .global __scatterload - .eabi_attribute Tag_ABI_PCS_RO_data, 1 .eabi_attribute Tag_ABI_PCS_R9_use, 1 .eabi_attribute Tag_ABI_PCS_RW_data, 2 diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c index 34ec131d..e6ebe65f 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -89,7 +89,7 @@ extern VOID _txm_module_initialize(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,14 +106,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the ARM C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S index da83909f..17a79b0f 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,9 @@ /**************************************************************************/ /**************************************************************************/ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif .text .align 4 @@ -28,20 +31,16 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_context_restore Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ /* This function is only needed for legacy applications and it should */ /* not be called in any new development on a Cortex-M. */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ /* */ /* INPUT */ /* */ @@ -53,7 +52,7 @@ /* */ /* CALLS */ /* */ -/* _tx_thread_schedule Thread scheduling routine */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -63,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -71,6 +70,13 @@ .global _tx_thread_context_restore .thumb_func _tx_thread_context_restore: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S index e48108d5..511ca82e 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S @@ -20,27 +20,26 @@ /**************************************************************************/ /**************************************************************************/ - .text .align 4 .syntax unified +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_context_save Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ /* This function is only needed for legacy applications and it should */ /* not be called in any new development on a Cortex-M. */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ /* */ /* INPUT */ /* */ @@ -52,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -62,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -70,6 +69,15 @@ .global _tx_thread_context_save .thumb_func _tx_thread_context_save: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + + /* Context is already saved - just return. */ + BX lr // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S index 7336051f..07d2a131 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -@/* _tx_thread_interrupt_control Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_interrupt_control Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) @@ -66,15 +66,14 @@ .global _tx_thread_interrupt_control .thumb_func _tx_thread_interrupt_control: - - // Pickup current interrupt lockout posture. - - MRS r1, PRIMASK // Pickup current interrupt lockout - - // Apply the new interrupt posture. - - MSR PRIMASK, r0 // Apply the new interrupt lockout - MOV r0, r1 // Transfer old to return register - BX lr // Return to caller - +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S index b7615814..345ab227 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S @@ -20,18 +20,21 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_thread_current_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_thread_system_stack_ptr - .global _tx_thread_preempt_disable - .global _txm_module_manager_memory_fault_handler - .global _txm_module_manager_memory_fault_info -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - .global _tx_execution_thread_enter - .global _tx_execution_thread_exit + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit #endif - .text .align 4 .syntax unified @@ -73,7 +76,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -84,7 +87,7 @@ _tx_thread_schedule: /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -99,7 +102,6 @@ _tx_thread_schedule: STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -188,10 +190,8 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function CPSIE i // Enable interrupts @@ -224,10 +224,8 @@ __tx_PendSVHandler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function @@ -294,10 +292,8 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ - PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function POP {r0, r1} // Recover r0 and r1 @@ -324,10 +320,10 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block - LDM r0!,{r2-r9} // Load MPU regions 0-3 - STM r1,{r2-r9} // Store MPU regions 0-3 - LDM r0!,{r2-r9} // Load MPU regions 4-7 - STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load first four MPU regions + STM r1,{r2-r9} // Store first four MPU regions + LDM r0,{r2-r9} // Load second four MPU regions + STM r1,{r2-r9} // Store second four MPU regions LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU @@ -349,11 +345,25 @@ __tx_ts_wait: LDR r1, [r2] // Pickup the next thread to execute pointer STR r1, [r0] // Store it in the current pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + CPSIE i // Enable interrupts B __tx_ts_wait // Loop to continue waiting @@ -369,6 +379,7 @@ __tx_ts_ready: CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } /* SVC Handler. */ @@ -393,6 +404,7 @@ __tx_SVCallHandler: the kernel from a module thread with user mode selected. */ LDR r2, =_txm_module_priv // Load address of where we should have come from + // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_entry? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -425,14 +437,14 @@ __tx_SVCallHandler: /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} MSR PSP, r0 // Set kernel stack pointer @@ -444,6 +456,7 @@ _tx_skip_kernel_stack_enter: _tx_thread_user_return: LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_exit? IT NE // If no (not equal), then... BXNE lr // return from where we came @@ -471,14 +484,14 @@ _tx_thread_user_return: MRS r3, PSP // Pickup kernel stack pointer /* Copy kernel hardware stack to module thread stack. */ - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -493,10 +506,10 @@ _tx_skip_kernel_stack_exit: BX lr // Return to thread - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch - .align 5 + .align 5 .syntax unified // VOID _txm_module_manager_user_mode_entry(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S index 548fe34a..d50f9243 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - .text .align 4 .syntax unified @@ -28,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_stack_build Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -61,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -70,7 +69,6 @@ .thumb_func _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: @@ -96,7 +94,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - BIC r2, r2, #0x7 // Align frame + BIC r2, r2, #0x7 // Align frame for 8-byte alignment SUB r2, r2, #68 // Subtract frame size LDR r3, =0xFFFFFFFD // Build initial LR value STR r3, [r2, #0] // Save on the stack diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S index 1639bbf2..6560db62 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - .text 32 .align 4 .syntax unified @@ -28,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_system_return Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -61,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -79,10 +78,16 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S index 2cbef75d..46f54da0 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S @@ -20,17 +20,15 @@ /**************************************************************************/ /**************************************************************************/ - - .global _tx_timer_time_slice - .global _tx_timer_system_clock - .global _tx_timer_current_ptr - .global _tx_timer_list_start - .global _tx_timer_list_end - .global _tx_timer_expired_time_slice - .global _tx_timer_expired - .global _tx_thread_time_slice - .global _tx_timer_expiration_process - + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process .text .align 4 @@ -39,19 +37,18 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_timer_interrupt Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -74,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -83,8 +80,7 @@ .thumb_func _tx_timer_interrupt: - /* Upon entry to this routine, it is assumed that context save has already - been called, and therefore the compiler scratch registers are available + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available for use. */ /* Increment the system clock. */ @@ -176,7 +172,6 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { @@ -192,7 +187,6 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment @@ -253,5 +247,4 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 59be7606..85f06b66 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 475fc5a2..0e57c7c1 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index c670a087..b435d107 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 5249a938..f83a982f 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index df21aab9..a2e4dfa1 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 98982a1f..9d0b5a06 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -23,7 +23,6 @@ .text .align 4 .syntax unified - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -61,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -73,8 +72,8 @@ _txm_module_manager_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: - Stack Top: - LR Interrupted LR (LR at time of PENDSV) + Stack Top: + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 @@ -111,7 +110,7 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #28] // Store initial r10 STR r3, [r2, #32] // Store initial r11 - /* Hardware stack follows. */ + /* Hardware stack follows. */ STR r0, [r2, #36] // Store initial r0, which is the thread control block @@ -138,4 +137,3 @@ _txm_module_manager_thread_stack_build: STR r2, [r0, #8] // Save stack pointer in thread's control block BX lr // Return to caller // } - |