Release 6.1.12v6.1.12_rel

4 files changed, 151 insertions, 37 deletions

diff --git a/ports_module/cortex_m3/gnu/example_build/build_threadx_sample.bat b/ports_module/cortex_m3/gnu/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..af3156de
--- /dev/null
+++ b/ports_module/cortex_m3/gnu/example_build/build_threadx_sample.bat
@@ -0,0 +1,4 @@
+arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc sample_threadx.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_simulator_startup.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb cortexm_crt0.S
+arm-none-eabi-ld -A cortex-m3 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm_crt0.o sample_threadx.o tx.a libc.a -o sample_threadx.axf -M > sample_threadx.map
diff --git a/ports_module/cortex_m3/gnu/inc/txm_module_port.h b/ports_module/cortex_m3/gnu/inc/txm_module_port.h
index 58ed9614..c77eb2f0 100644
--- a/ports_module/cortex_m3/gnu/inc/txm_module_port.h
+++ b/ports_module/cortex_m3/gnu/inc/txm_module_port.h
@@ -26,7 +26,7 @@
 /*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
 /*                                                                        */
 /*    txm_module_port.h                                 Cortex-M3/GNU     */
-/*                                                           6.1.9        */
+/*                                                           6.1.12       */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -41,6 +41,9 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  10-15-2021      Scott Larson            Initial Version 6.1.9         */
+/*  07-29-2022      Scott Larson            Enabled user-defined and      */
+/*                                            default MPU settings,       */
+/*                                            resulting in version 6.1.12 */
 /*                                                                        */
 /**************************************************************************/
 
@@ -111,6 +114,60 @@ The following extensions must also be defined in tx_port.h:
 #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL    0x12070000
 #endif
 
+/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15)
+   are not used by ThreadX. These may be defined by the user.  */
+#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12     0
+#define TXM_MODULE_MPU_USER_DEFINED_RASR_12     0
+#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13     0
+#define TXM_MODULE_MPU_USER_DEFINED_RASR_13     0
+#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14     0
+#define TXM_MODULE_MPU_USER_DEFINED_RASR_14     0
+#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15     0
+#define TXM_MODULE_MPU_USER_DEFINED_RASR_15     0
+
+
+/* Users can define these default MPU configuration values.
+
+   If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled
+   when a thread that is not owned by a module is running
+   and the defines below are not used.
+
+   If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the
+   below values when a thread that is not owned by a module is running.  */
+#define TXM_MODULE_MPU_DEFAULT_RBAR_0           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_0           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_1           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_1           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_2           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_2           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_3           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_3           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_4           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_4           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_5           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_5           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_6           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_6           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_7           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_7           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_8           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_8           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_9           0
+#define TXM_MODULE_MPU_DEFAULT_RASR_9           0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_10          0
+#define TXM_MODULE_MPU_DEFAULT_RASR_10          0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_11          0
+#define TXM_MODULE_MPU_DEFAULT_RASR_11          0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_12          0
+#define TXM_MODULE_MPU_DEFAULT_RASR_12          0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_13          0
+#define TXM_MODULE_MPU_DEFAULT_RASR_13          0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_14          0
+#define TXM_MODULE_MPU_DEFAULT_RASR_14          0
+#define TXM_MODULE_MPU_DEFAULT_RBAR_15          0
+#define TXM_MODULE_MPU_DEFAULT_RASR_15          0
+
+
 /* Define constants specific to the tools the module can be built with for this particular modules port.  */
 
 #define TXM_MODULE_IAR_COMPILER                 0x00000000
@@ -376,6 +433,6 @@ UINT  _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance
 
 #define TXM_MODULE_MANAGER_VERSION_ID   \
 CHAR                            _txm_module_manager_version_id[] =  \
-                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Module Cortex-M3/GNU Version 6.1.9 *";
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Module Cortex-M3/GNU Version 6.1.12 *";
 
 #endif
diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S
index e5d101b5..a8b3894f 100644
--- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S
+++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S
@@ -40,7 +40,7 @@
 /*  FUNCTION                                               RELEASE        */
 /*                                                                        */
 /*    _tx_thread_schedule                               Cortex-M3/GNU     */
-/*                                                           6.1.11       */
+/*                                                           6.1.12       */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -78,6 +78,10 @@
 /*  04-25-2022      Scott Larson            Optimized MPU configuration,  */
 /*                                            added BASEPRI support,      */
 /*                                            resulting in version 6.1.11 */
+/*  07-29-2022      Scott Larson            Removed the code path to skip */
+/*                                            MPU reloading, optional     */
+/*                                            default MPU settings,       */
+/*                                            resulting in version 6.1.12 */
 /*                                                                        */
 /**************************************************************************/
 // VOID   _tx_thread_schedule(VOID)
@@ -398,26 +402,33 @@ __tx_ts_restore:
 
     LDR     r0, =0xE000ED94                         // Build MPU control reg address
     MOV     r3, #0                                  // Build disable value
+    CPSID   i                                       // Disable interrupts
     STR     r3, [r0]                                // Disable MPU
     LDR     r0, [r1, #0x90]                         // Pickup the module instance pointer
+#ifdef TXM_MODULE_MPU_DEFAULT
+    CBZ     r0, default_mpu                         // Is this thread owned by a module? No, default MPU setup
+#else
     CBZ     r0, skip_mpu_setup                      // Is this thread owned by a module? No, skip MPU setup
-    
+#endif
+
     LDR     r2, [r0, #0x8C]                         // Pickup MPU region 5 address
+#ifdef TXM_MODULE_MPU_DEFAULT
+    CBZ     r2, default_mpu                         // Is protection required for this module? No, default MPU setup
+#else
     CBZ     r2, skip_mpu_setup                      // Is protection required for this module? No, skip MPU setup
-    
-    // Is the MPU already set up for this module?
-    MOV     r1, #5                                  // Select region 5 from MPU
-    LDR     r3, =0xE000ED98                         // MPU_RNR register address
-    STR     r1, [r3]                                // Set region to 5
+#endif
     LDR     r1, =0xE000ED9C                         // MPU_RBAR register address
-    LDR     r3, [r1]                                // Load address stored in MPU region 5
-    BIC     r2, r2, #0x10                           // Clear VALID bit
-    CMP     r2, r3                                  // Is module already loaded?
-    BEQ     _tx_enable_mpu                          // Yes - skip MPU reconfiguration
 
     // Use alias registers to quickly load MPU
     ADD     r0, r0, #100                            // Build address of MPU register start in thread control block
 
+#ifdef TXM_MODULE_MPU_DEFAULT
+    B       config_mpu                              // configure MPU for module
+default_mpu:
+    LDR     r0, =txm_module_default_mpu_registers   // default MPU configuration
+#endif
+
+config_mpu:
     LDM     r0!,{r2-r9}                             // Load MPU regions 0-3
     STM     r1,{r2-r9}                              // Store MPU regions 0-3
     LDM     r0!,{r2-r9}                             // Load MPU regions 4-7
@@ -425,14 +436,17 @@ __tx_ts_restore:
 #ifdef TXM_MODULE_MANAGER_16_MPU
     LDM     r0!,{r2-r9}                             // Load MPU regions 8-11
     STM     r1,{r2-r9}                              // Store MPU regions 8-11
+    // Regions 12-15 are reserved for the user to define.
     LDM     r0,{r2-r9}                              // Load MPU regions 12-15
     STM     r1,{r2-r9}                              // Store MPU regions 12-15
 #endif
+
 _tx_enable_mpu:
     LDR     r0, =0xE000ED94                         // Build MPU control reg address
     MOV     r1, #5                                  // Build enable value with background region enabled
     STR     r1, [r0]                                // Enable MPU
 skip_mpu_setup:
+    CPSIE   i                                       // Enable interrupts
     LDMIA   r12!, {LR}                              // Pickup LR
 #ifdef __ARM_FP
     TST     LR, #0x10                               // Determine if the VFP extended frame is present
@@ -588,14 +602,14 @@ _tx_no_lazy_clear:
 #endif
 
     /* Copy kernel hardware stack to module thread stack. */
-    LDM     r3!, {r1-r2}
-    STM     r0!, {r1-r2}
-    LDM     r3!, {r1-r2}
-    STM     r0!, {r1-r2}
-    LDM     r3!, {r1-r2}
-    STM     r0!, {r1-r2}
-    LDM     r3!, {r1-r2}
-    STM     r0!, {r1-r2}
+    LDM     r3!, {r1-r2}                            // Get r0, r1 from kernel stack
+    STM     r0!, {r1-r2}                            // Insert r0, r1 into thread stack
+    LDM     r3!, {r1-r2}                            // Get r2, r3 from kernel stack
+    STM     r0!, {r1-r2}                            // Insert r2, r3 into thread stack
+    LDM     r3!, {r1-r2}                            // Get r12, lr from kernel stack
+    STM     r0!, {r1-r2}                            // Insert r12, lr into thread stack
+    LDM     r3!, {r1-r2}                            // Get pc, xpsr from kernel stack
+    STM     r0!, {r1-r2}                            // Insert pc, xpsr into thread stack
     SUB     r0, r0, #32                             // Subtract 32 to get back to top of stack
     MSR     PSP, r0                                 // Set thread stack pointer
 
diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c
index 48a14571..4a00404f 100644
--- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c
+++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c
@@ -25,6 +25,43 @@
 #include "tx_api.h"
 #include "txm_module.h"
 
+#ifdef TXM_MODULE_MPU_DEFAULT
+const ULONG txm_module_default_mpu_registers[32] =
+    {
+        TXM_MODULE_MPU_DEFAULT_RBAR_0,
+        TXM_MODULE_MPU_DEFAULT_RASR_0,
+        TXM_MODULE_MPU_DEFAULT_RBAR_1,
+        TXM_MODULE_MPU_DEFAULT_RASR_1,
+        TXM_MODULE_MPU_DEFAULT_RBAR_2,
+        TXM_MODULE_MPU_DEFAULT_RASR_2,
+        TXM_MODULE_MPU_DEFAULT_RBAR_3,
+        TXM_MODULE_MPU_DEFAULT_RASR_3,
+        TXM_MODULE_MPU_DEFAULT_RBAR_4,
+        TXM_MODULE_MPU_DEFAULT_RASR_4,
+        TXM_MODULE_MPU_DEFAULT_RBAR_5,
+        TXM_MODULE_MPU_DEFAULT_RASR_5,
+        TXM_MODULE_MPU_DEFAULT_RBAR_6,
+        TXM_MODULE_MPU_DEFAULT_RASR_6,
+        TXM_MODULE_MPU_DEFAULT_RBAR_7,
+        TXM_MODULE_MPU_DEFAULT_RASR_7,
+        TXM_MODULE_MPU_DEFAULT_RBAR_8,
+        TXM_MODULE_MPU_DEFAULT_RASR_8,
+        TXM_MODULE_MPU_DEFAULT_RBAR_9,
+        TXM_MODULE_MPU_DEFAULT_RASR_9,
+        TXM_MODULE_MPU_DEFAULT_RBAR_10,
+        TXM_MODULE_MPU_DEFAULT_RASR_10,
+        TXM_MODULE_MPU_DEFAULT_RBAR_11,
+        TXM_MODULE_MPU_DEFAULT_RASR_11,
+        TXM_MODULE_MPU_DEFAULT_RBAR_12,
+        TXM_MODULE_MPU_DEFAULT_RASR_12,
+        TXM_MODULE_MPU_DEFAULT_RBAR_13,
+        TXM_MODULE_MPU_DEFAULT_RASR_13,
+        TXM_MODULE_MPU_DEFAULT_RBAR_14,
+        TXM_MODULE_MPU_DEFAULT_RASR_14,
+        TXM_MODULE_MPU_DEFAULT_RBAR_15,
+        TXM_MODULE_MPU_DEFAULT_RASR_15
+    };
+#endif
 
 /**************************************************************************/
 /*                                                                        */
@@ -231,7 +268,7 @@ UINT    srd_bit_index;
 /*  FUNCTION                                               RELEASE        */
 /*                                                                        */
 /*    _txm_module_manager_mm_register_setup               Cortex-M3       */
-/*                                                           6.1.9        */
+/*                                                           6.1.12       */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -267,10 +304,10 @@ UINT    srd_bit_index;
 /*      9       Module shared memory region                               */
 /*      10      Module shared memory region                               */
 /*      11      Module shared memory region                               */
-/*      12      Unused region                                             */
-/*      13      Unused region                                             */
-/*      14      Unused region                                             */
-/*      15      Unused region                                             */
+/*      12      User-defined region                                       */
+/*      13      User-defined region                                       */
+/*      14      User-defined region                                       */
+/*      15      User-defined region                                       */
 /*                                                                        */
 /*                                                                        */
 /*  INPUT                                                                 */
@@ -294,6 +331,8 @@ UINT    srd_bit_index;
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  10-15-2021      Scott Larson            Initial Version 6.1.9         */
+/*  07-29-2022      Scott Larson            Enable user defined regions,  */
+/*                                            resulting in version 6.1.12 */
 /*                                                                        */
 /**************************************************************************/
 VOID  _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
@@ -456,18 +495,18 @@ UINT    i;
         /* Increment MPU table index.  */
         mpu_table_index++;
     }
-    
-    /* Setup MPU for the remaining regions.  */
-    while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES)
-    {
-        /* Build the base address register with address, MPU region, set Valid bit.  */
-        module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10;
-        
-        /* Increment MPU table index.  */
-        mpu_table_index++;
-    }
 
-#else
+    /* Setup user-defined regions (12-15).  */
+    module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address          = TXM_MODULE_MPU_USER_DEFINED_RBAR_12;
+    module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size   = TXM_MODULE_MPU_USER_DEFINED_RASR_12;
+    module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address          = TXM_MODULE_MPU_USER_DEFINED_RBAR_13;
+    module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size   = TXM_MODULE_MPU_USER_DEFINED_RASR_13;
+    module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address          = TXM_MODULE_MPU_USER_DEFINED_RBAR_14;
+    module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size   = TXM_MODULE_MPU_USER_DEFINED_RASR_14;
+    module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address          = TXM_MODULE_MPU_USER_DEFINED_RBAR_15;
+    module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size   = TXM_MODULE_MPU_USER_DEFINED_RASR_15;
+
+#else   /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */
 
 ULONG   code_address;
 ULONG   code_size;