diff options
| author | Tiejun Zhou <[email protected]> | 2022-10-26 23:41:13 +0000 |
|---|---|---|
| committer | Tiejun Zhou <[email protected]> | 2022-10-26 23:41:13 +0000 |
| commit | 3e8e85cdc1e51f9de577457377a4f9a4f6b9b82f (patch) | |
| tree | 861c0ab74e5dc5de7509b4b85f5e75dd74457117 /ports_module/cortex_m33 | |
| parent | b871c33620f9b58a83e92a33f4ca00025e850c7f (diff) | |
Release 6.2.0v6.2.0_rel
Diffstat (limited to 'ports_module/cortex_m33')
3 files changed, 51 insertions, 3 deletions
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S index 417d1404..e305ca17 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/AC6 */ -/* 6.1.12 */ +/* 6.2.0 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +75,8 @@ /* 07-29-2022 Scott Larson Removed the code path to skip */ /* MPU reloading, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Added low power support, */ +/* resulting in version 6.2.0 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -344,11 +346,25 @@ __tx_ts_wait: #endif LDR r1, [r2] // Pickup the next thread to execute pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + #ifdef TX_PORT_USE_BASEPRI MOV r4, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r4 diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S index af8be2ba..f8fb777b 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S @@ -29,7 +29,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/GNU */ -/* 6.1.12 */ +/* 6.2.0 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,6 +76,8 @@ /* 07-29-2022 Scott Larson Removed the code path to skip */ /* MPU reloading, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Added low power support, */ +/* resulting in version 6.2.0 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -345,11 +347,25 @@ __tx_ts_wait: #endif LDR r1, [r2] // Pickup the next thread to execute pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + #ifdef TX_PORT_USE_BASEPRI MOV r4, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r4 diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s index 3242fac2..5cf5ae16 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/IAR */ -/* 6.1.12 */ +/* 6.2.0 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -87,6 +87,8 @@ /* 07-29-2022 Scott Larson Removed the code path to skip */ /* MPU reloading, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Added low power support, */ +/* resulting in version 6.2.0 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -341,11 +343,25 @@ __tx_ts_wait: #endif LDR r1, [r2] // Pickup the next thread to execute pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + #ifdef TX_PORT_USE_BASEPRI MOV r4, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r4 |