Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

7 files changed, 75 insertions, 19 deletions

diff --git a/ports_module/cortex_m4/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex_m4/gnu/example_build/build_threadx_module_sample.bat
index f146d743..ec102df7 100644
--- a/ports_module/cortex_m4/gnu/example_build/build_threadx_module_sample.bat
+++ b/ports_module/cortex_m4/gnu/example_build/build_threadx_module_sample.bat
@@ -1,5 +1,5 @@
 arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base txm_module_preamble.s
 arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base gcc_setup.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c
-arm-none-eabi-ld -A cortex-m4 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map 
+arm-none-eabi-ld -A cortex-m4 -T sample_threadx_module.ld -pie --no-dynamic-linker txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map 
 
diff --git a/ports_module/cortex_m4/gnu/example_build/gcc_setup.s b/ports_module/cortex_m4/gnu/example_build/gcc_setup.s
index 4a729ffe..80ccb19b 100644
--- a/ports_module/cortex_m4/gnu/example_build/gcc_setup.s
+++ b/ports_module/cortex_m4/gnu/example_build/gcc_setup.s
@@ -1,4 +1,6 @@
 
+// Portions of this file were generated with AI assistance.
+
     .text
     .align 4
     .syntax unified
@@ -71,6 +73,46 @@ got_setup_done:
     mov     r2, #0
     bl      crt0_memory_set
 
+    /* Apply the R_ARM_RELATIVE relocations that target the module data area.  */
+
+    ldr     r3, =__FLASH_segment_start__ // crt0_memory_copy used r3 as a scratch register
+    ldr     r0, =__reldyn_load_start__
+    sub     r0,r0,r3
+    add     r0,r0,r5
+    ldr     r1, =__reldyn_end__
+    sub     r1,r1,r3
+    add     r1,r1,r5
+
+new_reldyn_setup:
+    cmp     r0, r1              // See if there are more relocation entries
+    beq     reldyn_setup_done   // No, done with the relocations
+    ldr     r6, [r0]            // Pickup the r_offset field
+    ldr     r7, [r0, #4]        // Pickup the r_info field
+    add     r0, r0, #8          // Move to the next entry
+    uxtb    r7, r7              // The relocation type is in the low byte
+    cmp     r7, #23             // Is it R_ARM_RELATIVE?
+    bne     new_reldyn_setup    // No, only R_ARM_RELATIVE is supported
+    cmp     r6, r4              // Does it target the code or the data area?
+    blt     new_reldyn_setup    // The code area is shared and read-only, skip it
+    sub     r6, r6, r4          // Compute offset of data area
+    add     r6, r6, r9          // Build the address of the word to relocate
+    ldr     r7, [r6]            // Pickup the link time address stored there
+    cmp     r7, #0              // Is it 0?
+    beq     new_reldyn_setup    // Yes, just skip the adjustment
+    cmp     r7, r4              // Is it in the code or data area?
+    blt     reldyn_flash_area   // If less than, it is a code address
+    sub     r7, r7, r4          // Compute offset of data area
+    add     r7, r7, r9          // Build address based on the loaded data address
+    b       reldyn_built        // Finished building address
+reldyn_flash_area:
+    sub     r7, r7, r3          // Compute offset of code area
+    add     r7, r7, r5          // Build address based on the loaded code address
+reldyn_built:
+    str     r7, [r6]            // Store the relocated address back
+    b       new_reldyn_setup    // Continue at the top of the loop
+reldyn_setup_done:
+
+
 
     /* Setup heap - not recommended for Threadx but here for compatibility reasons */
 
diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld
index 5fa4c680..f77bedda 100644
--- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld
+++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld
@@ -206,5 +206,13 @@ SECTIONS
 
   __data_size__ =  __heap_end__ - __RAM_segment_start__;
 
+  /* The dynamic linking metadata is not used by the module manager.  Discarding
+     it keeps it out of the binary image produced from this ELF file.  */
+
+  /DISCARD/ :
+  {
+    *(.dynamic)
+  }
+
 }
 
diff --git a/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S
index e922a5b5..24cb0fa7 100644
--- a/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S
+++ b/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -21,12 +22,10 @@
 /**************************************************************************/
 
 
-    .global     _tx_thread_system_stack_ptr
     .global     _tx_initialize_unused_memory
     .global     __RAM_segment_used_end__
     .global     _tx_timer_interrupt
     .global     __main
-    .global     _vectors
     .global     __tx_NMIHandler                     // NMI
     .global     __tx_BadHandler                     // HardFault
     .global     __tx_DBGHandler                     // Monitor
@@ -92,12 +91,6 @@ _tx_initialize_low_level:
     ADD     r1, r1, #4                              //
     STR     r1, [r0]                                // Setup first unused memory pointer
 
-    /* Setup Vector Table Offset Register.  */
-
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    LDR     r1, =_vectors                           // Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        // Set vector table address
-
     /* Enable the cycle count register.  */
 
 //    LDR     r0, =0xE0001000                         // Build address of DWT register
@@ -105,16 +98,12 @@ _tx_initialize_low_level:
 //    ORR     r1, r1, #1                              // Set the CYCCNTENA bit
 //    STR     r1, [r0]                                // Enable the cycle count register
 
-    /* Set system stack pointer from vector value.  */
-
-    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
-    LDR     r1, =_vectors                           // Pickup address of vector table
-    LDR     r1, [r1]                                // Pickup reset stack pointer
-    STR     r1, [r0]                                // Save system stack pointer
-
     /* Configure SysTick.  */
 
     MOV     r0, #0xE000E000                         // Build address of NVIC registers
+    MOV     r1, #0                                  // Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         // Reset SysTick Control
+    STR     r1, [r0, #0x18]                         // Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
     MOV     r1, #0x7                                // Build SysTick Control Enable Value
diff --git a/ports_module/cortex_m4/gnu/inc/tx_port.h b/ports_module/cortex_m4/gnu/inc/tx_port.h
index 14dbe962..ab64b09b 100644
--- a/ports_module/cortex_m4/gnu/inc/tx_port.h
+++ b/ports_module/cortex_m4/gnu/inc/tx_port.h
@@ -711,7 +711,7 @@ void    tx_thread_fpu_disable(void);
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.2.202603 *";
 #else
 #ifdef TX_MISRA_ENABLE
 extern  CHAR                    _tx_version_id[100];
diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S
index a5a80868..a4c11abc 100644
--- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S
+++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -215,7 +216,7 @@ UsageFault_Handler:
     STR     r1, [r0]                                // Store ICSR
     DSB                                             // Wait for memory access to complete
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -250,7 +251,7 @@ __tx_ts_handler:
     BL      _tx_execution_thread_exit               // Call the thread exit function
     POP     {r0, lr}                                // Recover LR
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -330,9 +331,19 @@ __tx_ts_wait:
 #endif
 
 #ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+    CPSID   i                                       // Mask every interrupt with PRIMASK, which WFI ignores
+    MOV     r1, #0                                  // Clear BASEPRI so that an interrupt masked by it
+    MSR     BASEPRI, r1                             //   is still able to wake the processor
+#endif
     DSB                                             // Ensure no outstanding memory transactions
     WFI                                             // Wait for interrupt
     ISB                                             // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+    LDR     r1, =TX_PORT_BASEPRI                    // Restore the BASEPRI mask
+    MSR     BASEPRI, r1
+    CPSIE   i                                       // Clear PRIMASK; a pending interrupt is taken here
+#endif
 #endif
 
 #ifdef TX_LOW_POWER
diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S
index 8c4a09fd..09349318 100644
--- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S
+++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller