Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

6 files changed, 29 insertions, 32 deletions

diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S
index 2837a142..3ec0d153 100644
--- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S
+++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -21,7 +22,6 @@
 /**************************************************************************/
 
 
-    .global     _tx_thread_system_stack_ptr
     .global     _tx_initialize_unused_memory
     .global     _tx_timer_interrupt
     .global     __main
@@ -93,19 +93,6 @@ _tx_initialize_low_level:
     ADD     r1, r1, #4                              //
     STR     r1, [r0]                                // Setup first unused memory pointer
 
-    /* Setup Vector Table Offset Register.  */
-
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    LDR     r1, =vector_table                       // Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        // Set vector table address
-
-    /* Set system stack pointer from vector value.  */
-
-    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
-    LDR     r1, =vector_table                       // Pickup address of vector table
-    LDR     r1, [r1]                                // Pickup reset stack pointer
-    STR     r1, [r0]                                // Save system stack pointer
-
     /* Enable the cycle count register.  */
 
     LDR     r0, =0xE0001000                         // Build address of DWT register
@@ -116,6 +103,9 @@ _tx_initialize_low_level:
     /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference.  */
 
     MOV     r0, #0xE000E000                         // Build address of NVIC registers
+    MOV     r1, #0                                  // Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         // Reset SysTick Control
+    STR     r1, [r0, #0x18]                         // Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
     MOV     r1, #0x7                                // Build SysTick Control Enable Value
diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
index 7b783402..187beb06 100644
--- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
+++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
@@ -155,7 +155,7 @@
     <booleanAttribute key="VFS_ENABLED" value="true"/>
     <stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
     <stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
-    <stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;112&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;112&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;115&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;115&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;118&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;118&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;124&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;124&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;89&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;89&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;97&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;97&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/common_modules/module_manager/src/txm_module_manager_in_place_load.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\common_modules\module_manager\src\txm_module_manager_in_place_load.c&quot; line=&quot;119&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/common_modules/module_manager/src/txm_module_manager_in_place_load.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\common_modules\module_manager\src\txm_module_manager_in_place_load.c&quot; line=&quot;119&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;103&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;103&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/common_modules/module_manager/src/txm_module_manager_start.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\common_modules\module_manager\src\txm_module_manager_start.c&quot; line=&quot;225&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/common_modules/module_manager/src/txm_module_manager_start.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\common_modules\module_manager\src\txm_module_manager_start.c&quot; line=&quot;225&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;106&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;106&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;109&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;109&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x000315E8&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_txm_update/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_txm_update\ports_module\cortex-m7\ac6\example_build\sample_threadx_module\sample_threadx_module.c&quot; line=&quot;247&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x000315E8&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_txm_update/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_txm_update\ports_module\cortex-m7\ac6\example_build\sample_threadx_module\sample_threadx_module.c&quot; line=&quot;247&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&lt;/breakpoints&gt;&#10;"/>
+    <stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#10;&lt;/breakpoints&gt;&#10;"/>
     <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses">
         <listEntry value="&lt;Next Instruction&gt;"/>
         <listEntry value=""/>
diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S
index 2df350e5..9eb0bdf5 100644
--- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S
+++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -21,7 +22,6 @@
 /**************************************************************************/
 
 
-    .global     _tx_thread_system_stack_ptr
     .global     _tx_initialize_unused_memory
     .global     _tx_timer_interrupt
     .global     __main
@@ -93,12 +93,6 @@ _tx_initialize_low_level:
     ADD     r1, r1, #4                              //
     STR     r1, [r0]                                // Setup first unused memory pointer
 
-    /* Setup Vector Table Offset Register.  */
-
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    LDR     r1, =vector_table                       // Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        // Set vector table address
-
     /* Enable the cycle count register.  */
 
 //    LDR     r0, =0xE0001000                         // Build address of DWT register
@@ -106,16 +100,12 @@ _tx_initialize_low_level:
 //    ORR     r1, r1, #1                              // Set the CYCCNTENA bit
 //    STR     r1, [r0]                                // Enable the cycle count register
 
-    /* Set system stack pointer from vector value.  */
-
-    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
-    LDR     r1, =vector_table                       // Pickup address of vector table
-    LDR     r1, [r1]                                // Pickup reset stack pointer
-    STR     r1, [r0]                                // Save system stack pointer
-
     /* Configure SysTick.  */
 
     MOV     r0, #0xE000E000                         // Build address of NVIC registers
+    MOV     r1, #0                                  // Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         // Reset SysTick Control
+    STR     r1, [r0, #0x18]                         // Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
     MOV     r1, #0x7                                // Build SysTick Control Enable Value
diff --git a/ports_module/cortex_m7/ac6/inc/tx_port.h b/ports_module/cortex_m7/ac6/inc/tx_port.h
index 70b6c5a9..9a009596 100644
--- a/ports_module/cortex_m7/ac6/inc/tx_port.h
+++ b/ports_module/cortex_m7/ac6/inc/tx_port.h
@@ -711,7 +711,7 @@ void    tx_thread_fpu_disable(void);
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.2.202603 *";
 #else
 #ifdef TX_MISRA_ENABLE
 extern  CHAR                    _tx_version_id[100];
diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S
index a3126bc7..958a739d 100644
--- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S
+++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -217,7 +218,7 @@ UsageFault_Handler:
     STR     r1, [r0]                                // Store ICSR
     DSB                                             // Wait for memory access to complete
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -252,7 +253,7 @@ __tx_ts_handler:
     BL      _tx_execution_thread_exit               // Call the thread exit function
     POP     {r0, lr}                                // Recover LR
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -332,9 +333,19 @@ __tx_ts_wait:
 #endif
 
 #ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+    CPSID   i                                       // Mask every interrupt with PRIMASK, which WFI ignores
+    MOV     r1, #0                                  // Clear BASEPRI so that an interrupt masked by it
+    MSR     BASEPRI, r1                             //   is still able to wake the processor
+#endif
     DSB                                             // Ensure no outstanding memory transactions
     WFI                                             // Wait for interrupt
     ISB                                             // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+    LDR     r1, =TX_PORT_BASEPRI                    // Restore the BASEPRI mask
+    MSR     BASEPRI, r1
+    CPSIE   i                                       // Clear PRIMASK; a pending interrupt is taken here
+#endif
 #endif
 
 #ifdef TX_LOW_POWER
diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S
index 831c00e4..4071b1a1 100644
--- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S
+++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller