Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel

Merged changes ahead of the v6.5.2.202603 release

6 files changed, 43 insertions, 34 deletions

diff --git a/ports_module/cortex_m7/iar/example_build/tx.ewp b/ports_module/cortex_m7/iar/example_build/tx.ewp
index 7ff6209d..09ad5b2e 100644
--- a/ports_module/cortex_m7/iar/example_build/tx.ewp
+++ b/ports_module/cortex_m7/iar/example_build/tx.ewp
@@ -1054,7 +1054,7 @@
                 </option>
                 <option>
                     <name>IarchiveOutput</name>
-                    <state>C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\iar\example_build\Debug\Exe\tx.a</state>
+                    <state>###Unitialized###</state>
                 </option>
             </data>
         </settings>
diff --git a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s
index 2df2d19f..8c599aef 100644
--- a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s
+++ b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s
@@ -8,6 +8,7 @@
  *
  * SPDX-License-Identifier: MIT
  **************************************************************************/
+// Portions of this file were generated with AI assistance.
 
 
 /**************************************************************************/
@@ -21,10 +22,8 @@
 /**************************************************************************/
 
 
-    EXTERN  _tx_thread_system_stack_ptr
     EXTERN  _tx_initialize_unused_memory
     EXTERN  _tx_timer_interrupt
-    EXTERN  __vector_table
     EXTERN  _tx_execution_isr_enter
     EXTERN  _tx_execution_isr_exit
 
@@ -87,12 +86,6 @@ _tx_initialize_low_level:
     LDR     r1, =__tx_free_memory_start             // Build first free address
     STR     r1, [r0]                                // Setup first unused memory pointer
 
-    /* Setup Vector Table Offset Register.  */
-
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    LDR     r1, =__vector_table                     // Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        // Set vector table address
-
     /* Enable the cycle count register.  */
 
 //    LDR     r0, =0xE0001000                         // Build address of DWT register
@@ -100,16 +93,12 @@ _tx_initialize_low_level:
 //    ORR     r1, r1, #1                              // Set the CYCCNTENA bit
 //    STR     r1, [r0]                                // Enable the cycle count register
 
-    /* Set system stack pointer from vector value.  */
-
-    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
-    LDR     r1, =__vector_table                     // Pickup address of vector table
-    LDR     r1, [r1]                                // Pickup reset stack pointer
-    STR     r1, [r0]                                // Save system stack pointer
-
     /* Configure SysTick.  */
 
     MOV     r0, #0xE000E000                         // Build address of NVIC registers
+    MOV     r1, #0                                  // Build value for SysTick reset
+    STR     r1, [r0, #0x10]                         // Reset SysTick Control
+    STR     r1, [r0, #0x18]                         // Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
     MOV     r1, #0x7                                // Build SysTick Control Enable Value
diff --git a/ports_module/cortex_m7/iar/inc/tx_port.h b/ports_module/cortex_m7/iar/inc/tx_port.h
index 70b6c5a9..9a009596 100644
--- a/ports_module/cortex_m7/iar/inc/tx_port.h
+++ b/ports_module/cortex_m7/iar/inc/tx_port.h
@@ -711,7 +711,7 @@ void    tx_thread_fpu_disable(void);
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] =
-                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602a *";
+                                    "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.2.202603 *";
 #else
 #ifdef TX_MISRA_ENABLE
 extern  CHAR                    _tx_version_id[100];
diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c
index 238b485e..ab6c209c 100644
--- a/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c
+++ b/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c
@@ -9,6 +9,7 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
 
 /**************************************************************************/
 /**************************************************************************/
@@ -270,7 +271,7 @@ TX_MUTEX    *mutex_ptr;
         mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
 
         /* Check for wrap-around on the next free mutex.  */
-        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK)
         {
 
             /* Yes, set the free index back to 0.  */
@@ -287,7 +288,7 @@ TX_MUTEX    *mutex_ptr;
     }
 
     /* Determine if a free mutex was found.   */
-    if (i >= _MAX_LOCK)
+    if (i >= _MAX_FLOCK)
     {
 
         /* Error!  No more free mutexes!  */
@@ -678,7 +679,7 @@ TX_MUTEX    *mutex_ptr;
         mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
 
         /* Check for wrap-around on the next free mutex.  */
-        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK)
         {
 
             /* Yes, set the free index back to 0.  */
@@ -695,7 +696,7 @@ TX_MUTEX    *mutex_ptr;
     }
 
     /* Determine if a free mutex was found.   */
-    if (i >= _MAX_LOCK)
+    if (i >= _MAX_FLOCK)
     {
 
         /* Error!  No more free mutexes!  */
diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s
index d38c8df7..5e2a95ad 100644
--- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s
+++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Portions of this file were generated with AI assistance.
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -207,7 +209,7 @@ UsageFault_Handler:
     STR     r1, [r0]                                // Store ICSR
     DSB                                             // Wait for memory access to complete
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -239,7 +241,7 @@ __tx_ts_handler:
     BL      _tx_execution_thread_exit               // Call the thread exit function
     POP     {r0, lr}                                // Recover LR
 #ifdef TX_PORT_USE_BASEPRI
-    MOV     r0, 0                                   // Disable BASEPRI masking (enable interrupts)
+    MOV     r0, #0                                  // Disable BASEPRI masking (enable interrupts)
     MSR     BASEPRI, r0
 #else
     CPSIE   i                                       // Enable interrupts
@@ -319,9 +321,19 @@ __tx_ts_wait:
 #endif
 
 #ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+    CPSID   i                                       // Mask every interrupt with PRIMASK, which WFI ignores
+    MOV     r1, #0                                  // Clear BASEPRI so that an interrupt masked by it
+    MSR     BASEPRI, r1                             //   is still able to wake the processor
+#endif
     DSB                                             // Ensure no outstanding memory transactions
     WFI                                             // Wait for interrupt
     ISB                                             // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+    LDR     r1, =TX_PORT_BASEPRI                    // Restore the BASEPRI mask
+    MSR     BASEPRI, r1
+    CPSIE   i                                       // Clear PRIMASK; a pending interrupt is taken here
+#endif
 #endif
 
 #ifdef TX_LOW_POWER
diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s
index 0cef80c6..ab1f05ba 100644
--- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s
+++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s
@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Portions of this file were generated with AI assistance.
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -78,10 +83,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller