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authorTiejun Zhou <[email protected]>2023-03-08 08:26:22 +0000
committerTiejun Zhou <[email protected]>2023-03-08 08:26:22 +0000
commit2aa19f3de0b6cf09bb9dca78c8a53fe337b8f0f7 (patch)
tree8ec91a64e0831e3100a6ad9a5dec41d9fd7fc74f /ports_smp/cortex_a76ae_smp/gnu
parent745395d6a2f931c85c4428425db21eb7d03b4324 (diff)
Release 6.2.1 on 08 Mar 2023. Expand to see details.v6.2.1_rel
cee19603d Include tx_user.h conditionally. e40e08007 Update owners d69641273 Update release date and version 394aee52f Add tx_user.h to GNU port assembly files 5cca2ddd0 RISC-V 64 bit port for Microchip e0f2c373c Link Winmm.lib that required by the high-resolution timer. 6af472a68 Update Win32 port with high resolution timer. aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler 19091a262 Add .section .preamble to m3 m4 m7 module ports ced60e1b7 Add missing parenthesis in ports assembly file 309dc77ca Modules Cortex-A7 IAR new port c752a4063 Modules Cortex-A7 GNU new port dc224b90f Fix race condition in tx_thread_wait_abort and update regression test 6e261f5b7 create threadx cmsis-pack
Diffstat (limited to 'ports_smp/cortex_a76ae_smp/gnu')
-rw-r--r--ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h2
-rw-r--r--ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S9
2 files changed, 7 insertions, 4 deletions
diff --git a/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h
index fcac1485..019db6eb 100644
--- a/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h
+++ b/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h
@@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
- "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *";
+ "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *";
#else
extern CHAR _tx_version_id[];
#endif
diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S
index 35a8fc96..8246e24f 100644
--- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S
+++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S
@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule ARMv8-A-SMP */
-/* 6.1.10 */
+/* 6.2.1 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,8 +63,11 @@
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
-/* added ARMv8.2-A support, */
+/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
+/* 03-08-2023 Cindy Deng Updated comment(s), */
+/* added memory barrier, */
+/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -165,7 +168,7 @@ _tx_thread_ready_for_execution:
LDR x2, =_tx_thread_current_ptr // Pickup address of current thread
STR x0, [x2, x20, LSL #3] // Setup current thread pointer
-
+ DMB ISH
LDR x1, [x1, x20, LSL #3] // Reload the execute pointer
CMP w0, w1 // Did it change?
BEQ _execute_pointer_did_not_change // If not, skip handling