Added a QEMU module execution harness for the Cortex-M3 and M4 ports (#821)dev

No Cortex-M module port ran in CI. gcc_check compiles each port's module manager
sources and links nothing that loads a module, and the host tests under
test/tx/module_manager compile a few portable sources against stubs. A module's
start-up, its kernel calls through the supervisor call, the MPU programming on context
switches and the fault path that terminates a misbehaving module were exercised only
on the Cortex-R52 FVP.

test/tx/cmake/module_qemu is a stand-alone CMake project, like test/tx/cmake/riscv, that
builds the kernel and Module Manager with a module port's headers, builds test modules
position-independent with the port's module linker script, embeds their raw images in
manager images, and registers each image with CTest. A Python runner starts it on
QEMU's MPS2 board for the core, mps2-an385 for cortex_m3 and mps2-an386 for cortex_m4
built for its FPU with the hard-float ABI, and judges the result line the image prints
over semihosting and the exit status it sets. Three images per port: a protected module
loaded, started, exercising queues, semaphores, a worker thread and the timer, stopped
and unloaded twice with its memory returned; the same module faulting on a read of
kernel memory, reported to the fault notification with its module, thread and address
and terminated, then stopped and unloaded; and the module built privileged and
unprotected, whose identical read succeeds. The fault image is also the check that
QEMU's MPU enforces at all. The new module_qemu workflow runs both ports on changes to
common/, common_modules/, the two module ports and the harness, installing QEMU from
the Ubuntu archive through the bounded apt helpers in scripts/tx_ci_common.sh.

Both ports pass 3/3 on QEMU 8.2.2 with Arm GNU 14.3.rel1, using the workflow's commands,
with zero compiler warnings; configure, build and run take 9 seconds for both. The AI
disclosure check passes. The workflow itself has not run on GitHub yet.

Assisted-by: Claude Code (Opus 5.5) <[email protected]>

1 files changed, 87 insertions, 0 deletions

diff --git a/test/tx/cmake/module_qemu/src/tx_initialize_low_level.S b/test/tx/cmake/module_qemu/src/tx_initialize_low_level.S
new file mode 100644
index 00000000..2e6ecfdf
--- /dev/null
+++ b/test/tx/cmake/module_qemu/src/tx_initialize_low_level.S
@@ -0,0 +1,87 @@
+/***************************************************************************
+ * Copyright (c) 2026 Eclipse ThreadX contributors
+ *
+ * This program and the accompanying materials are made available under the
+ * terms of the MIT License which is available at
+ * https://opensource.org/licenses/MIT.
+ *
+ * AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5.5).
+ * The AI-generated portions may be considered public domain (CC0-1.0)
+ * and not subject to the project's licence. The human contributor has
+ * reviewed and verified that the code is correct.
+ *
+ * SPDX-License-Identifier: MIT and CC0-1.0
+ **************************************************************************/
+
+@ Low-level initialisation for the module execution harness on QEMU's MPS2
+@ AN385 (Cortex-M3) and AN386 (Cortex-M4) boards, both clocked at 25 MHz.
+
+    .syntax unified
+    .thumb
+
+    .global _tx_initialize_unused_memory
+    .global _tx_timer_interrupt
+    .global __RAM_segment_used_end__
+
+SYSTEM_CLOCK    =   25000000
+SYSTICK_CYCLES  =   ((SYSTEM_CLOCK / 100) - 1)
+
+    .text
+    .align  2
+
+@ VOID _tx_initialize_low_level(VOID)
+
+    .global _tx_initialize_low_level
+    .thumb_func
+_tx_initialize_low_level:
+
+    CPSID   i                               @ Interrupts stay off until the scheduler starts
+
+    @ First free memory follows everything the image uses.
+
+    LDR     r0, =_tx_initialize_unused_memory
+    LDR     r1, =__RAM_segment_used_end__
+    ADD     r1, r1, #4
+    STR     r1, [r0]
+
+    @ Vector table base, in case the board boots with another.
+
+    LDR     r0, =0xE000ED08                 @ VTOR
+    LDR     r1, =_vectors
+    STR     r1, [r0]
+
+    @ SysTick at 100 Hz.
+
+    LDR     r0, =0xE000E000
+    MOV     r1, #0
+    STR     r1, [r0, #0x10]                 @ SysTick control: off
+    STR     r1, [r0, #0x18]                 @ SysTick current value
+    LDR     r1, =SYSTICK_CYCLES
+    STR     r1, [r0, #0x14]                 @ SysTick reload
+    MOV     r1, #0x7
+    STR     r1, [r0, #0x10]                 @ SysTick control: on, interrupt, core clock
+
+    @ Handler priorities: the faults highest, SVCall and PendSV lowest, as the
+    @ module port requires.
+
+    LDR     r1, =0x00000000                 @ Reserved, UsageFault, BusFault, MemManage
+    STR     r1, [r0, #0xD18]
+    LDR     r1, =0xFF000000                 @ SVCall, reserved x3
+    STR     r1, [r0, #0xD1C]
+    LDR     r1, =0x40FF0000                 @ SysTick, PendSV, reserved, debug monitor
+    STR     r1, [r0, #0xD20]
+
+    BX      lr
+
+@ SysTick: drive the ThreadX timer.
+
+    .global __tx_SysTickHandler
+    .global SysTick_Handler
+    .thumb_func
+__tx_SysTickHandler:
+    .thumb_func
+SysTick_Handler:
+    PUSH    {r0, lr}
+    BL      _tx_timer_interrupt
+    POP     {r0, lr}
+    BX      lr