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-rw-r--r--ports/cortex_m0/ac6/inc/tx_port.h2
-rw-r--r--ports/cortex_m0/ac6/src/tx_thread_system_return.S3
-rw-r--r--ports/cortex_m0/gnu/example_build/cortexm0_crt0.S32
-rw-r--r--ports/cortex_m0/gnu/example_build/sample_threadx.ld30
-rw-r--r--ports/cortex_m0/iar/inc/tx_port.h1
-rw-r--r--ports/cortex_m0/iar/src/tx_thread_system_return.s1
-rwxr-xr-xscripts/check_clang.sh6
7 files changed, 56 insertions, 19 deletions
diff --git a/ports/cortex_m0/ac6/inc/tx_port.h b/ports/cortex_m0/ac6/inc/tx_port.h
index 006c7e48..214ca8e8 100644
--- a/ports/cortex_m0/ac6/inc/tx_port.h
+++ b/ports/cortex_m0/ac6/inc/tx_port.h
@@ -322,11 +322,13 @@ unsigned int interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+ __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_primask_value();
__enable_interrupts();
__restore_interrupts(interrupt_save);
+ __asm__ volatile ("isb 0xF " : : : "memory");
}
}
diff --git a/ports/cortex_m0/ac6/src/tx_thread_system_return.S b/ports/cortex_m0/ac6/src/tx_thread_system_return.S
index fc62c0c6..bd7a23f3 100644
--- a/ports/cortex_m0/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m0/ac6/src/tx_thread_system_return.S
@@ -72,12 +72,15 @@ _tx_thread_system_return:
LDR r0, =0x10000000 @ Load PENDSVSET bit
LDR r1, =0xE000ED04 @ Load NVIC base
STR r0, [r1] @ Set PENDSVBIT in ICSR
+ DSB #0xF @ Ensure memory access is complete
+ ISB #0xF @ Flush pipeline
MRS r0, IPSR @ Pickup IPSR
CMP r0, #0 @ Is it a thread returning?
BNE _isr_context @ If ISR, skip interrupt enable
MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK
CPSIE i @ Enable interrupts
MSR PRIMASK, r1 @ Restore original interrupt posture
+ ISB #0xF @ Flush pipeline
_isr_context:
BX lr @ Return to caller
@/* } */
diff --git a/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S
index 070871a3..8138ef97 100644
--- a/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S
+++ b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S
@@ -4,6 +4,12 @@
.section .init, "ax"
.code 16
+ /* Unified assembler syntax. Without it GNU as falls back to the legacy
+ divided syntax, in which a plain add or sub sets the flags implicitly.
+ LLVM implements only unified syntax, where ARMv6-M has no
+ flag-preserving encoding, so the S-forms below are required. Declaring
+ the mode makes both assemblers agree. */
+ .syntax unified
.align 2
.thumb_func
@@ -43,16 +49,16 @@ _start:
/* Zero bss. */
ldr r0, =__bss_start__
ldr r1, =__bss_end__
- mov r2, #0
+ movs r2, #0
bl crt0_memory_set
/* Setup heap - not recommended for Threadx but here for compatibility reasons */
ldr r0, = __heap_start__
ldr r1, = __heap_end__
- sub r1, r1, r0
- mov r2, #0
+ subs r1, r1, r0
+ movs r2, #0
str r2, [r0]
- add r0, r0, #4
+ adds r0, r0, #4
str r1, [r0]
/* constructors in case of using C++ */
@@ -62,7 +68,7 @@ crt0_ctor_loop:
cmp r0, r1
beq crt0_ctor_end
ldr r2, [r0]
- add r0, #4
+ adds r0, #4
push {r0-r1}
blx r2
pop {r0-r1}
@@ -70,14 +76,14 @@ crt0_ctor_loop:
crt0_ctor_end:
/* Setup call frame for main() */
- mov r0, #0
+ movs r0, #0
mov lr, r0
mov r12, sp
start:
/* Jump to main() */
- mov r0, #0
- mov r1, #0
+ movs r0, #0
+ movs r1, #0
ldr r2, =main
blx r2
/* when main returns, loop forever. */
@@ -91,14 +97,14 @@ crt0_exit_loop:
crt0_memory_copy:
cmp r0, r1
beq memory_copy_done
- sub r2, r2, r1
+ subs r2, r2, r1
beq memory_copy_done
memory_copy_loop:
ldrb r3, [r0]
- add r0, r0, #1
+ adds r0, r0, #1
strb r3, [r1]
- add r1, r1, #1
- sub r2, r2, #1
+ adds r1, r1, #1
+ subs r2, r2, #1
bne memory_copy_loop
memory_copy_done:
bx lr
@@ -107,7 +113,7 @@ crt0_memory_set:
cmp r0, r1
beq memory_set_done
strb r2, [r0]
- add r0, r0, #1
+ adds r0, r0, #1
b crt0_memory_set
memory_set_done:
bx lr
diff --git a/ports/cortex_m0/gnu/example_build/sample_threadx.ld b/ports/cortex_m0/gnu/example_build/sample_threadx.ld
index 3f19c29e..d2da5859 100644
--- a/ports/cortex_m0/gnu/example_build/sample_threadx.ld
+++ b/ports/cortex_m0/gnu/example_build/sample_threadx.ld
@@ -17,6 +17,8 @@ SECTIONS
.text :
{
+ __text_start__ = .;
+
*(.text*)
KEEP(*(.init))
@@ -26,6 +28,7 @@ SECTIONS
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ __ctors_load_start__ = .;
__ctors_start__ = ALIGN(4);
*(SORT(.ctors.*))
*(.ctors)
@@ -35,16 +38,41 @@ SECTIONS
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ __dtors_load_start__ = .;
__dtors_start__ = ALIGN(4);
*(SORT(.dtors.*))
*(.dtors)
__dtors_end__ = ALIGN(4);
+ KEEP(*(.eh_frame*))
+
+ __text_end__ = ALIGN(4);
+ } > FLASH
+
+ __text_load_start__ = LOADADDR(.text);
+
+ .rodata :
+ {
+ __rodata_start__ = .;
+
*(.rodata*)
- KEEP(*(.eh_frame*))
+ __rodata_end__ = ALIGN(4);
} > FLASH
+ __rodata_load_start__ = LOADADDR(.rodata);
+
+ /* Fast section: for time-critical code/data to be copied from FLASH to RAM at startup.
+ No .fast content in this sample; symbols defined so crt0 startup copy is a no-op. */
+ .fast (NOLOAD) :
+ {
+ __fast_start__ = .;
+ *(.fast*)
+ __fast_end__ = .;
+ } > RAM
+
+ __fast_load_start__ = __fast_start__;
+
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
diff --git a/ports/cortex_m0/iar/inc/tx_port.h b/ports/cortex_m0/iar/inc/tx_port.h
index 2dcb7b4e..035009e7 100644
--- a/ports/cortex_m0/iar/inc/tx_port.h
+++ b/ports/cortex_m0/iar/inc/tx_port.h
@@ -319,6 +319,7 @@ __istate_t interrupt_save;
interrupt_save = __get_interrupt_state();
__enable_interrupt();
__set_interrupt_state(interrupt_save);
+ __asm__ volatile ("isb 0xF " : : : "memory");
}
}
diff --git a/ports/cortex_m0/iar/src/tx_thread_system_return.s b/ports/cortex_m0/iar/src/tx_thread_system_return.s
index 9426a137..ab92a8c7 100644
--- a/ports/cortex_m0/iar/src/tx_thread_system_return.s
+++ b/ports/cortex_m0/iar/src/tx_thread_system_return.s
@@ -79,6 +79,7 @@ _tx_thread_system_return:
MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
+ ISB SY ; Flush pipeline
_isr_context:
BX lr ; Return to caller
;}
diff --git a/scripts/check_clang.sh b/scripts/check_clang.sh
index 5bf902e3..512b0385 100755
--- a/scripts/check_clang.sh
+++ b/scripts/check_clang.sh
@@ -148,10 +148,6 @@ C_CORES="cortex_m0 cortex_m4 cortex_m23 cortex_m33 cortex_m55 cortex_a7 cortex_a
# explicitly rather than silently skipped, so the gaps stay visible.
#
# These fail with the GNU toolchain too, so they are not LLVM problems:
-# cortex_m0 cortexm0_crt0.S references __text_load_start__,
-# __text_start__ and __text_end__, which its linker
-# script never defines. The Cortex-M4 script defines the
-# equivalents, so this is a gap in that one example.
# arm9 arm11 need newlib multilib variants for those CPUs, which are
# cortex_r4 cortex_r5 not present in every GNU toolchain packaging.
#
@@ -160,7 +156,7 @@ C_CORES="cortex_m0 cortex_m4 cortex_m23 cortex_m33 cortex_m55 cortex_a7 cortex_a
# own crt0 is linked, and it needs picolibc's
# __data_start, __data_source, __data_size and __bss_size,
# which the example's linker script does not define.
-EXAMPLES_EXPECTED_TO_FAIL="arm9 arm11 cortex_m0 cortex_r4 cortex_r5 cortex_a12 cortex_a15 cortex_a17"
+EXAMPLES_EXPECTED_TO_FAIL="arm9 arm11 cortex_r4 cortex_r5 cortex_a12 cortex_a15 cortex_a17"
failures=0
skipped=""
generated by cgit v1.3.1 (git 2.54.0) at 2026-11-09 05:16:33 +0000