diff options
Diffstat (limited to 'ports/arm11')
65 files changed, 2772 insertions, 3149 deletions
diff --git a/ports/arm11/ac5/example_build/sample_threadx.c b/ports/arm11/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/arm11/ac5/example_build/sample_threadx.c +++ b/ports/arm11/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm11/ac5/example_build/tx_initialize_low_level.s b/ports/arm11/ac5/example_build/tx_initialize_low_level.s index 541ddb1e..3badfc20 100644 --- a/ports/arm11/ac5/example_build/tx_initialize_low_level.s +++ b/ports/arm11/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -41,7 +41,7 @@ SYS_STACK_SIZE EQU 1024 ; SYS stack size (used for neste IRQ_STACK_SIZE EQU 1024 ; IRQ stack size ; ; -;/* ARM11 ARMulator Timer and Interrupt controller information. This depends on +;/* ARM11 ARMulator Timer and Interrupt controller information. This depends on ; the ARMulator's Interrupt Controller and Timer being enabled in the default.ami. ; In addition, the addresses must match those specified in the peripherals.ami file. ; Please refer to section 2.10 and 4.16 of the Debug Target Guide, version 1.2. */ @@ -50,7 +50,7 @@ IRQStatus EQU 0x0a000000 ; IRQ Status Register IRQRawStatus EQU 0x0a000004 ; IRQ Raw Status Register IRQEnable EQU 0x0a000008 ; IRQ Enable Set Register IRQEnableClear EQU 0x0a00000C ; IRQ Enable Clear Register -IRQSoft EQU 0x0a000010 ; IRQ Soft +IRQSoft EQU 0x0a000010 ; IRQ Soft FIQStatus EQU 0x0a000100 ; FIQ Status Register FIQRawStatus EQU 0x0a000104 ; FIQ Raw Status Register FIQEnable EQU 0x0a000108 ; FIQ Enable Set Register @@ -113,45 +113,39 @@ __vectors ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -202,7 +196,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -238,7 +232,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -290,7 +284,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -298,34 +292,34 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; ; /* Check for Timer1 interrupts on the ARMulator. */ LDR r1,=IRQStatus ; Pickup address of IRQStatus register - LDR r2, [r1] ; Read IRQStatus + LDR r2, [r1] ; Read IRQStatus LDR r0,=TIMER1_BIT ; Pickup Timer1 interrupt present bit AND r2, r2, r0 ; Is this a timer interrupt? - CMP r2, r0 ; + CMP r2, r0 ; BNE _tx_not_timer_interrupt ; If 0, not a timer interrupt LDR r1,=Timer1Clear ; Build address of Timer1 clear register - MOV r0,#0 ; + MOV r0,#0 ; STR r0, [r1] ; Clear timer 0 interrupt BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -335,7 +329,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -351,28 +345,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -381,7 +375,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -403,11 +397,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/arm11/ac5/inc/tx_port.h b/ports/arm11/ac5/inc/tx_port.h index eb74538b..b1bf6e36 100644 --- a/ports/arm11/ac5/inc/tx_port.h +++ b/ports/arm11/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h ARM11/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM11/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include <string.h> -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,21 +238,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -280,7 +272,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -289,7 +281,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -318,8 +310,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARM11/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/ac5/readme_threadx.txt b/ports/arm11/ac5/readme_threadx.txt index 82a9dfa2..a89d79b5 100644 --- a/ports/arm11/ac5/readme_threadx.txt +++ b/ports/arm11/ac5/readme_threadx.txt @@ -6,15 +6,15 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the ARM -AC5 development environment. At this point you may run the build_threadx.bat -batch file. This will build the ThreadX run-time environment in the -"example_build" directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -24,39 +24,39 @@ Since there is no ARM11 FVP, there are no instructions here for running the demonstration; users are expected to run the demonstration on their platform of choice. -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the user's platform of choice. 3. System Initialization -The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label +The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label __main. This is defined within the AC5 compiler's startup code. In addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler Switch Meaning @@ -72,10 +72,10 @@ Linker Switch Meaning -o demo.axf Specifies demo output file name --elf Specifies elf output file format --ro Specifies that Read-Only memory starts at address 0 - --first tx_initialize_low_level.o(Init) + --first tx_initialize_low_level.o(Init) Specifies that the first area loaded is Init --remove Remove unused areas - --list Specifies map file name + --list Specifies map file name --symbols Specifies symbols for map file --map Creates a map file @@ -86,161 +86,161 @@ Application Defines ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -258,39 +258,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A5 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -301,12 +301,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -314,7 +314,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -327,7 +327,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -337,12 +337,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -359,22 +359,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -382,10 +382,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -398,12 +398,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -412,7 +412,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -440,18 +440,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -467,7 +467,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -483,28 +483,28 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-A5 Mixed Mode -By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 11. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/arm11/ac5/src/tx_thread_context_restore.s b/ports/arm11/ac5/src/tx_thread_context_restore.s index e9dbf9e0..d7bce36c 100644 --- a/ports/arm11/ac5/src/tx_thread_context_restore.s +++ b/ports/arm11/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask SVC_MODE_BITS EQU 0x13 ; SVC mode value ; @@ -55,44 +55,38 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -120,13 +114,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/arm11/ac5/src/tx_thread_context_save.s b/ports/arm11/ac5/src/tx_thread_context_save.s index 8c92eeb1..aa99af37 100644 --- a/ports/arm11/ac5/src/tx_thread_context_save.s +++ b/ports/arm11/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -45,43 +45,37 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -96,7 +90,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -116,7 +110,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -132,7 +126,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -146,13 +140,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -172,7 +166,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -182,7 +176,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -197,7 +191,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s b/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s index af516975..41fc0eac 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits SVC_MODE_BITS EQU 0x13 ; SVC mode value @@ -57,44 +57,38 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -122,13 +116,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -172,7 +166,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -219,7 +213,7 @@ __tx_thread_fiq_preempt_restore BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/arm11/ac5/src/tx_thread_fiq_context_save.s b/ports/arm11/ac5/src/tx_thread_fiq_context_save.s index 72bebd9d..7aa2c832 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s b/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s index 66b82422..69faffe0 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_cxsf, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s b/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s index fd36e17f..2bbd33e8 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_interrupt_control.s b/ports/arm11/ac5/src/tx_thread_interrupt_control.s index 7d3bddae..e51c993d 100644 --- a/ports/arm11/ac5/src/tx_thread_interrupt_control.s +++ b/ports/arm11/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm11/ac5/src/tx_thread_interrupt_disable.s b/ports/arm11/ac5/src/tx_thread_interrupt_disable.s index e2c50cfd..6224b590 100644 --- a/ports/arm11/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/arm11/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,41 +36,35 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm11/ac5/src/tx_thread_interrupt_restore.s b/ports/arm11/ac5/src/tx_thread_interrupt_restore.s index ad7fb5d2..a35c0621 100644 --- a/ports/arm11/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/arm11/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s b/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s index a8ee12ad..83e93891 100644 --- a/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_cxsf, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s b/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s index aea8bbf4..d658bf1c 100644 --- a/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_schedule.s b/ports/arm11/ac5/src/tx_thread_schedule.s index 17646482..b8bc01e6 100644 --- a/ports/arm11/ac5/src/tx_thread_schedule.s +++ b/ports/arm11/ac5/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -47,45 +47,39 @@ ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -112,7 +106,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -121,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -135,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/arm11/ac5/src/tx_thread_stack_build.s b/ports/arm11/ac5/src/tx_thread_stack_build.s index 83821335..64482069 100644 --- a/ports/arm11/ac5/src/tx_thread_stack_build.s +++ b/ports/arm11/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,44 +38,38 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -83,10 +77,10 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the ARM11 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/arm11/ac5/src/tx_thread_system_return.s b/ports/arm11/ac5/src/tx_thread_system_return.s index 82a1e0c4..37ce7066 100644 --- a/ports/arm11/ac5/src/tx_thread_system_return.s +++ b/ports/arm11/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,50 +40,44 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -96,12 +90,12 @@ _tx_thread_system_return MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1, r4-r11, lr} ; Save minimal context -; +; ; /* Lockout interrupts. */ ; ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR MSR CPSR_cxsf, r2 ; Disable interrupts - + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ diff --git a/ports/arm11/ac5/src/tx_thread_vectored_context_save.s b/ports/arm11/ac5/src/tx_thread_vectored_context_save.s index e9ae138a..ca013608 100644 --- a/ports/arm11/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/arm11/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -45,43 +45,37 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -144,7 +138,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -180,7 +174,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/arm11/ac5/src/tx_timer_interrupt.s b/ports/arm11/ac5/src/tx_timer_interrupt.s index 9d745e0a..c5b7ee10 100644 --- a/ports/arm11/ac5/src/tx_timer_interrupt.s +++ b/ports/arm11/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/arm11/gnu/example_build/crt0.S b/ports/arm11/gnu/example_build/crt0.S index aa0f3239..56b6c958 100644 --- a/ports/arm11/gnu/example_build/crt0.S +++ b/ports/arm11/gnu/example_build/crt0.S @@ -26,13 +26,13 @@ _mainCRTStartup: mov a2, #0 /* Second arg: fill value */ mov fp, a2 /* Null frame pointer */ mov r7, a2 /* Null frame pointer for Thumb */ - + ldr a1, .LC1 /* First arg: start of memory block */ - ldr a3, .LC2 + ldr a3, .LC2 sub a3, a3, a1 /* Third arg: length of block */ - - + + bl memset mov r0, #0 /* no arguments */ mov r1, #0 /* no argv either */ @@ -48,15 +48,15 @@ _mainCRTStartup: /* bl init */ mov r0, r4 mov r1, r5 -#endif +#endif bl main bl exit /* Should not return. */ - - /* For Thumb, constants must be after the code since only + + /* For Thumb, constants must be after the code since only positive offsets are supported for PC relative addresses. */ - + .align 0 .LC0: .LC1: diff --git a/ports/arm11/gnu/example_build/reset.S b/ports/arm11/gnu/example_build/reset.S index a11c826a..5d05258b 100644 --- a/ports/arm11/gnu/example_build/reset.S +++ b/ports/arm11/gnu/example_build/reset.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -65,11 +65,11 @@ SWI: .word __tx_swi_interrupt @ Software interrupt handler PREFETCH: .word __tx_prefetch_handler @ Prefetch exception handler -ABORT: +ABORT: .word __tx_abort_handler @ Abort exception handler -RESERVED: +RESERVED: .word __tx_reserved_handler @ Reserved exception handler -IRQ: +IRQ: .word __tx_irq_handler @ IRQ interrupt handler FIQ: .word __tx_fiq_handler @ FIQ interrupt handler diff --git a/ports/arm11/gnu/example_build/sample_threadx.c b/ports/arm11/gnu/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/arm11/gnu/example_build/sample_threadx.c +++ b/ports/arm11/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm11/gnu/example_build/sample_threadx.ld b/ports/arm11/gnu/example_build/sample_threadx.ld index 3dea4e1c..e940b2b8 100644 --- a/ports/arm11/gnu/example_build/sample_threadx.ld +++ b/ports/arm11/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/arm11/gnu/example_build/tx_initialize_low_level.S b/ports/arm11/gnu/example_build/tx_initialize_low_level.S index f7c4617a..887ae4e0 100644 --- a/ports/arm11/gnu/example_build/tx_initialize_low_level.S +++ b/ports/arm11/gnu/example_build/tx_initialize_low_level.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -62,7 +62,7 @@ SYS_STACK_SIZE = 1024 @ System stack size .type $_tx_initialize_low_level,function $_tx_initialize_low_level: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_initialize_low_level @ Call _tx_initialize_low_level function @@ -72,45 +72,39 @@ $_tx_initialize_low_level: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level ARM11/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -125,7 +119,7 @@ _tx_initialize_low_level: @ LDR r1, =_sp @ Get pointer to stack area -#ifdef TX_ENABLE_IRQ_NESTING +#ifdef TX_ENABLE_IRQ_NESTING @ @ /* Setup the system mode stack for nested interrupt support */ @ @@ -156,7 +150,7 @@ _tx_initialize_low_level: MSR CPSR, r0 @ Enter SVC mode LDR r2, =_stack_bottom @ Pickup stack bottom CMP r3, r2 @ Compare the current stack end with the bottom -_stack_error_loop: +_stack_error_loop: BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! @ @ /* Save the system stack pointer. */ @@ -208,7 +202,7 @@ __tx_reserved_handler: B __tx_reserved_handler @ Reserved exception handler @ .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -216,17 +210,17 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -240,7 +234,7 @@ __tx_irq_processing_return: @ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -256,28 +250,28 @@ __tx_irq_processing_return: @__tx_example_vectored_irq_handler: @ @ -@ /* Save initial context and call context save to prepare for +@ /* Save initial context and call context save to prepare for @ vectored ISR execution. */ @ @ STMDB sp!, {r0-r3} @ Save some scratch registers @ MRS r0, SPSR @ Pickup saved SPSR -@ SUB lr, lr, #4 @ Adjust point of interrupt +@ SUB lr, lr, #4 @ Adjust point of interrupt @ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers @ BL _tx_thread_vectored_context_save @ Vectored context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_start @@ -286,7 +280,7 @@ __tx_irq_processing_return: @ /* Application IRQ handlers can be called here! */ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_end @@ -308,11 +302,11 @@ __tx_fiq_processing_return: @ /* At this point execution is still in the FIQ mode. The CPSR, point of @ interrupt, and all C scratch registers are available for use. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start @ from FIQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with FIQ interrupts enabled. +@ system mode and returns with FIQ interrupts enabled. @ -@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ NOTE: It is very important to ensure all FIQ interrupts are cleared @ prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/arm11/gnu/inc/tx_port.h b/ports/arm11/gnu/inc/tx_port.h index 65ffe076..259ad092 100644 --- a/ports/arm11/gnu/inc/tx_port.h +++ b/ports/arm11/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h ARM11/GNU */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM11/GNU */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include <string.h> -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,24 +238,24 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ - + #if __TARGET_ARCH_ARM > 4 #ifndef __thumb__ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ - b = 31 - b; + b = 31 - b; #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -307,8 +299,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARM11/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/gnu/readme_threadx.txt b/ports/arm11/gnu/readme_threadx.txt index d7300854..92a7c16d 100644 --- a/ports/arm11/gnu/readme_threadx.txt +++ b/ports/arm11/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for ARM11 + Microsoft's Azure RTOS ThreadX for ARM11 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the ARM11 using GNU tools is at label _start. +The entry point in ThreadX for the ARM11 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for ARM11 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The ARM11 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, ARM7 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, ARM7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. diff --git a/ports/arm11/gnu/src/tx_thread_context_restore.S b/ports/arm11/gnu/src/tx_thread_context_restore.S index 6a270b66..74fb495f 100644 --- a/ports/arm11/gnu/src/tx_thread_context_restore.S +++ b/ports/arm11/gnu/src/tx_thread_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -43,51 +43,42 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -115,13 +106,13 @@ _tx_thread_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs diff --git a/ports/arm11/gnu/src/tx_thread_context_save.S b/ports/arm11/gnu/src/tx_thread_context_save.S index 3fe539d2..c8d7e503 100644 --- a/ports/arm11/gnu/src/tx_thread_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -36,50 +36,41 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @@ -95,7 +86,7 @@ _tx_thread_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt CPSR @@ -115,7 +106,7 @@ _tx_thread_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -131,7 +122,7 @@ _tx_thread_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ __tx_thread_not_nested_save: @ } @@ -145,13 +136,13 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} @ Store other registers @ @ /* Save the current stack pointer in the thread's control block. */ @@ -171,7 +162,7 @@ __tx_thread_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @ else @@ -181,7 +172,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit @@ -196,7 +187,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #16 @ Recover saved registers - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @} diff --git a/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S b/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S index 3d3dd37a..5d6ed149 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -25,7 +25,7 @@ SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask THUMB_MASK = 0x20 @ Thumb bit mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits SVC_MODE_BITS = 0x13 @ SVC mode value @@ -47,47 +47,38 @@ SVC_MODE_BITS = 0x13 @ SVC mode value .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_restore ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the fiq interrupt context when processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* FIQ ISR Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) @@ -116,13 +107,13 @@ _tx_thread_fiq_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs @@ -213,7 +204,7 @@ __tx_thread_fiq_preempt_restore: BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it @ @ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -@ _tx_timer_time_slice = 0; +@ _tx_timer_time_slice = 0; @ STR r2, [r0, #24] @ Save thread's time-slice MOV r2, #0 @ Clear value diff --git a/ports/arm11/gnu/src/tx_thread_fiq_context_save.S b/ports/arm11/gnu/src/tx_thread_fiq_context_save.S index 8dc69191..93b33309 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,46 +34,37 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_save ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) @@ -89,7 +80,7 @@ _tx_thread_fiq_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state CMP r2, #0 @ Is this the first interrupt? @@ -104,7 +95,7 @@ _tx_thread_fiq_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -120,38 +111,38 @@ _tx_thread_fiq_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ __tx_thread_fiq_not_nested_save: -@ } +@ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @ else if (_tx_thread_current_ptr) -@ { +@ { @ ADD r2, r2, #1 @ Increment the interrupt counter STR r2, [r3] @ Store it back in the variable LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in -@ @ scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, lr} @ Store other registers, Note that we don't -@ @ need to save sl and ip since FIQ has -@ @ copies of these registers. Nested +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested @ @ interrupt processing does need to save @ @ these registers. @ @ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; @ @ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr; +@ sp = _tx_thread_system_stack_ptr; @ MOV r10, #0 @ Clear stack limit @@ -164,7 +155,7 @@ __tx_thread_fiq_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } @ else @@ -184,16 +175,16 @@ __tx_thread_fiq_idle_system_save: #endif @ @ /* Not much to do here, save the current SPSR and LR for possible -@ use in IRQ interrupted in idle system conditions, and return to +@ use in IRQ interrupted in idle system conditions, and return to @ FIQ interrupt processing. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, lr} @ Store other registers that will get used -@ @ or stripped off the stack in context -@ @ restore - B __tx_fiq_processing_return @ Continue FIQ processing +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } -@} +@} diff --git a/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S b/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S index 82362bbc..1e9ba513 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask FIQ_MODE_BITS = 0x11 @ FIQ mode bits @ @ @@ -37,54 +37,45 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_end ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -@/* processing from system mode back to FIQ mode prior to the ISR */ -@/* calling _tx_thread_fiq_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) @@ -96,7 +87,7 @@ _tx_thread_fiq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_cxsf, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S b/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S index 5a6b6e1b..2f7f4f52 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,51 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_start ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -@/* processing to the system mode so nested FIQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_control.S b/ports/arm11/gnu/src/tx_thread_interrupt_control.S index ecc9326d..dd8b127c 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_control.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_control.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -35,7 +35,7 @@ INT_MASK = 0x03F $_tx_thread_interrupt_control: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function @@ -45,45 +45,36 @@ $_tx_thread_interrupt_control: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_disable.S b/ports/arm11/gnu/src/tx_thread_interrupt_disable.S index f51c2238..fb369d0b 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_disable.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -38,7 +38,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled $_tx_thread_interrupt_disable: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function @@ -48,44 +48,35 @@ $_tx_thread_interrupt_disable: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_disable ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for disabling interrupts */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_restore.S b/ports/arm11/gnu/src/tx_thread_interrupt_restore.S index 8506be1b..78c85f91 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,7 +31,7 @@ $_tx_thread_interrupt_restore: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function @@ -41,45 +41,36 @@ $_tx_thread_interrupt_restore: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_restore ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function is responsible for restoring interrupts to the state */ @/* returned by a previous _tx_thread_interrupt_disable call. */ -@/* */ -@/* INPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S b/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S index 649bbbb0..26504a38 100644 --- a/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @ @@ -37,54 +37,45 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_end ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -@/* processing from system mode back to IRQ mode prior to the ISR */ -@/* calling _tx_thread_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) @@ -96,7 +87,7 @@ _tx_thread_irq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_cxsf, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S b/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S index ee949845..12bedd93 100644 --- a/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,51 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_start ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_context_save has been called and switches the IRQ */ -@/* processing to the system mode so nested IRQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_schedule.S b/ports/arm11/gnu/src/tx_thread_schedule.S index 9350540c..2901fbef 100644 --- a/ports/arm11/gnu/src/tx_thread_schedule.S +++ b/ports/arm11/gnu/src/tx_thread_schedule.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -45,7 +45,7 @@ ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask $_tx_thread_schedule: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_schedule @ Call _tx_thread_schedule function @@ -55,48 +55,39 @@ $_tx_thread_schedule: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_schedule ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function waits for a thread control block pointer to appear in */ -@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -@/* in the variable, the corresponding thread is resumed. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ @/* None */ -@/* */ -@/* CALLS */ -@/* */ +@/* */ +@/* OUTPUT */ +@/* */ @/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* _tx_thread_system_return Return to system from thread */ -@/* _tx_thread_context_restore Restore thread's context */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -124,7 +115,7 @@ __tx_thread_schedule_loop: @ @ } @ while(_tx_thread_execute_ptr == TX_NULL); -@ +@ @ /* Yes! We have a thread to execute. Lockout interrupts and @ transfer control to it. */ @ @@ -133,7 +124,7 @@ __tx_thread_schedule_loop: @ /* Setup the current thread pointer. */ @ _tx_thread_current_ptr = _tx_thread_execute_ptr; @ - LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread STR r0, [r1] @ Setup current thread pointer @ @ /* Increment the run count for this thread. */ @@ -147,7 +138,7 @@ __tx_thread_schedule_loop: @ /* Setup time-slice, if present. */ @ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; @ - LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice @ variable LDR sp, [r0, #8] @ Switch stack pointers STR r3, [r2] @ Setup time-slice diff --git a/ports/arm11/gnu/src/tx_thread_stack_build.S b/ports/arm11/gnu/src/tx_thread_stack_build.S index 7f156ee0..989916ca 100644 --- a/ports/arm11/gnu/src/tx_thread_stack_build.S +++ b/ports/arm11/gnu/src/tx_thread_stack_build.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -42,7 +42,7 @@ CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interru .type $_tx_thread_stack_build,function $_tx_thread_stack_build: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_stack_build @ Call _tx_thread_stack_build function @@ -52,47 +52,38 @@ $_tx_thread_stack_build: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function builds a stack frame on the supplied thread's stack. */ @/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ @/* thread_ptr Pointer to thread control blk */ @/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ +@/* */ +@/* OUTPUT */ +@/* */ @/* None */ -@/* */ -@/* CALLS */ -@/* */ +@/* */ +@/* CALLS */ +@/* */ @/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -101,10 +92,10 @@ $_tx_thread_stack_build: .type _tx_thread_stack_build,function _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on theARM11 should look like the following after it is built: -@ +@ @ Stack Top: 1 Interrupt stack frame type @ CPSR Initial value for CPSR @ a1 (r0) Initial value for a1 diff --git a/ports/arm11/gnu/src/tx_thread_system_return.S b/ports/arm11/gnu/src/tx_thread_system_return.S index 1c26a7a0..c15ae266 100644 --- a/ports/arm11/gnu/src/tx_thread_system_return.S +++ b/ports/arm11/gnu/src/tx_thread_system_return.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -48,7 +48,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled $_tx_thread_system_return: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_system_return @ Call _tx_thread_system_return function @@ -58,47 +58,38 @@ $_tx_thread_system_return: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) @@ -112,12 +103,12 @@ _tx_thread_system_return: MOV r0, #0 @ Build a solicited stack type MRS r1, CPSR @ Pickup the CPSR STMDB sp!, {r0-r1, r4-r11, lr} @ Save minimal context -@ +@ @ /* Lockout interrupts. */ @ ORR r2, r1, #DISABLE_INTS @ Build disable interrupt CPSR MSR CPSR_cxsf, r2 @ Disable interrupts - + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @ /* Call the thread exit function to indicate the thread is no longer executing. */ diff --git a/ports/arm11/gnu/src/tx_thread_vectored_context_save.S b/ports/arm11/gnu/src/tx_thread_vectored_context_save.S index 23f82007..391cf717 100644 --- a/ports/arm11/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_vectored_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,50 +37,41 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_vectored_context_save ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) @@ -140,7 +131,7 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Note: Minimal context of interrupted thread is already saved. */ @@ -172,7 +163,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports/arm11/gnu/src/tx_timer_interrupt.S b/ports/arm11/gnu/src/tx_timer_interrupt.S index 137c5883..1236ec49 100644 --- a/ports/arm11/gnu/src/tx_timer_interrupt.S +++ b/ports/arm11/gnu/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Timer */ @/** */ @@ -48,7 +48,7 @@ .type $_tx_timer_interrupt,function $_tx_timer_interrupt: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_timer_interrupt @ Call _tx_timer_interrupt function @@ -58,49 +58,40 @@ $_tx_timer_interrupt: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -125,7 +116,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -243,7 +234,7 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired LDR r2, [r3] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing diff --git a/ports/arm11/iar/example_build/cstartup.s b/ports/arm11/iar/example_build/cstartup.s index b95efc0e..3da2b79d 100644 --- a/ports/arm11/iar/example_build/cstartup.s +++ b/ports/arm11/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports/arm11/iar/example_build/sample_threadx.c b/ports/arm11/iar/example_build/sample_threadx.c index a57d908d..f9d0e94a 100644 --- a/ports/arm11/iar/example_build/sample_threadx.c +++ b/ports/arm11/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,42 +85,42 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -128,23 +128,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -247,11 +247,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -310,7 +310,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -363,7 +363,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm11/iar/example_build/tx_initialize_low_level.s b/ports/arm11/iar/example_build/tx_initialize_low_level.s index 7242cfe4..61d554bc 100644 --- a/ports/arm11/iar/example_build/tx_initialize_low_level.s +++ b/ports/arm11/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -62,7 +62,7 @@ SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -75,47 +75,41 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -146,7 +140,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -188,7 +182,7 @@ __tx_reserved_handler RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -196,17 +190,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -221,7 +215,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -240,22 +234,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -264,7 +258,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -288,11 +282,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/arm11/iar/inc/tx_port.h b/ports/arm11/iar/inc/tx_port.h index 3f965ba3..52b43a86 100644 --- a/ports/arm11/iar/inc/tx_port.h +++ b/ports/arm11/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,38 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h ARM11/IAR */ -/* 6.1.6 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM11/IAR */ +/* 6.1.6 */ +/* */ +/* AUTHOR */ /* */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* */ -/**************************************************************************/ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -130,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -188,7 +180,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -202,17 +194,17 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -226,11 +218,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -240,23 +232,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -284,8 +276,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -296,22 +288,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -373,8 +365,8 @@ void _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARM11/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm11/iar/readme_threadx.txt b/ports/arm11/iar/readme_threadx.txt index fbe7deeb..8a4ef703 100644 --- a/ports/arm11/iar/readme_threadx.txt +++ b/ports/arm11/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for ARM11 + Microsoft's Azure RTOS ThreadX for ARM11 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,52 +20,52 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based ARM11 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's ARM11 simulator. A SPECIAL NOTE: The IAR ARM simulator does simulate interrupts. In order -for the ThreadX demonstration to run properly, a periodic IRQ interrupt must +for the ThreadX demonstration to run properly, a periodic IRQ interrupt must be setup in the IAR debugging environment. We recommend setting an IRQ interrupt to execute every 9999 cycles. 3. System Initialization -The entry point in ThreadX for the ARM11 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the ARM11 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -83,12 +83,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -97,146 +97,146 @@ The following are conditional compilation options for building the ThreadX libra and application: - TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables FIQ interrupt handling support in the ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_THUMB Defined, this option enables the BX LR calling return sequence @@ -250,29 +250,29 @@ and application: 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for ARM11 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The ARM11 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -283,12 +283,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -296,7 +296,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -309,7 +309,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -320,12 +320,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -342,24 +342,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -367,15 +367,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -383,7 +383,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -394,12 +394,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, ARM11 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, ARM11 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -408,7 +408,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -439,18 +439,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested FIQ interrupts are no -longer required, calling the _tx_thread_fiq_nesting_end service disables -nesting by disabling FIQ interrupts and switching back to FIQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -468,7 +468,7 @@ __tx_fiq_processing_return: ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -484,22 +484,22 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/ARM11 Mixed Mode -By default, ThreadX is setup for running in ARM11 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in ARM11 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be -built in 32-bit mode. In addition, if any Thumb code is used the entire +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX assembly source should be built with TX_THUMB defined. @@ -511,7 +511,7 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. diff --git a/ports/arm11/iar/src/tx_iar.c b/ports/arm11/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/arm11/iar/src/tx_iar.c +++ b/ports/arm11/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/arm11/iar/src/tx_thread_context_restore.s b/ports/arm11/iar/src/tx_thread_context_restore.s index 211b81dd..addf7705 100644 --- a/ports/arm11/iar/src/tx_thread_context_restore.s +++ b/ports/arm11/iar/src/tx_thread_context_restore.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -52,46 +52,40 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -119,13 +113,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/arm11/iar/src/tx_thread_context_save.s b/ports/arm11/iar/src/tx_thread_context_save.s index c4d5b1b4..26a3b4d2 100644 --- a/ports/arm11/iar/src/tx_thread_context_save.s +++ b/ports/arm11/iar/src/tx_thread_context_save.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -44,45 +44,39 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -97,7 +91,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -117,7 +111,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -133,7 +127,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -147,13 +141,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -173,7 +167,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -183,7 +177,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -198,7 +192,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/arm11/iar/src/tx_thread_fiq_context_restore.s b/ports/arm11/iar/src/tx_thread_fiq_context_restore.s index 31824589..d9f8a37a 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/arm11/iar/src/tx_thread_fiq_context_restore.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,7 +38,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -53,46 +53,40 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value EXTERN _tx_execution_isr_exit ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -120,13 +114,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -170,7 +164,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -217,7 +211,7 @@ __tx_thread_fiq_preempt_restore BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/arm11/iar/src/tx_thread_fiq_context_save.s b/ports/arm11/iar/src/tx_thread_fiq_context_save.s index 17062581..55860011 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_context_save.s +++ b/ports/arm11/iar/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,45 +36,39 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -89,7 +83,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -104,7 +98,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -120,38 +114,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -164,7 +158,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -184,18 +178,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; ; END diff --git a/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s b/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s index 0d71933a..2dbab8e5 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,57 +34,51 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s b/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s index 7b2b36cb..2bbbe9b6 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,50 +35,44 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_interrupt_control.s b/ports/arm11/iar/src/tx_thread_interrupt_control.s index 4cf6b917..22f39ddf 100644 --- a/ports/arm11/iar/src/tx_thread_interrupt_control.s +++ b/ports/arm11/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,44 +35,38 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_interrupt_disable.s b/ports/arm11/iar/src/tx_thread_interrupt_disable.s index e1a61860..d963c895 100644 --- a/ports/arm11/iar/src/tx_thread_interrupt_disable.s +++ b/ports/arm11/iar/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,43 +36,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_interrupt_restore.s b/ports/arm11/iar/src/tx_thread_interrupt_restore.s index 28856151..4bc8e9c2 100644 --- a/ports/arm11/iar/src/tx_thread_interrupt_restore.s +++ b/ports/arm11/iar/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,44 +28,38 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_irq_nesting_end.s b/ports/arm11/iar/src/tx_thread_irq_nesting_end.s index 7a7a3585..3695a57f 100644 --- a/ports/arm11/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/arm11/iar/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,57 +35,51 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_irq_nesting_start.s b/ports/arm11/iar/src/tx_thread_irq_nesting_start.s index b76d1ff6..e538ca1b 100644 --- a/ports/arm11/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/arm11/iar/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,50 +35,44 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_schedule.s b/ports/arm11/iar/src/tx_thread_schedule.s index 761ec21c..e4a4da47 100644 --- a/ports/arm11/iar/src/tx_thread_schedule.s +++ b/ports/arm11/iar/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -43,47 +43,41 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -111,7 +105,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -120,7 +114,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -134,7 +128,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/arm11/iar/src/tx_thread_stack_build.s b/ports/arm11/iar/src/tx_thread_stack_build.s index 4e32e1fa..13981a6c 100644 --- a/ports/arm11/iar/src/tx_thread_stack_build.s +++ b/ports/arm11/iar/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,58 +37,52 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ +;/* */ +;/* CALLED BY */ +;/* */ ;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + CODE32 _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the ARM9 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/arm11/iar/src/tx_thread_system_return.s b/ports/arm11/iar/src/tx_thread_system_return.s index c7042dfb..2bc395e0 100644 --- a/ports/arm11/iar/src/tx_thread_system_return.s +++ b/ports/arm11/iar/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -42,46 +42,40 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -95,7 +89,7 @@ _tx_thread_system_return MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1, r4-r11, lr} ; Save minimal context -; +; ; /* Lockout interrupts. */ ; ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR diff --git a/ports/arm11/iar/src/tx_thread_vectored_context_save.s b/ports/arm11/iar/src/tx_thread_vectored_context_save.s index e287b8a5..15598036 100644 --- a/ports/arm11/iar/src/tx_thread_vectored_context_save.s +++ b/ports/arm11/iar/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,45 +41,39 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -139,7 +133,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/arm11/iar/src/tx_timer_interrupt.s b/ports/arm11/iar/src/tx_timer_interrupt.s index 550bc007..13c26851 100644 --- a/ports/arm11/iar/src/tx_timer_interrupt.s +++ b/ports/arm11/iar/src/tx_timer_interrupt.s @@ -1,20 +1,20 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -45,48 +45,42 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -110,7 +104,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -228,13 +222,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; |