diff options
Diffstat (limited to 'ports/arm9/ac5/example_build')
| -rw-r--r-- | ports/arm9/ac5/example_build/sample_threadx.c | 46 | ||||
| -rw-r--r-- | ports/arm9/ac5/example_build/tx_initialize_low_level.s | 122 |
2 files changed, 81 insertions, 87 deletions
diff --git a/ports/arm9/ac5/example_build/sample_threadx.c b/ports/arm9/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/arm9/ac5/example_build/sample_threadx.c +++ b/ports/arm9/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm9/ac5/example_build/tx_initialize_low_level.s b/ports/arm9/ac5/example_build/tx_initialize_low_level.s index f2420967..49dd2736 100644 --- a/ports/arm9/ac5/example_build/tx_initialize_low_level.s +++ b/ports/arm9/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -41,7 +41,7 @@ SYS_STACK_SIZE EQU 1024 ; SYS stack size (used for neste IRQ_STACK_SIZE EQU 1024 ; IRQ stack size ; ; -;/* ARM9 ARMulator Timer and Interrupt controller information. This depends on +;/* ARM9 ARMulator Timer and Interrupt controller information. This depends on ; the ARMulator's Interrupt Controller and Timer being enabled in the default.ami. ; In addition, the addresses must match those specified in the peripherals.ami file. ; Please refer to section 2.10 and 4.16 of the Debug Target Guide, version 1.2. */ @@ -50,7 +50,7 @@ IRQStatus EQU 0x0a000000 ; IRQ Status Register IRQRawStatus EQU 0x0a000004 ; IRQ Raw Status Register IRQEnable EQU 0x0a000008 ; IRQ Enable Set Register IRQEnableClear EQU 0x0a00000C ; IRQ Enable Clear Register -IRQSoft EQU 0x0a000010 ; IRQ Soft +IRQSoft EQU 0x0a000010 ; IRQ Soft FIQStatus EQU 0x0a000100 ; FIQ Status Register FIQRawStatus EQU 0x0a000104 ; FIQ Raw Status Register FIQEnable EQU 0x0a000108 ; FIQ Enable Set Register @@ -113,45 +113,39 @@ __vectors ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -202,7 +196,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -238,7 +232,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -290,7 +284,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -298,34 +292,34 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; ; /* Check for Timer1 interrupts on the ARMulator. */ LDR r1,=IRQStatus ; Pickup address of IRQStatus register - LDR r2, [r1] ; Read IRQStatus + LDR r2, [r1] ; Read IRQStatus LDR r0,=TIMER1_BIT ; Pickup Timer1 interrupt present bit AND r2, r2, r0 ; Is this a timer interrupt? - CMP r2, r0 ; + CMP r2, r0 ; BNE _tx_not_timer_interrupt ; If 0, not a timer interrupt LDR r1,=Timer1Clear ; Build address of Timer1 clear register - MOV r0,#0 ; + MOV r0,#0 ; STR r0, [r1] ; Clear timer 0 interrupt BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -335,7 +329,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -351,28 +345,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -381,7 +375,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -403,11 +397,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start |