diff options
Diffstat (limited to 'ports/cortex_a34')
39 files changed, 568 insertions, 286 deletions
diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a34/ac6/example_build/sample_threadx/.cproject index 7310f92f..9d1e039f 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/.cproject @@ -29,7 +29,7 @@ <toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.1388095870" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6"> - <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.689426261" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="cortex-a34.AArch64.ARMv8.Neon.Crypto" valueType="string"/> + <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.689426261" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A34.AArch64.ARMv8.Neon.Crypto" valueType="string"/> <targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.1388095870.857809581" name=""/> diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_aliases.h b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_aliases.h new file mode 100644 index 00000000..826ba973 --- /dev/null +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_aliases.h @@ -0,0 +1,113 @@ +// +// Aliases for GICv3 registers +// +// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef GICV3_ALIASES_H +#define GICV3_ALIASES_H + +#ifndef __clang__ + +/* + * Mapping of MSR and MRS to physical and virtual CPU interface registers + * + * Arm Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-5 + */ +#define ICC_AP0R0_EL1 S3_0_C12_C8_4 +#define ICC_AP0R1_EL1 S3_0_C12_C8_5 +#define ICC_AP0R2_EL1 S3_0_C12_C8_6 +#define ICC_AP0R3_EL1 S3_0_C12_C8_7 + +#define ICC_AP1R0_EL1 S3_0_C12_C9_0 +#define ICC_AP1R1_EL1 S3_0_C12_C9_1 +#define ICC_AP1R2_EL1 S3_0_C12_C9_2 +#define ICC_AP1R3_EL1 S3_0_C12_C9_3 + +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 + +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 + +#define ICC_DIR_EL1 S3_0_C12_C11_1 + +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 + +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 + +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 + +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 + +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 + +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 + +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 + +/* + * Mapping of MSR and MRS to virtual interface control registers + * + * Arm Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-6 + */ +#define ICH_AP0R0_EL2 S3_4_C12_C8_0 +#define ICH_AP0R1_EL2 S3_4_C12_C8_1 +#define ICH_AP0R2_EL2 S3_4_C12_C8_2 +#define ICH_AP0R3_EL2 S3_4_C12_C8_3 + +#define ICH_AP1R0_EL2 S3_4_C12_C9_0 +#define ICH_AP1R1_EL2 S3_4_C12_C9_1 +#define ICH_AP1R2_EL2 S3_4_C12_C9_2 +#define ICH_AP1R3_EL2 S3_4_C12_C9_3 + +#define ICH_HCR_EL2 S3_4_C12_C11_0 + +#define ICH_VTR_EL2 S3_4_C12_C11_1 + +#define ICH_MISR_EL2 S3_4_C12_C11_2 + +#define ICH_EISR_EL2 S3_4_C12_C11_3 + +#define ICH_ELRSR_EL2 S3_4_C12_C11_5 + +#define ICH_VMCR_EL2 S3_4_C12_C11_7 + +#define ICH_LR0_EL2 S3_4_C12_C12_0 +#define ICH_LR1_EL2 S3_4_C12_C12_1 +#define ICH_LR2_EL2 S3_4_C12_C12_2 +#define ICH_LR3_EL2 S3_4_C12_C12_3 +#define ICH_LR4_EL2 S3_4_C12_C12_4 +#define ICH_LR5_EL2 S3_4_C12_C12_5 +#define ICH_LR6_EL2 S3_4_C12_C12_6 +#define ICH_LR7_EL2 S3_4_C12_C12_7 +#define ICH_LR8_EL2 S3_4_C12_C13_0 +#define ICH_LR9_EL2 S3_4_C12_C13_1 +#define ICH_LR10_EL2 S3_4_C12_C13_2 +#define ICH_LR11_EL2 S3_4_C12_C13_3 +#define ICH_LR12_EL2 S3_4_C12_C13_4 +#define ICH_LR13_EL2 S3_4_C12_C13_5 +#define ICH_LR14_EL2 S3_4_C12_C13_6 +#define ICH_LR15_EL2 S3_4_C12_C13_7 + +#endif /* not __clang__ */ + +#endif /* GICV3_ALIASES */ diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicc.h b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicc.h index beaa9157..998d92b5 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicc.h +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicc.h @@ -9,6 +9,11 @@ #ifndef GICV3_gicc_h #define GICV3_gicc_h +#include "GICv3_aliases.h" + +#define stringify_no_expansion(x) #x +#define stringify(x) stringify_no_expansion(x) + /**********************************************************************/ typedef enum @@ -21,42 +26,42 @@ typedef enum static inline void setICC_SRE_EL1(ICC_SREBits_t mode) { - asm("msr ICC_SRE_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); + asm("msr "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); } static inline uint64_t getICC_SRE_EL1(void) { uint64_t retc; - asm("mrs %0, ICC_SRE_EL1\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc)); return retc; } static inline void setICC_SRE_EL2(ICC_SREBits_t mode) { - asm("msr ICC_SRE_EL2, %0\n; isb" :: "r" ((uint64_t)mode)); + asm("msr "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode)); } static inline uint64_t getICC_SRE_EL2(void) { uint64_t retc; - asm("mrs %0, ICC_SRE_EL2\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc)); return retc; } static inline void setICC_SRE_EL3(ICC_SREBits_t mode) { - asm("msr ICC_SRE_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); + asm("msr "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); } static inline uint64_t getICC_SRE_EL3(void) { uint64_t retc; - asm("mrs %0, ICC_SRE_EL3\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc)); return retc; } @@ -72,17 +77,17 @@ typedef enum static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode) { - asm("msr ICC_IGRPEN0_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); + asm("msr "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); } static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode) { - asm("msr ICC_IGRPEN1_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); + asm("msr "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); } static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode) { - asm("msr ICC_IGRPEN1_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); + asm("msr "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); } /**********************************************************************/ @@ -102,28 +107,28 @@ typedef enum static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode) { - asm("msr ICC_CTLR_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); + asm("msr "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); } static inline uint64_t getICC_CTLR_EL1(void) { uint64_t retc; - asm("mrs %0, ICC_CTLR_EL1\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc)); return retc; } static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode) { - asm("msr ICC_CTLR_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); + asm("msr "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); } static inline uint64_t getICC_CTLR_EL3(void) { uint64_t retc; - asm("mrs %0, ICC_CTLR_EL3\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc)); return retc; } @@ -134,7 +139,7 @@ static inline uint64_t getICC_IAR0(void) { uint64_t retc; - asm("mrs %0, ICC_IAR0_EL1\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc)); return retc; } @@ -143,46 +148,46 @@ static inline uint64_t getICC_IAR1(void) { uint64_t retc; - asm("mrs %0, ICC_IAR1_EL1\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc)); return retc; } static inline void setICC_EOIR0(uint32_t interrupt) { - asm("msr ICC_EOIR0_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); + asm("msr "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); } static inline void setICC_EOIR1(uint32_t interrupt) { - asm("msr ICC_EOIR1_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); + asm("msr "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); } static inline void setICC_DIR(uint32_t interrupt) { - asm("msr ICC_DIR_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); + asm("msr "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); } static inline void setICC_PMR(uint32_t priority) { - asm("msr ICC_PMR_EL1, %0\n; isb" :: "r" ((uint64_t)priority)); + asm("msr "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority)); } static inline void setICC_BPR0(uint32_t binarypoint) { - asm("msr ICC_BPR0_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint)); + asm("msr "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint)); } static inline void setICC_BPR1(uint32_t binarypoint) { - asm("msr ICC_BPR1_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint)); + asm("msr "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint)); } static inline uint64_t getICC_BPR0(void) { uint64_t retc; - asm("mrs %0, ICC_BPR0_EL1\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc)); return retc; } @@ -191,7 +196,7 @@ static inline uint64_t getICC_BPR1(void) { uint64_t retc; - asm("mrs %0, ICC_BPR1_EL1\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc)); return retc; } @@ -200,7 +205,7 @@ static inline uint64_t getICC_RPR(void) { uint64_t retc; - asm("mrs %0, ICC_RPR_EL1\n" : "=r" (retc)); + asm("mrs %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc)); return retc; } @@ -221,7 +226,7 @@ static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2, ((uint64_t)aff1 << 16) | irm | targetlist | \ ((uint64_t)(intid & 0x0f) << 24)); - asm("msr ICC_SGI0R_EL1, %0\n; isb" :: "r" (packedbits)); + asm("msr "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits)); } static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2, @@ -232,7 +237,7 @@ static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2, ((uint64_t)aff1 << 16) | irm | targetlist | \ ((uint64_t)(intid & 0x0f) << 24)); - asm("msr ICC_SGI1R_EL1, %0\n; isb" :: "r" (packedbits)); + asm("msr "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits)); } static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2, @@ -243,7 +248,7 @@ static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2, ((uint64_t)aff1 << 16) | irm | targetlist | \ ((uint64_t)(intid & 0x0f) << 24)); - asm("msr ICC_ASGI1R_EL1, %0\n; isb" :: "r" (packedbits)); + asm("msr "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits)); } #endif /* ndef GICV3_gicc_h */ diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicr.c b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicr.c index 912ab2e4..d91aeb27 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicr.c +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicr.c @@ -293,7 +293,7 @@ void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group) uint32_t groupmod; /* - * get each bit of group config duplicated over all 32 bits + * get each bit of group config duplicated over all 32-bits */ groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); group = (uint32_t)(((int32_t)group << nbits) >> 31); diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.launch b/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.launch index 44afb600..7c5d62bb 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.launch +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.launch @@ -5,64 +5,64 @@ <stringAttribute key="ANDROID_APP_DIR" value=""/> <stringAttribute key="ANDROID_PROCESS_NAME" value=""/> <mapAttribute key="AverageDurationTracker"> - <mapEntry key="*Fetching Data Model" value="2175329"/> - <mapEntry key="*list global low level symbols" value="1285824"/> + <mapEntry key="*Fetching Data Model" value="2164664"/> + <mapEntry key="*list global low level symbols" value="1257028"/> <mapEntry key="*loading memory from target" value="820184"/> - <mapEntry key="*loading values from target" value="19105203"/> + <mapEntry key="*loading values from target" value="17587201"/> <mapEntry key="*trace" value="71991640"/> - <mapEntry key="*updating expressions" value="116156985"/> + <mapEntry key="*updating expressions" value="65540292"/> <mapEntry key="*updating registers" value="44165495"/> <mapEntry key="*updating variables" value="8591428"/> <mapEntry key="Add Watchpoint" value="24597988"/> - <mapEntry key="AddEventObserver" value="3783094"/> - <mapEntry key="Evaluate" value="5585240"/> + <mapEntry key="AddEventObserver" value="3303997"/> + <mapEntry key="Evaluate" value="9741530"/> <mapEntry key="GlobalsLoaderCommand" value="154351059"/> <mapEntry key="areCachesAvailable" value="1362117"/> <mapEntry key="backtrace" value="5112231"/> <mapEntry key="break" value="2857608"/> <mapEntry key="checking tracepoints" value="181653"/> - <mapEntry key="compute execution mode" value="8129999"/> - <mapEntry key="continue" value="29213923"/> + <mapEntry key="compute execution mode" value="2388424"/> + <mapEntry key="continue" value="17295461"/> <mapEntry key="core" value="3940900"/> - <mapEntry key="directory" value="3909111"/> + <mapEntry key="directory" value="3642355"/> <mapEntry key="disable" value="1478680"/> - <mapEntry key="disassemble" value="108875923"/> + <mapEntry key="disassemble" value="73653580"/> <mapEntry key="enable" value="1860234"/> <mapEntry key="evaluate" value="2783965"/> <mapEntry key="evaluate address" value="17239727"/> <mapEntry key="get byte order" value="472733"/> - <mapEntry key="get capabilities" value="368069"/> - <mapEntry key="get execution addresss" value="998734"/> - <mapEntry key="get source lines" value="6158428"/> - <mapEntry key="get substitute paths" value="439569"/> + <mapEntry key="get capabilities" value="277384"/> + <mapEntry key="get execution addresss" value="803429"/> + <mapEntry key="get source lines" value="8797728"/> + <mapEntry key="get substitute paths" value="366134"/> <mapEntry key="get value" value="402104"/> <mapEntry key="getValidEncodings" value="1410473"/> - <mapEntry key="initialize command help" value="106557304"/> + <mapEntry key="initialize command help" value="91066852"/> <mapEntry key="interrupt" value="44963461"/> - <mapEntry key="list breakpoint options" value="1390967"/> - <mapEntry key="list breakpoints" value="1718183"/> - <mapEntry key="list instruction sets" value="1963806"/> - <mapEntry key="list signals" value="2235162"/> + <mapEntry key="list breakpoint options" value="1324766"/> + <mapEntry key="list breakpoints" value="1847541"/> + <mapEntry key="list instruction sets" value="1763403"/> + <mapEntry key="list signals" value="2185731"/> <mapEntry key="list source files" value="864344"/> - <mapEntry key="list watchpoint options" value="4710094"/> - <mapEntry key="list watchpoints" value="1044640"/> - <mapEntry key="loadfile" value="301226781"/> + <mapEntry key="list watchpoint options" value="4792947"/> + <mapEntry key="list watchpoints" value="1009370"/> + <mapEntry key="loadfile" value="374708990"/> <mapEntry key="next" value="25423704"/> <mapEntry key="nexti" value="29780513"/> <mapEntry key="remove" value="1521133"/> - <mapEntry key="run script" value="54442817"/> - <mapEntry key="set CWD" value="8047311"/> + <mapEntry key="run script" value="43050208"/> + <mapEntry key="set CWD" value="7281705"/> <mapEntry key="set breakpoint properties" value="4075180"/> - <mapEntry key="set debug-from" value="1635791"/> - <mapEntry key="set substitute-path" value="36281177"/> + <mapEntry key="set debug-from" value="1229495"/> + <mapEntry key="set substitute-path" value="35280088"/> <mapEntry key="set watchpoint properties" value="1458988"/> - <mapEntry key="source use_model_semihosting.ds" value="14186140"/> - <mapEntry key="start" value="61054248"/> + <mapEntry key="source use_model_semihosting.ds" value="11060320"/> + <mapEntry key="start" value="50342824"/> <mapEntry key="step" value="30959584"/> <mapEntry key="stepi" value="30815174"/> <mapEntry key="synchronizing trace ranges" value="74184"/> - <mapEntry key="toggleBreakpoint" value="5010527"/> - <mapEntry key="waitForTargetToStop" value="58813931"/> + <mapEntry key="toggleBreakpoint" value="11765863"/> + <mapEntry key="waitForTargetToStop" value="63934815"/> <mapEntry key="write expression" value="5812240"/> </mapAttribute> <stringAttribute key="CLOCK_SPEED" value="Auto"/> @@ -82,13 +82,10 @@ <stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/> <stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/> <intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/> - <listAttribute key="FILES.DOWNLOAD_AND_DEBUG"> - <listEntry value="ON_DEMAND_LOAD"/> - <listEntry value="ALSO_LOAD_SYMBOLS"/> - </listAttribute> + <listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/> <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/> <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/> - <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/> + <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/> <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/> <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/> <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/> @@ -96,16 +93,13 @@ <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/> <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/> <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/> - <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/> + <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/> <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/> <intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/> - <listAttribute key="FILES.DOWNLOAD_DEBUG"> - <listEntry value="ON_DEMAND_LOAD"/> - <listEntry value="ALSO_LOAD_SYMBOLS"/> - </listAttribute> + <listAttribute key="FILES.DOWNLOAD_DEBUG"/> <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/> <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/> - <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/> + <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/> <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/> <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/> <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/> @@ -113,7 +107,7 @@ <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/> <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/> <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/> - <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/> + <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/> <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/> <intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/> <intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/> @@ -238,7 +232,7 @@ <stringAttribute key="config_db_platform_name" value="Arm FVP (Installed with Arm DS) - Base_A34x1"/> <stringAttribute key="config_db_project_type" value="Bare Metal Debug"/> <stringAttribute key="config_db_project_type_id" value="BARE_METAL"/> - <stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/base_a35x1"/> + <stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/base_a34x1"/> <stringAttribute key="config_file" value="CDB://../../Arm FVP/Base_A34x1/iris_config.xml"/> <booleanAttribute key="connectOnly" value="false"/> <stringAttribute key="connect_existing_model" value="false"/> @@ -288,7 +282,7 @@ <mapEntry key="6" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/> <mapEntry key="7" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/> </mapAttribute> - <stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1	8	0	true	true	187	-1	true	1	false	true	90	-1	true	2	true	true	108	-1	true	3	true	true	57	-1	true	4	true	true	50	-1	true	5	true	true	37	-1	true	6	true	true	151	-1	true	7	true	true	53	-1	true"/> + <stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1	8	0	true	true	255	-1	true	1	false	true	127	-1	true	2	true	true	159	-1	true	3	true	true	75	-1	true	4	true	true	65	-1	true	5	true	true	48	-1	true	6	true	true	240	-1	true	7	true	true	69	-1	true"/> <stringAttribute key="debugger.view.MemoryView" value="<?xml version="1.0" encoding="UTF-8"?> <page> 	<memoryView/> </page> "/> <listAttribute key="debugger.view.MemoryView:current"> <listEntry value=""/> @@ -317,15 +311,10 @@ <stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/> <booleanAttribute key="runAfterConnect" value="false"/> <stringAttribute key="runTargetInitializationScript" value="${workspace_loc:/sample_threadx/use_model_semihosting.ds}"/> - <mapAttribute key="scripts_view_script_links"> - <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports\cortex_a35\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/> - <mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/> - </mapAttribute> <listAttribute key="setup"> <listEntry value="CDB://Scripts/rtsm_launcher.py"/> <listEntry value=""FVP_Base_Cortex-A34x1""/> </listAttribute> <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/> - <stringAttribute key="substitutePath" value="<?xml version="1.0" encoding="UTF-8"?> <tuplelist> 	<tuple> 		<ta>C:\temp1702\tx\</ta> 		<tb>C:\temp1702\tx\</tb> 	</tuple> </tuplelist> "/> <stringAttribute key="watchpoints" value="<?xml version="1.0" encoding="UTF-8"?> <watchpoints> </watchpoints> "/> </launchConfiguration> diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/startup.S b/ports/cortex_a34/ac6/example_build/sample_threadx/startup.S index 9f0fc211..3952a200 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/startup.S +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/startup.S @@ -13,7 +13,7 @@ #include "v8_mmu.h" #include "v8_system.h" - +#include "GICv3_aliases.h" .section StartUp, "ax" .balign 4 diff --git a/ports/cortex_a34/ac6/example_build/tx/.cproject b/ports/cortex_a34/ac6/example_build/tx/.cproject index a7e80321..dacd531b 100644 --- a/ports/cortex_a34/ac6/example_build/tx/.cproject +++ b/ports/cortex_a34/ac6/example_build/tx/.cproject @@ -29,7 +29,7 @@ <toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.174366982" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6"> - <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.319260876" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="cortex-a34.AArch64.ARMv8.Neon.Crypto" valueType="string"/> + <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.319260876" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A34.AArch64.ARMv8.Neon.Crypto" valueType="string"/> <targetPlatform id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.174366982.1434986226" name=""/> diff --git a/ports/cortex_a34/ac6/inc/tx_port.h b/ports/cortex_a34/ac6/inc/tx_port.h index 4487de47..691fedd8 100644 --- a/ports/cortex_a34/ac6/inc/tx_port.h +++ b/ports/cortex_a34/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.2.202603 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a34/ac6/src/tx_initialize_low_level.S b/ports/cortex_a34/ac6/src/tx_initialize_low_level.S index 55bcfaa8..7d2a4be3 100644 --- a/ports/cortex_a34/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a34/ac6/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -27,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,16 +68,18 @@ _tx_initialize_low_level: MSR DAIFSet, 0x3 // Lockout interrupts + /* Save the system stack pointer. */ // _tx_thread_system_stack_ptr = (VOID_PTR) (sp); LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr MOV x1, sp // Pickup SP + SUB x1, x1, #15 // BIC x1, x1, #0xF // Get 16-bit alignment STR x1, [x0] // Store system stack /* Save the first available memory address. */ - /* _tx_initialize_unused_memory = (VOID_PTR) Image$$ZI$$Limit; */ + // _tx_initialize_unused_memory = (VOID_PTR) Image$$ZI$$Limit; LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr LDR x1, =zi_limit // Pickup unused memory address diff --git a/ports/cortex_a34/ac6/src/tx_thread_context_restore.S b/ports/cortex_a34/ac6/src/tx_thread_context_restore.S index 3870de0d..9ba82827 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a34/ac6/src/tx_thread_context_restore.S @@ -19,8 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 /**************************************************************************/ @@ -28,7 +29,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/ac6/src/tx_thread_context_save.S b/ports/cortex_a34/ac6/src/tx_thread_context_save.S index 8bc7e21b..c2395155 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a34/ac6/src/tx_thread_context_save.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a34/ac6/src/tx_thread_fp_disable.c index c69f6de5..25233f77 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a34/ac6/src/tx_thread_fp_disable.c @@ -15,18 +15,20 @@ /** */ /** ThreadX Component */ /** */ -/** Module Manager */ +/** Thread */ /** */ /**************************************************************************/ /**************************************************************************/ #define TX_SOURCE_CODE + +/* Include necessary system files. */ + #include "tx_api.h" #include "tx_thread.h" - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -35,7 +37,7 @@ /* 6.1.10 */ /* AUTHOR */ /* */ -/* Scott Larson, Microsoft Corporation */ +/* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -47,7 +49,7 @@ /* */ /* OUTPUT */ /* */ -/* status Completion status */ +/* None */ /* */ /* CALLS */ /* */ @@ -84,3 +86,4 @@ ULONG system_state; } } } + diff --git a/ports/cortex_a34/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a34/ac6/src/tx_thread_interrupt_control.S index d4235180..21ec2dd1 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a34/ac6/src/tx_thread_interrupt_control.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a34/ac6/src/tx_thread_interrupt_disable.S index 08f0e7e1..af2ef874 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a34/ac6/src/tx_thread_interrupt_disable.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a34/ac6/src/tx_thread_interrupt_restore.S index 69a859da..3e0780d0 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a34/ac6/src/tx_thread_interrupt_restore.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/ac6/src/tx_thread_schedule.S b/ports/cortex_a34/ac6/src/tx_thread_schedule.S index 4d3763eb..d15e7ded 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a34/ac6/src/tx_thread_schedule.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -217,4 +219,3 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } - diff --git a/ports/cortex_a34/ac6/src/tx_thread_stack_build.S b/ports/cortex_a34/ac6/src/tx_thread_stack_build.S index d1002b2c..01084da7 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a34/ac6/src/tx_thread_stack_build.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/ac6/src/tx_thread_system_return.S b/ports/cortex_a34/ac6/src/tx_thread_system_return.S index 112e1454..b7593d79 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a34/ac6/src/tx_thread_system_return.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/ac6/src/tx_timer_interrupt.S b/ports/cortex_a34/ac6/src/tx_timer_interrupt.S index ac61450b..1b80a7f2 100644 --- a/ports/cortex_a34/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a34/ac6/src/tx_timer_interrupt.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/gnu/CMakeLists.txt b/ports/cortex_a34/gnu/CMakeLists.txt new file mode 100644 index 00000000..972c10f1 --- /dev/null +++ b/ports/cortex_a34/gnu/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2026 Eclipse ThreadX contributors +# SPDX-License-Identifier: MIT +# Portions of this file were generated with AI assistance. +# +# ThreadX port sources for the AArch64 cores, GNU tools. +# Copied into every AArch64 gnu port by update.sh, so edit it here. + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_fp_disable.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_fp_enable.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + SYSTEM + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/cortex_a34/gnu/example_build/build_threadx.sh b/ports/cortex_a34/gnu/example_build/build_threadx.sh new file mode 100755 index 00000000..b3b2cd36 --- /dev/null +++ b/ports/cortex_a34/gnu/example_build/build_threadx.sh @@ -0,0 +1,87 @@ +#!/bin/bash +############################################################################## +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5). +# The AI-generated portions may be considered public domain (CC0-1.0) +# and not subject to the project's licence. The human contributor has +# reviewed and verified that the code is correct. +# +# SPDX-License-Identifier: MIT and CC0-1.0 +############################################################################## + +# Builds the ThreadX library, tx.a, for the AArch64 port this script sits in. +# The AArch64 examples previously had no build driver at all and could only be +# built through Arm Development Studio project files. +# +# ./build_threadx.sh +# TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx.sh +# +# The CPU is derived from the directory this script lives in, so one script +# serves every AArch64 port rather than needing one copy per core. + +set -eu + +cd "$(dirname "$(realpath "$0")")" + +# ports/<core>/gnu/example_build -> up two levels is <core> -> the -mcpu name. +# The same example tree is copied into the SMP ports, where the core directory +# carries an _smp suffix and the kernel sources live in common_smp. +core="$(basename "$(cd ../.. && pwd)")" +case "${core}" in + *_smp) cpu="${core%_smp}"; common="common_smp" ;; + *) cpu="${core}"; common="common" ;; +esac +cpu="${cpu//_/-}" + +: "${TOOLCHAIN:=gnu}" +case "${TOOLCHAIN}" in + gnu) + CC="aarch64-none-elf-gcc" + AR="aarch64-none-elf-ar" + TARGET_FLAGS="" + ;; + atfe) + CC="${ATFE_CLANG:-clang}" + case "${CC}" in + */*) AR="$(dirname "${CC}")/llvm-ar" ;; + *) AR="llvm-ar" ;; + esac + TARGET_FLAGS="--target=aarch64-none-elf" + ;; + *) + echo "Unknown TOOLCHAIN '${TOOLCHAIN}'; expected gnu or atfe" >&2 + exit 1 + ;; +esac + +CFLAGS="-g -mcpu=${cpu} -I../../../../${common}/inc -I../inc" + +echo "Building tx.a for ${cpu} with ${TOOLCHAIN}" + +rm -f tx.a ./*.o + +# Port sources. The SMP ports carry C sources here as well as assembly. +for src in ../src/*.S ../src/*.c; do + [ -f "${src}" ] || continue + obj="$(basename "${src}")" + "${CC}" ${TARGET_FLAGS} -c ${CFLAGS} "${src}" -o "${obj%.*}.o" +done + +# Common ThreadX sources. tx_misra.c is deliberately excluded: it is only for +# MISRA builds and has an assembly counterpart in the port. +for src in ../../../../${common}/src/*.c; do + case "$(basename "${src}")" in + tx_misra.c) continue ;; + esac + "${CC}" ${TARGET_FLAGS} -c ${CFLAGS} "${src}" -o "$(basename "${src%.c}").o" +done + +"${AR}" -rcs tx.a ./*.o +rm -f ./*.o + +echo "Done: $(basename "$(pwd)")/tx.a" diff --git a/ports/cortex_a34/gnu/example_build/build_threadx_sample.sh b/ports/cortex_a34/gnu/example_build/build_threadx_sample.sh new file mode 100755 index 00000000..94248a88 --- /dev/null +++ b/ports/cortex_a34/gnu/example_build/build_threadx_sample.sh @@ -0,0 +1,109 @@ +#!/bin/bash +############################################################################## +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5). +# The AI-generated portions may be considered public domain (CC0-1.0) +# and not subject to the project's licence. The human contributor has +# reviewed and verified that the code is correct. +# +# SPDX-License-Identifier: MIT and CC0-1.0 +############################################################################## + +# Builds the sample image for the AArch64 port this script sits in. Run +# build_threadx.sh first, which produces tx.a. +# +# ./build_threadx_sample.sh +# TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx_sample.sh +# +# The sample targets a fixed virtual platform: a GICv3 interrupt controller and +# an SP804 timer at the Base platform addresses. It is not expected to run on +# other models or on hardware without changing those addresses. + +set -eu + +cd "$(dirname "$(realpath "$0")")" + +core="$(basename "$(cd ../.. && pwd)")" +case "${core}" in + *_smp) cpu="${core%_smp}"; common="common_smp" ;; + *) cpu="${core}"; common="common" ;; +esac +cpu="${cpu//_/-}" + +: "${TOOLCHAIN:=gnu}" +case "${TOOLCHAIN}" in + gnu) + CC="aarch64-none-elf-gcc" + TARGET_FLAGS="" + # rdimon supplies the semihosting syscalls and, with them, the real + # initialise_monitor_handles that startup.S calls. + SYSCALL_LIB="--specs=rdimon.specs" + SEMIHOST_STUB="" + # crti.o defines _init and _fini; crtn.o closes them. The link below + # passes -nostartfiles, which is right for a port with its own reset + # path but also drops these two, and startup.S calls + # __libc_init_array, whose newlib implementation calls _init. Without + # them every AArch64 sample failed to link: + # + # libg.a(libc_a-init.o): in function `__libc_init_array': + # undefined reference to `_init' + # relocation truncated to fit: R_AARCH64_CALL26 against undefined + # symbol `_init' + # + # crti.o must precede every other .init contribution and crtn.o must + # follow all of them, which is why they bracket the object list rather + # than sitting with the other flags. The AArch32 scripts need none of + # this: they use nosys.specs and never reach __libc_init_array. + CRT_BEGIN="$("${CC}" -mcpu="${cpu}" -print-file-name=crti.o)" + CRT_END="$("${CC}" -mcpu="${cpu}" -print-file-name=crtn.o)" + ;; + atfe) + CC="${ATFE_CLANG:-clang}" + TARGET_FLAGS="--target=aarch64-none-elf" + SYSCALL_LIB="-lsemihost" + # picolibc has no initialise_monitor_handles, and neither does the + # toolchain's semihosting library, so the weak stub stands in for it. + SEMIHOST_STUB="sample_threadx/semihost_stub.S" + # Deliberately empty. picolibc's __libc_init_array does not call _init, + # so these images link today and adding crti.o would change a working + # link for no reason. + CRT_BEGIN="" + CRT_END="" + ;; + *) + echo "Unknown TOOLCHAIN '${TOOLCHAIN}'; expected gnu or atfe" >&2 + exit 1 + ;; +esac + +CFLAGS="-g -mcpu=${cpu} -I../../../../${common}/inc -I../inc -Isample_threadx" + +echo "Building the sample for ${cpu} with ${TOOLCHAIN}" + +objects="" +for src in sample_threadx/startup.S sample_threadx/vectors.S \ + sample_threadx/v8_aarch64.S sample_threadx/v8_utils.S \ + sample_threadx/MP_Mutexes.S ${SEMIHOST_STUB} \ + sample_threadx/GICv3_gicd.c sample_threadx/GICv3_gicr.c \ + sample_threadx/sp804_timer.c sample_threadx/timer_interrupts.c \ + sample_threadx/sample_threadx.c; do + [ -n "${src}" ] || continue + obj="$(basename "${src}")" + obj="${obj%.*}.o" + "${CC}" ${TARGET_FLAGS} -c ${CFLAGS} "${src}" -o "${obj}" + objects="${objects} ${obj}" +done + +"${CC}" ${TARGET_FLAGS} -g -mcpu="${cpu}" -nostartfiles \ + -T sample_threadx/sample_threadx.ld ${SYSCALL_LIB} \ + -o sample_threadx.out -Wl,-Map=sample_threadx.map \ + ${CRT_BEGIN} ${objects} tx.a ${CRT_END} + +rm -f ${objects} + +echo "Done: $(basename "$(pwd)")/sample_threadx.out" diff --git a/ports/cortex_a34/gnu/example_build/readme.md b/ports/cortex_a34/gnu/example_build/readme.md new file mode 100644 index 00000000..3c52a7da --- /dev/null +++ b/ports/cortex_a34/gnu/example_build/readme.md @@ -0,0 +1,39 @@ +# AArch64 GNU example build + +Builds the ThreadX library and a sample image for the AArch64 port this +directory belongs to. + +```sh +./build_threadx.sh # the ThreadX library, tx.a +./build_threadx_sample.sh # the sample image, sample_threadx.out +``` + +Set `TOOLCHAIN=atfe` to build with Arm Toolchain for Embedded, which is LLVM +based, instead of the GNU toolchain: + +```sh +TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx.sh +TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx_sample.sh +``` + +Both scripts derive the `-mcpu` value and the kernel source directory from the +port directory they sit in, so one pair of scripts serves every AArch64 port, +SMP included. Before they existed these examples could only be built through the +Arm Development Studio project files beside them, which is why the `.cproject` +and `.launch` files remain. + +## What the sample targets + +A fixed virtual platform: a GICv3 interrupt controller and an SP804 timer at the +Base platform addresses, as set up by `startup.S`, `vectors.S` and the GICv3 +sources here. It will not run on a model or board that places those peripherals +elsewhere without changing the addresses. + +## Semihosting + +`startup.S` calls `initialise_monitor_handles` to open the standard file handles +over a debugger connection. The GNU toolchain provides it in libgloss, pulled in +by `--specs=rdimon.specs`. picolibc, which Arm Toolchain for Embedded ships, has +no equivalent and neither does its semihosting library, so `semihost_stub.S` +supplies a weak no-op for that toolchain only. A real definition always wins +over it. diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a34/gnu/example_build/sample_threadx/.cproject index eae50159..40d4912d 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/.cproject @@ -131,78 +131,6 @@ </cconfiguration> - <cconfiguration id="com.arm.eclipse.build.config.v6.exe.release.base.262471578"> - - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.release.base.262471578" moduleId="org.eclipse.cdt.core.settings" name="Release"> - - <externalSettings/> - - <extensions> - - <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - - <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - - <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - - </extensions> - - </storageModule> - - <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - - <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.release.base.262471578" name="Release" parent="com.arm.eclipse.build.config.v6.exe.release.base"> - - <folderInfo id="com.arm.eclipse.build.config.v6.exe.release.base.262471578." name="/" resourcePath=""> - - <toolChain id="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6.2039978271" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6"> - - <targetPlatform id="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6.2039978271.1401365679" name=""/> - - <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx}/Release" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.152908166" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="com.arm.toolchain.v6.builder"/> - - <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2113724202" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6"> - - <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.1064912621" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/> - - <inputType id="com.arm.tool.c.compiler.v6.base.input.274442412" superClass="com.arm.tool.c.compiler.v6.base.input"/> - - </tool> - - <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.857388488" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6"> - - <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.703057645" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/> - - </tool> - - <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.494258017" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6"> - - <inputType id="com.arm.tool.assembler.v6.base.input.2016749997" superClass="com.arm.tool.assembler.v6.base.input"/> - - </tool> - - <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1332640632" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/> - - <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1069857726" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - - </toolChain> - - </folderInfo> - - <sourceEntries> - - <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - - </sourceEntries> - - </configuration> - - </storageModule> - - <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - - </cconfiguration> - </storageModule> <storageModule moduleId="cdtBuildSystem" version="4.0.0"> diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicr.c b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicr.c index 61addaef..26b5af8a 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicr.c +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicr.c @@ -293,7 +293,7 @@ void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group) uint32_t groupmod; /* - * get each bit of group config duplicated over all 32 bits + * get each bit of group config duplicated over all 32-bits */ groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); group = (uint32_t)(((int32_t)group << nbits) >> 31); diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.launch b/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.launch index dd70fe94..2c5a357d 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.launch +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.launch @@ -184,7 +184,7 @@ <booleanAttribute key="VFS_ENABLED" value="true"/> <stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/> <stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/> - <stringAttribute key="breakpoints" value="<?xml version="1.0" encoding="UTF-8"?> <breakpoints order="ALPHA"> 	<breakpoint ignorecount="0" threadenabled="no" core_list="" continue="no" verboseBreakpoints="yes" kind="SOURCEPOSITION"> 		<master_location index="0" enabled="true" version="2" address="EL3:0x0000000080000800" debugFile="C:/Users/nisohack/Documents/work/x-ware_libs/threadx/ports/cortex_a35/gnu/example_build/sample_threadx/vectors.S" hostFile="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\gnu\example_build\sample_threadx\vectors.S" line="27"/> 		<location index="0" enabled="true" version="2" address="EL3:0x0000000080000800" debugFile="C:/Users/nisohack/Documents/work/x-ware_libs/threadx/ports/cortex_a35/gnu/example_build/sample_threadx/vectors.S" hostFile="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\gnu\example_build\sample_threadx\vectors.S" line="27"/> 		<location index="1" enabled="true" version="2" address="EL1N:0x0000000080000800" debugFile="C:/Users/nisohack/Documents/work/x-ware_libs/threadx/ports/cortex_a35/gnu/example_build/sample_threadx/vectors.S" hostFile="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\gnu\example_build\sample_threadx\vectors.S" line="27"/> 	</breakpoint> </breakpoints> "/> + <stringAttribute key="breakpoints" value="<?xml version="1.0" encoding="UTF-8"?> <breakpoints order="ALPHA"> </breakpoints> "/> <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses"> <listEntry value="<Next Instruction>"/> <listEntry value=""/> @@ -239,7 +239,7 @@ <stringAttribute key="config_db_platform_name" value="Arm FVP (Installed with Arm DS) - Base_A34x1"/> <stringAttribute key="config_db_project_type" value="Bare Metal Debug"/> <stringAttribute key="config_db_project_type_id" value="BARE_METAL"/> - <stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/base_a35x1"/> + <stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/base_a34x1"/> <stringAttribute key="config_file" value="CDB://cadi_config.xml"/> <booleanAttribute key="connectOnly" value="false"/> <listAttribute key="debugger.view.DisassemblyView:current"> @@ -314,15 +314,10 @@ <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/> <booleanAttribute key="runAfterConnect" value="false"/> <stringAttribute key="runTargetInitializationScript" value="${workspace_loc:/sample_threadx/use_model_semihosting.ds}"/> - <mapAttribute key="scripts_view_script_links"> - <mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/> - <mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\gnu\example_build\sample_threadx\use_model_semihosting.ds" value=""/> - </mapAttribute> <listAttribute key="setup"> <listEntry value="CDB://Scripts/rtsm_launcher.py"/> <listEntry value=""FVP_Base_Cortex-A34x1""/> </listAttribute> <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/> - <stringAttribute key="substitutePath" value="<?xml version="1.0" encoding="UTF-8"?> <tuplelist> 	<tuple> 		<ta>C:\temp1702\tx\</ta> 		<tb>C:\temp1702\tx\</tb> 	</tuple> </tuplelist> "/> <stringAttribute key="watchpoints" value="<?xml version="1.0" encoding="UTF-8"?> <watchpoints> </watchpoints> "/> </launchConfiguration> diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/semihost_stub.S b/ports/cortex_a34/gnu/example_build/sample_threadx/semihost_stub.S new file mode 100644 index 00000000..c456875d --- /dev/null +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/semihost_stub.S @@ -0,0 +1,43 @@ +/*************************************************************************** + * Copyright (c) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ARMv8-A example semihosting stub */ +/** */ +/**************************************************************************/ + +/* startup.S calls initialise_monitor_handles to open the standard file handles + over a debugger connection. The GNU toolchain provides it in libgloss, which + --specs=rdimon.specs pulls in, so this file is linked only for the LLVM + toolchain: picolibc has no equivalent, and neither does the toolchain's own + semihosting library, so without it the sample does not link at all. + + The definition is weak, so a real one always wins if something provides it. + The sample writes nothing to the standard handles, so doing nothing here + costs it no output. */ + + .text + .balign 4 + + .weak initialise_monitor_handles + .type initialise_monitor_handles, %function +initialise_monitor_handles: + ret + .size initialise_monitor_handles, . - initialise_monitor_handles + + .end diff --git a/ports/cortex_a34/gnu/example_build/tx/.cproject b/ports/cortex_a34/gnu/example_build/tx/.cproject index 4d9d34ca..9e5a975e 100644 --- a/ports/cortex_a34/gnu/example_build/tx/.cproject +++ b/ports/cortex_a34/gnu/example_build/tx/.cproject @@ -39,7 +39,7 @@ <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1755052156" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf"> - <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.281590127" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="cortex-a34" valueType="string"/> + <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.281590127" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="" valueType="string"/> <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym.1254489229" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols"> @@ -58,6 +58,7 @@ </option> <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.379931340" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" value="gnu.c.optimization.level.none" valueType="enumerated"/> + <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch.590859224" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch" useByScannerDiscovery="false" value="armv8-a" valueType="string"/> <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.11119542" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/> @@ -71,7 +72,7 @@ <tool command="aarch64-elf-gcc.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.2113642977" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf"> - <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu.1603138513" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu" useByScannerDiscovery="false" value="cortex-a34" valueType="string"/> + <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu.1603138513" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu" useByScannerDiscovery="false" value="" valueType="string"/> <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym.1797095306" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols"> @@ -80,6 +81,7 @@ </option> <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.1075418381" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" useByScannerDiscovery="false" value="true" valueType="boolean"/> + <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch.590859224" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch" useByScannerDiscovery="false" value="armv8-a" valueType="string"/> <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.93700751" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/> @@ -123,78 +125,6 @@ </cconfiguration> - <cconfiguration id="com.arm.eclipse.build.config.v6.lib.release.base.979090268"> - - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.release.base.979090268" moduleId="org.eclipse.cdt.core.settings" name="Release"> - - <externalSettings/> - - <extensions> - - <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - - <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - - <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - - </extensions> - - </storageModule> - - <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - - <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.release.base.979090268" name="Release" parent="com.arm.eclipse.build.config.v6.lib.release.base"> - - <folderInfo id="com.arm.eclipse.build.config.v6.lib.release.base.979090268." name="/" resourcePath=""> - - <toolChain id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.423324903" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6"> - - <targetPlatform id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.423324903.1130606835" name=""/> - - <builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Release" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1266548138" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="com.arm.toolchain.v6.builder"/> - - <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1044032924" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6"> - - <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.297151373" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/> - - <inputType id="com.arm.tool.c.compiler.v6.base.input.1163793161" superClass="com.arm.tool.c.compiler.v6.base.input"/> - - </tool> - - <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.370619180" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6"> - - <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.570633086" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/> - - </tool> - - <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1018315840" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6"> - - <inputType id="com.arm.tool.assembler.v6.base.input.1395216260" superClass="com.arm.tool.assembler.v6.base.input"/> - - </tool> - - <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.273247708" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/> - - <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.904926956" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - - </toolChain> - - </folderInfo> - - <sourceEntries> - - <entry excluding="src_generic/tx_misra.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - - </sourceEntries> - - </configuration> - - </storageModule> - - <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - - </cconfiguration> - </storageModule> <storageModule moduleId="cdtBuildSystem" version="4.0.0"> diff --git a/ports/cortex_a34/gnu/inc/tx_port.h b/ports/cortex_a34/gnu/inc/tx_port.h index 4487de47..691fedd8 100644 --- a/ports/cortex_a34/gnu/inc/tx_port.h +++ b/ports/cortex_a34/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.2.202603 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a34/gnu/src/tx_initialize_low_level.S b/ports/cortex_a34/gnu/src/tx_initialize_low_level.S index aa3f04cd..f86568c5 100644 --- a/ports/cortex_a34/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a34/gnu/src/tx_initialize_low_level.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ /**************************************************************************/ @@ -30,10 +31,10 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ -/* Scott Larson, Microsoft Corporation */ +/* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -49,7 +50,7 @@ /* */ /* OUTPUT */ /* */ -/* status Completion status */ +/* None */ /* */ /* CALLS */ /* */ @@ -74,6 +75,7 @@ _tx_initialize_low_level: LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr MOV x1, sp // Pickup SP + SUB x1, x1, #15 // BIC x1, x1, #0xF // Get 16-bit alignment STR x1, [x0] // Store system stack @@ -82,7 +84,6 @@ _tx_initialize_low_level: LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr LDR x1, =__top_of_ram // Pickup unused memory address - LDR x1, [x1] // STR x1, [x0] // Store unused memory address /* Done, return to caller. */ diff --git a/ports/cortex_a34/gnu/src/tx_thread_context_restore.S b/ports/cortex_a34/gnu/src/tx_thread_context_restore.S index 54ebca65..9ba82827 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a34/gnu/src/tx_thread_context_restore.S @@ -22,8 +22,6 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE #include "tx_user.h" #endif - - .text .align 3 /**************************************************************************/ @@ -31,7 +29,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/gnu/src/tx_thread_context_save.S b/ports/cortex_a34/gnu/src/tx_thread_context_save.S index ae416079..c2395155 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a34/gnu/src/tx_thread_context_save.S @@ -23,7 +23,6 @@ #include "tx_user.h" #endif - .text .align 3 /**************************************************************************/ @@ -31,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S index 465e7bb1..21ec2dd1 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S @@ -23,7 +23,6 @@ #include "tx_user.h" #endif - .text .align 3 /**************************************************************************/ @@ -31,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S index f2d30435..af2ef874 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S @@ -23,7 +23,6 @@ #include "tx_user.h" #endif - .text .align 3 /**************************************************************************/ @@ -31,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S index 9f703456..3e0780d0 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S @@ -23,7 +23,6 @@ #include "tx_user.h" #endif - .text .align 3 /**************************************************************************/ @@ -31,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/gnu/src/tx_thread_schedule.S b/ports/cortex_a34/gnu/src/tx_thread_schedule.S index 3d9d215c..d15e7ded 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a34/gnu/src/tx_thread_schedule.S @@ -23,7 +23,6 @@ #include "tx_user.h" #endif - .text .align 3 /**************************************************************************/ @@ -31,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -220,4 +219,3 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } - diff --git a/ports/cortex_a34/gnu/src/tx_thread_stack_build.S b/ports/cortex_a34/gnu/src/tx_thread_stack_build.S index 116a2a3c..01084da7 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a34/gnu/src/tx_thread_stack_build.S @@ -23,7 +23,6 @@ #include "tx_user.h" #endif - .text .align 3 /**************************************************************************/ @@ -31,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/gnu/src/tx_thread_system_return.S b/ports/cortex_a34/gnu/src/tx_thread_system_return.S index 0db113d5..b7593d79 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a34/gnu/src/tx_thread_system_return.S @@ -23,7 +23,6 @@ #include "tx_user.h" #endif - .text .align 3 /**************************************************************************/ @@ -31,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ diff --git a/ports/cortex_a34/gnu/src/tx_timer_interrupt.S b/ports/cortex_a34/gnu/src/tx_timer_interrupt.S index 2e6c8f8f..1b80a7f2 100644 --- a/ports/cortex_a34/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a34/gnu/src/tx_timer_interrupt.S @@ -23,7 +23,6 @@ #include "tx_user.h" #endif - .text .align 3 /**************************************************************************/ @@ -31,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv8-A */ -/* 6.1.10 */ +/* 6.3.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ |