diff options
Diffstat (limited to 'ports/cortex_a72/gnu')
9 files changed, 312 insertions, 10 deletions
diff --git a/ports/cortex_a72/gnu/CMakeLists.txt b/ports/cortex_a72/gnu/CMakeLists.txt new file mode 100644 index 00000000..972c10f1 --- /dev/null +++ b/ports/cortex_a72/gnu/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2026 Eclipse ThreadX contributors +# SPDX-License-Identifier: MIT +# Portions of this file were generated with AI assistance. +# +# ThreadX port sources for the AArch64 cores, GNU tools. +# Copied into every AArch64 gnu port by update.sh, so edit it here. + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_fp_disable.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_fp_enable.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + SYSTEM + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/cortex_a72/gnu/example_build/build_threadx.sh b/ports/cortex_a72/gnu/example_build/build_threadx.sh new file mode 100755 index 00000000..b3b2cd36 --- /dev/null +++ b/ports/cortex_a72/gnu/example_build/build_threadx.sh @@ -0,0 +1,87 @@ +#!/bin/bash +############################################################################## +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5). +# The AI-generated portions may be considered public domain (CC0-1.0) +# and not subject to the project's licence. The human contributor has +# reviewed and verified that the code is correct. +# +# SPDX-License-Identifier: MIT and CC0-1.0 +############################################################################## + +# Builds the ThreadX library, tx.a, for the AArch64 port this script sits in. +# The AArch64 examples previously had no build driver at all and could only be +# built through Arm Development Studio project files. +# +# ./build_threadx.sh +# TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx.sh +# +# The CPU is derived from the directory this script lives in, so one script +# serves every AArch64 port rather than needing one copy per core. + +set -eu + +cd "$(dirname "$(realpath "$0")")" + +# ports/<core>/gnu/example_build -> up two levels is <core> -> the -mcpu name. +# The same example tree is copied into the SMP ports, where the core directory +# carries an _smp suffix and the kernel sources live in common_smp. +core="$(basename "$(cd ../.. && pwd)")" +case "${core}" in + *_smp) cpu="${core%_smp}"; common="common_smp" ;; + *) cpu="${core}"; common="common" ;; +esac +cpu="${cpu//_/-}" + +: "${TOOLCHAIN:=gnu}" +case "${TOOLCHAIN}" in + gnu) + CC="aarch64-none-elf-gcc" + AR="aarch64-none-elf-ar" + TARGET_FLAGS="" + ;; + atfe) + CC="${ATFE_CLANG:-clang}" + case "${CC}" in + */*) AR="$(dirname "${CC}")/llvm-ar" ;; + *) AR="llvm-ar" ;; + esac + TARGET_FLAGS="--target=aarch64-none-elf" + ;; + *) + echo "Unknown TOOLCHAIN '${TOOLCHAIN}'; expected gnu or atfe" >&2 + exit 1 + ;; +esac + +CFLAGS="-g -mcpu=${cpu} -I../../../../${common}/inc -I../inc" + +echo "Building tx.a for ${cpu} with ${TOOLCHAIN}" + +rm -f tx.a ./*.o + +# Port sources. The SMP ports carry C sources here as well as assembly. +for src in ../src/*.S ../src/*.c; do + [ -f "${src}" ] || continue + obj="$(basename "${src}")" + "${CC}" ${TARGET_FLAGS} -c ${CFLAGS} "${src}" -o "${obj%.*}.o" +done + +# Common ThreadX sources. tx_misra.c is deliberately excluded: it is only for +# MISRA builds and has an assembly counterpart in the port. +for src in ../../../../${common}/src/*.c; do + case "$(basename "${src}")" in + tx_misra.c) continue ;; + esac + "${CC}" ${TARGET_FLAGS} -c ${CFLAGS} "${src}" -o "$(basename "${src%.c}").o" +done + +"${AR}" -rcs tx.a ./*.o +rm -f ./*.o + +echo "Done: $(basename "$(pwd)")/tx.a" diff --git a/ports/cortex_a72/gnu/example_build/build_threadx_sample.sh b/ports/cortex_a72/gnu/example_build/build_threadx_sample.sh new file mode 100755 index 00000000..94248a88 --- /dev/null +++ b/ports/cortex_a72/gnu/example_build/build_threadx_sample.sh @@ -0,0 +1,109 @@ +#!/bin/bash +############################################################################## +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5). +# The AI-generated portions may be considered public domain (CC0-1.0) +# and not subject to the project's licence. The human contributor has +# reviewed and verified that the code is correct. +# +# SPDX-License-Identifier: MIT and CC0-1.0 +############################################################################## + +# Builds the sample image for the AArch64 port this script sits in. Run +# build_threadx.sh first, which produces tx.a. +# +# ./build_threadx_sample.sh +# TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx_sample.sh +# +# The sample targets a fixed virtual platform: a GICv3 interrupt controller and +# an SP804 timer at the Base platform addresses. It is not expected to run on +# other models or on hardware without changing those addresses. + +set -eu + +cd "$(dirname "$(realpath "$0")")" + +core="$(basename "$(cd ../.. && pwd)")" +case "${core}" in + *_smp) cpu="${core%_smp}"; common="common_smp" ;; + *) cpu="${core}"; common="common" ;; +esac +cpu="${cpu//_/-}" + +: "${TOOLCHAIN:=gnu}" +case "${TOOLCHAIN}" in + gnu) + CC="aarch64-none-elf-gcc" + TARGET_FLAGS="" + # rdimon supplies the semihosting syscalls and, with them, the real + # initialise_monitor_handles that startup.S calls. + SYSCALL_LIB="--specs=rdimon.specs" + SEMIHOST_STUB="" + # crti.o defines _init and _fini; crtn.o closes them. The link below + # passes -nostartfiles, which is right for a port with its own reset + # path but also drops these two, and startup.S calls + # __libc_init_array, whose newlib implementation calls _init. Without + # them every AArch64 sample failed to link: + # + # libg.a(libc_a-init.o): in function `__libc_init_array': + # undefined reference to `_init' + # relocation truncated to fit: R_AARCH64_CALL26 against undefined + # symbol `_init' + # + # crti.o must precede every other .init contribution and crtn.o must + # follow all of them, which is why they bracket the object list rather + # than sitting with the other flags. The AArch32 scripts need none of + # this: they use nosys.specs and never reach __libc_init_array. + CRT_BEGIN="$("${CC}" -mcpu="${cpu}" -print-file-name=crti.o)" + CRT_END="$("${CC}" -mcpu="${cpu}" -print-file-name=crtn.o)" + ;; + atfe) + CC="${ATFE_CLANG:-clang}" + TARGET_FLAGS="--target=aarch64-none-elf" + SYSCALL_LIB="-lsemihost" + # picolibc has no initialise_monitor_handles, and neither does the + # toolchain's semihosting library, so the weak stub stands in for it. + SEMIHOST_STUB="sample_threadx/semihost_stub.S" + # Deliberately empty. picolibc's __libc_init_array does not call _init, + # so these images link today and adding crti.o would change a working + # link for no reason. + CRT_BEGIN="" + CRT_END="" + ;; + *) + echo "Unknown TOOLCHAIN '${TOOLCHAIN}'; expected gnu or atfe" >&2 + exit 1 + ;; +esac + +CFLAGS="-g -mcpu=${cpu} -I../../../../${common}/inc -I../inc -Isample_threadx" + +echo "Building the sample for ${cpu} with ${TOOLCHAIN}" + +objects="" +for src in sample_threadx/startup.S sample_threadx/vectors.S \ + sample_threadx/v8_aarch64.S sample_threadx/v8_utils.S \ + sample_threadx/MP_Mutexes.S ${SEMIHOST_STUB} \ + sample_threadx/GICv3_gicd.c sample_threadx/GICv3_gicr.c \ + sample_threadx/sp804_timer.c sample_threadx/timer_interrupts.c \ + sample_threadx/sample_threadx.c; do + [ -n "${src}" ] || continue + obj="$(basename "${src}")" + obj="${obj%.*}.o" + "${CC}" ${TARGET_FLAGS} -c ${CFLAGS} "${src}" -o "${obj}" + objects="${objects} ${obj}" +done + +"${CC}" ${TARGET_FLAGS} -g -mcpu="${cpu}" -nostartfiles \ + -T sample_threadx/sample_threadx.ld ${SYSCALL_LIB} \ + -o sample_threadx.out -Wl,-Map=sample_threadx.map \ + ${CRT_BEGIN} ${objects} tx.a ${CRT_END} + +rm -f ${objects} + +echo "Done: $(basename "$(pwd)")/sample_threadx.out" diff --git a/ports/cortex_a72/gnu/example_build/readme.md b/ports/cortex_a72/gnu/example_build/readme.md new file mode 100644 index 00000000..3c52a7da --- /dev/null +++ b/ports/cortex_a72/gnu/example_build/readme.md @@ -0,0 +1,39 @@ +# AArch64 GNU example build + +Builds the ThreadX library and a sample image for the AArch64 port this +directory belongs to. + +```sh +./build_threadx.sh # the ThreadX library, tx.a +./build_threadx_sample.sh # the sample image, sample_threadx.out +``` + +Set `TOOLCHAIN=atfe` to build with Arm Toolchain for Embedded, which is LLVM +based, instead of the GNU toolchain: + +```sh +TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx.sh +TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx_sample.sh +``` + +Both scripts derive the `-mcpu` value and the kernel source directory from the +port directory they sit in, so one pair of scripts serves every AArch64 port, +SMP included. Before they existed these examples could only be built through the +Arm Development Studio project files beside them, which is why the `.cproject` +and `.launch` files remain. + +## What the sample targets + +A fixed virtual platform: a GICv3 interrupt controller and an SP804 timer at the +Base platform addresses, as set up by `startup.S`, `vectors.S` and the GICv3 +sources here. It will not run on a model or board that places those peripherals +elsewhere without changing the addresses. + +## Semihosting + +`startup.S` calls `initialise_monitor_handles` to open the standard file handles +over a debugger connection. The GNU toolchain provides it in libgloss, pulled in +by `--specs=rdimon.specs`. picolibc, which Arm Toolchain for Embedded ships, has +no equivalent and neither does its semihosting library, so `semihost_stub.S` +supplies a weak no-op for that toolchain only. A real definition always wins +over it. diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.launch b/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.launch index 2b75e0ee..89ab7146 100644 --- a/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.launch +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.launch @@ -184,7 +184,7 @@ <booleanAttribute key="VFS_ENABLED" value="true"/> <stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/> <stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/> - <stringAttribute key="breakpoints" value="<?xml version="1.0" encoding="UTF-8"?> <breakpoints order="ALPHA"> 	<breakpoint ignorecount="0" threadenabled="no" core_list="" continue="no" verboseBreakpoints="yes" kind="SOURCEPOSITION"> 		<master_location index="0" enabled="true" version="2" address="EL3:0x0000000080000800" debugFile="C:/Users/nisohack/Documents/work/x-ware_libs/threadx/ports/cortex_a35/gnu/example_build/sample_threadx/vectors.S" hostFile="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\gnu\example_build\sample_threadx\vectors.S" line="27"/> 		<location index="0" enabled="true" version="2" address="EL3:0x0000000080000800" debugFile="C:/Users/nisohack/Documents/work/x-ware_libs/threadx/ports/cortex_a35/gnu/example_build/sample_threadx/vectors.S" hostFile="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\gnu\example_build\sample_threadx\vectors.S" line="27"/> 		<location index="1" enabled="true" version="2" address="EL1N:0x0000000080000800" debugFile="C:/Users/nisohack/Documents/work/x-ware_libs/threadx/ports/cortex_a35/gnu/example_build/sample_threadx/vectors.S" hostFile="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\gnu\example_build\sample_threadx\vectors.S" line="27"/> 	</breakpoint> </breakpoints> "/> + <stringAttribute key="breakpoints" value="<?xml version="1.0" encoding="UTF-8"?> <breakpoints order="ALPHA"> </breakpoints> "/> <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses"> <listEntry value="<Next Instruction>"/> <listEntry value=""/> @@ -239,7 +239,7 @@ <stringAttribute key="config_db_platform_name" value="Arm FVP (Installed with Arm DS) - Base_A72x1"/> <stringAttribute key="config_db_project_type" value="Bare Metal Debug"/> <stringAttribute key="config_db_project_type_id" value="BARE_METAL"/> - <stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/base_a35x1"/> + <stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/base_a72x1"/> <stringAttribute key="config_file" value="CDB://cadi_config.xml"/> <booleanAttribute key="connectOnly" value="false"/> <listAttribute key="debugger.view.DisassemblyView:current"> @@ -314,15 +314,10 @@ <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/> <booleanAttribute key="runAfterConnect" value="false"/> <stringAttribute key="runTargetInitializationScript" value="${workspace_loc:/sample_threadx/use_model_semihosting.ds}"/> - <mapAttribute key="scripts_view_script_links"> - <mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/> - <mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a35\gnu\example_build\sample_threadx\use_model_semihosting.ds" value=""/> - </mapAttribute> <listAttribute key="setup"> <listEntry value="CDB://Scripts/rtsm_launcher.py"/> <listEntry value=""FVP_Base_Cortex-A72x1""/> </listAttribute> <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/> - <stringAttribute key="substitutePath" value="<?xml version="1.0" encoding="UTF-8"?> <tuplelist> 	<tuple> 		<ta>C:\temp1702\tx\</ta> 		<tb>C:\temp1702\tx\</tb> 	</tuple> </tuplelist> "/> <stringAttribute key="watchpoints" value="<?xml version="1.0" encoding="UTF-8"?> <watchpoints> </watchpoints> "/> </launchConfiguration> diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/semihost_stub.S b/ports/cortex_a72/gnu/example_build/sample_threadx/semihost_stub.S new file mode 100644 index 00000000..c456875d --- /dev/null +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/semihost_stub.S @@ -0,0 +1,43 @@ +/*************************************************************************** + * Copyright (c) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ARMv8-A example semihosting stub */ +/** */ +/**************************************************************************/ + +/* startup.S calls initialise_monitor_handles to open the standard file handles + over a debugger connection. The GNU toolchain provides it in libgloss, which + --specs=rdimon.specs pulls in, so this file is linked only for the LLVM + toolchain: picolibc has no equivalent, and neither does the toolchain's own + semihosting library, so without it the sample does not link at all. + + The definition is weak, so a real one always wins if something provides it. + The sample writes nothing to the standard handles, so doing nothing here + costs it no output. */ + + .text + .balign 4 + + .weak initialise_monitor_handles + .type initialise_monitor_handles, %function +initialise_monitor_handles: + ret + .size initialise_monitor_handles, . - initialise_monitor_handles + + .end diff --git a/ports/cortex_a72/gnu/inc/tx_port.h b/ports/cortex_a72/gnu/inc/tx_port.h index 4487de47..691fedd8 100644 --- a/ports/cortex_a72/gnu/inc/tx_port.h +++ b/ports/cortex_a72/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.2.202603 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a72/gnu/src/tx_initialize_low_level.S b/ports/cortex_a72/gnu/src/tx_initialize_low_level.S index 3025f12b..f86568c5 100644 --- a/ports/cortex_a72/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a72/gnu/src/tx_initialize_low_level.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ /**************************************************************************/ @@ -83,7 +84,6 @@ _tx_initialize_low_level: LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr LDR x1, =__top_of_ram // Pickup unused memory address - LDR x1, [x1] // STR x1, [x0] // Store unused memory address /* Done, return to caller. */ diff --git a/ports/cortex_a72/gnu/src/tx_thread_schedule.S b/ports/cortex_a72/gnu/src/tx_thread_schedule.S index 057aa538..d15e7ded 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a72/gnu/src/tx_thread_schedule.S @@ -219,4 +219,3 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } - |