diff options
Diffstat (limited to 'ports/cortex_m0')
26 files changed, 417 insertions, 3255 deletions
diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s index 3a585477..8f2cbaf1 100644 --- a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -20,7 +22,6 @@ ;/**************************************************************************/ ; ; - IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory IMPORT _tx_timer_interrupt IMPORT __main @@ -137,12 +138,6 @@ _tx_initialize_low_level ADDS r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000ED08 ; Build address of NVIC registers - LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register @@ -151,21 +146,6 @@ _tx_initialize_low_level ; ORRS r1, r1, r2 ; Set the CYCCNTENA bit ; STR r1, [r0] ; Enable the cycle count register ; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD08 ; Offset to vector base register - ADD r0, r0, r2 ; Build vector base register - LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__tx_vectors ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers diff --git a/ports/cortex_m0/ac5/inc/tx_port.h b/ports/cortex_m0/ac5/inc/tx_port.h index 5ddf74bb..53018a6f 100644 --- a/ports/cortex_m0/ac5/inc/tx_port.h +++ b/ports/cortex_m0/ac5/inc/tx_port.h @@ -312,7 +312,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S index f7e3eb2d..a3da17f7 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -7,6 +8,7 @@ @ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ +@ Portions of this file were generated with AI assistance. @ @ @/**************************************************************************/ @@ -20,7 +22,6 @@ @/**************************************************************************/ @ @ - .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory .global _tx_thread_context_save .global _tx_thread_context_restore @@ -93,24 +94,12 @@ _tx_initialize_low_level: @ ORRS r1, r1, r2 @ Set the CYCCNTENA bit @ STR r1, [r0] @ Enable the cycle count register @ -@ /* Setup Vector Table Offset Register. */ -@ - LDR r0, =0xE000E000 @ Build address of NVIC registers - LDR r2, =0xD08 @ Offset to vector base register - ADD r0, r0, r2 @ Build vector base register - LDR r1, =vector_table @ Pickup address of vector table - STR r1, [r0] @ Set vector table address -@ -@ /* Set system stack pointer from vector value. */ -@ - LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer - LDR r1, =vector_table @ Pickup address of vector table - LDR r1, [r1] @ Pickup reset stack pointer - STR r1, [r0] @ Save system stack pointer -@ @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ LDR r0, =0xE000E000 @ Build address of NVIC registers + LDR r1, =0 @ Build value for SysTick reset + STR r1, [r0, #0x10] @ Reset SysTick Control + STR r1, [r0, #0x18] @ Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] @ Setup SysTick Reload Value LDR r1, =0x7 @ Build SysTick Control Enable Value diff --git a/ports/cortex_m0/ac6/inc/tx_port.h b/ports/cortex_m0/ac6/inc/tx_port.h index 006c7e48..8b02e6e3 100644 --- a/ports/cortex_m0/ac6/inc/tx_port.h +++ b/ports/cortex_m0/ac6/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -322,11 +324,13 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb sy \n isb sy " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); + __asm__ volatile ("isb sy " : : : "memory"); } } @@ -355,7 +359,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC6 Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC6 Version 6.5.2.202603 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/ac6/src/tx_thread_system_return.S b/ports/cortex_m0/ac6/src/tx_thread_system_return.S index fc62c0c6..bd7a23f3 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m0/ac6/src/tx_thread_system_return.S @@ -72,12 +72,15 @@ _tx_thread_system_return: LDR r0, =0x10000000 @ Load PENDSVSET bit LDR r1, =0xE000ED04 @ Load NVIC base STR r0, [r1] @ Set PENDSVBIT in ICSR + DSB #0xF @ Ensure memory access is complete + ISB #0xF @ Flush pipeline MRS r0, IPSR @ Pickup IPSR CMP r0, #0 @ Is it a thread returning? BNE _isr_context @ If ISR, skip interrupt enable MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture + ISB #0xF @ Flush pipeline _isr_context: BX lr @ Return to caller @/* } */ diff --git a/ports/cortex_m0/gnu/CMakeLists.txt b/ports/cortex_m0/gnu/CMakeLists.txt index 0e3cc8ec..3c318e65 100755 --- a/ports/cortex_m0/gnu/CMakeLists.txt +++ b/ports/cortex_m0/gnu/CMakeLists.txt @@ -16,6 +16,7 @@ target_sources(${PROJECT_NAME} ) target_include_directories(${PROJECT_NAME} + SYSTEM PUBLIC ${CMAKE_CURRENT_LIST_DIR}/inc ) diff --git a/ports/cortex_m0/gnu/example_build/build_threadx.sh b/ports/cortex_m0/gnu/example_build/build_threadx.sh index dc34a9ae..3ef03845 100755 --- a/ports/cortex_m0/gnu/example_build/build_threadx.sh +++ b/ports/cortex_m0/gnu/example_build/build_threadx.sh @@ -10,6 +10,7 @@ # SPDX-License-Identifier: MIT # # AI Disclosure: This file was largely AI-generated by Copilot (Claude Sonnet 4.6). +# Portions of this file were generated with AI assistance. # The AI-generated portions may be considered public domain (CC0-1.0) # and not subject to the project's licence. The human contributor has # reviewed and verified that the code is correct. @@ -20,231 +21,267 @@ set -e cd "$(dirname "$0")" +# Toolchain selection. The default is the GNU toolchain, so an existing +# invocation of this script behaves exactly as before. Set TOOLCHAIN=atfe to +# build with Arm Toolchain for Embedded, which is LLVM based and is the +# successor to Arm Compiler 6: +# +# TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx.sh +# +: "${TOOLCHAIN:=gnu}" +case "${TOOLCHAIN}" in + gnu) + CC="arm-none-eabi-gcc" + AR="arm-none-eabi-ar" + TARGET_FLAGS="" + ENTRY_FLAG="-ereset_handler" + SYSCALL_LIB="--specs=nosys.specs" + ;; + atfe) + CC="${ATFE_CLANG:-clang}" + # llvm-ar ships beside clang in the toolchain. + case "${CC}" in + */*) AR="$(dirname "${CC}")/llvm-ar" ;; + *) AR="llvm-ar" ;; + esac + TARGET_FLAGS="--target=arm-none-eabi" + ENTRY_FLAG="-Wl,--entry=reset_handler" + # picolibc leaves _exit to the application; the toolchain's own + # semihosting library supplies it, which suits an example that runs on + # a model. + SYSCALL_LIB="-lsemihost" + ;; + *) + echo "Unknown TOOLCHAIN '${TOOLCHAIN}'; expected gnu or atfe" >&2 + exit 1 + ;; +esac + rm -f tx.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_stack_build.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_schedule.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_system_return.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_context_save.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_context_restore.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_interrupt_control.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_timer_interrupt.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_stack_build.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_schedule.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_system_return.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_context_save.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_context_restore.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_interrupt_control.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb ../src/tx_timer_interrupt.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc 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-I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc 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../../../../common/src/tx_initialize_kernel_setup.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +"${CC}" ${TARGET_FLAGS} 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-I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c 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-I../inc ../../../../common/src/txe_byte_release.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +"${CC}" ${TARGET_FLAGS} -c -g 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../../../../common/src/txe_semaphore_ceiling_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c -arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o -arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o -arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o -arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o -arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o -arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o -arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o -arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o -arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o -arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o -arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o -arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o -arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o -arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o -arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o -arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o -arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o -arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o -arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o -arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o -arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o -arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o -arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o -arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o -arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o -arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o -arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o -arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o -arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o -arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o -arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o -arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o -arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o -arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o +"${AR}" -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +"${AR}" -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +"${AR}" -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +"${AR}" -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +"${AR}" -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +"${AR}" -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +"${AR}" -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +"${AR}" -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +"${AR}" -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +"${AR}" -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +"${AR}" -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +"${AR}" -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +"${AR}" -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +"${AR}" -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +"${AR}" -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +"${AR}" -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +"${AR}" -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +"${AR}" -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +"${AR}" -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +"${AR}" -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +"${AR}" -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +"${AR}" -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +"${AR}" -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +"${AR}" -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +"${AR}" -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +"${AR}" -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +"${AR}" -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +"${AR}" -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +"${AR}" -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +"${AR}" -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +"${AR}" -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +"${AR}" -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +"${AR}" -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +"${AR}" -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_m0/gnu/example_build/build_threadx_sample.sh b/ports/cortex_m0/gnu/example_build/build_threadx_sample.sh index 9c6d89b1..772813df 100755 --- a/ports/cortex_m0/gnu/example_build/build_threadx_sample.sh +++ b/ports/cortex_m0/gnu/example_build/build_threadx_sample.sh @@ -10,6 +10,7 @@ # SPDX-License-Identifier: MIT # # AI Disclosure: This file was largely AI-generated by Copilot (Claude Sonnet 4.6). +# Portions of this file were generated with AI assistance. # The AI-generated portions may be considered public domain (CC0-1.0) # and not subject to the project's licence. The human contributor has # reviewed and verified that the code is correct. @@ -20,8 +21,44 @@ set -e cd "$(dirname "$0")" -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb cortexm0_vectors.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb cortexm0_crt0.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb tx_initialize_low_level.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc sample_threadx.c -arm-none-eabi-gcc -g -mcpu=cortex-m0 -mthumb -T sample_threadx.ld -ereset_handler -nostartfiles -o sample_threadx.out -Wl,-Map=sample_threadx.map cortexm0_vectors.o cortexm0_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a +# Toolchain selection. The default is the GNU toolchain, so an existing +# invocation of this script behaves exactly as before. Set TOOLCHAIN=atfe to +# build with Arm Toolchain for Embedded, which is LLVM based and is the +# successor to Arm Compiler 6: +# +# TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx_sample.sh +# +: "${TOOLCHAIN:=gnu}" +case "${TOOLCHAIN}" in + gnu) + CC="arm-none-eabi-gcc" + AR="arm-none-eabi-ar" + TARGET_FLAGS="" + ENTRY_FLAG="-ereset_handler" + SYSCALL_LIB="--specs=nosys.specs" + ;; + atfe) + CC="${ATFE_CLANG:-clang}" + # llvm-ar ships beside clang in the toolchain. + case "${CC}" in + */*) AR="$(dirname "${CC}")/llvm-ar" ;; + *) AR="llvm-ar" ;; + esac + TARGET_FLAGS="--target=arm-none-eabi" + ENTRY_FLAG="-Wl,--entry=reset_handler" + # picolibc leaves _exit to the application; the toolchain's own + # semihosting library supplies it, which suits an example that runs on + # a model. + SYSCALL_LIB="-lsemihost" + ;; + *) + echo "Unknown TOOLCHAIN '${TOOLCHAIN}'; expected gnu or atfe" >&2 + exit 1 + ;; +esac + +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb cortexm0_vectors.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb cortexm0_crt0.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb tx_initialize_low_level.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc sample_threadx.c +"${CC}" ${TARGET_FLAGS} -g -mcpu=cortex-m0 -mthumb -T sample_threadx.ld ${ENTRY_FLAG} -nostartfiles -o sample_threadx.out -Wl,-Map=sample_threadx.map cortexm0_vectors.o cortexm0_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a diff --git a/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S index 070871a3..8138ef97 100644 --- a/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S +++ b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S @@ -4,6 +4,12 @@ .section .init, "ax" .code 16 + /* Unified assembler syntax. Without it GNU as falls back to the legacy + divided syntax, in which a plain add or sub sets the flags implicitly. + LLVM implements only unified syntax, where ARMv6-M has no + flag-preserving encoding, so the S-forms below are required. Declaring + the mode makes both assemblers agree. */ + .syntax unified .align 2 .thumb_func @@ -43,16 +49,16 @@ _start: /* Zero bss. */ ldr r0, =__bss_start__ ldr r1, =__bss_end__ - mov r2, #0 + movs r2, #0 bl crt0_memory_set /* Setup heap - not recommended for Threadx but here for compatibility reasons */ ldr r0, = __heap_start__ ldr r1, = __heap_end__ - sub r1, r1, r0 - mov r2, #0 + subs r1, r1, r0 + movs r2, #0 str r2, [r0] - add r0, r0, #4 + adds r0, r0, #4 str r1, [r0] /* constructors in case of using C++ */ @@ -62,7 +68,7 @@ crt0_ctor_loop: cmp r0, r1 beq crt0_ctor_end ldr r2, [r0] - add r0, #4 + adds r0, #4 push {r0-r1} blx r2 pop {r0-r1} @@ -70,14 +76,14 @@ crt0_ctor_loop: crt0_ctor_end: /* Setup call frame for main() */ - mov r0, #0 + movs r0, #0 mov lr, r0 mov r12, sp start: /* Jump to main() */ - mov r0, #0 - mov r1, #0 + movs r0, #0 + movs r1, #0 ldr r2, =main blx r2 /* when main returns, loop forever. */ @@ -91,14 +97,14 @@ crt0_exit_loop: crt0_memory_copy: cmp r0, r1 beq memory_copy_done - sub r2, r2, r1 + subs r2, r2, r1 beq memory_copy_done memory_copy_loop: ldrb r3, [r0] - add r0, r0, #1 + adds r0, r0, #1 strb r3, [r1] - add r1, r1, #1 - sub r2, r2, #1 + adds r1, r1, #1 + subs r2, r2, #1 bne memory_copy_loop memory_copy_done: bx lr @@ -107,7 +113,7 @@ crt0_memory_set: cmp r0, r1 beq memory_set_done strb r2, [r0] - add r0, r0, #1 + adds r0, r0, #1 b crt0_memory_set memory_set_done: bx lr diff --git a/ports/cortex_m0/gnu/example_build/sample_threadx.ld b/ports/cortex_m0/gnu/example_build/sample_threadx.ld index 3f19c29e..d2da5859 100644 --- a/ports/cortex_m0/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_m0/gnu/example_build/sample_threadx.ld @@ -17,6 +17,8 @@ SECTIONS .text : { + __text_start__ = .; + *(.text*) KEEP(*(.init)) @@ -26,6 +28,7 @@ SECTIONS *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + __ctors_load_start__ = .; __ctors_start__ = ALIGN(4); *(SORT(.ctors.*)) *(.ctors) @@ -35,16 +38,41 @@ SECTIONS *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + __dtors_load_start__ = .; __dtors_start__ = ALIGN(4); *(SORT(.dtors.*)) *(.dtors) __dtors_end__ = ALIGN(4); + KEEP(*(.eh_frame*)) + + __text_end__ = ALIGN(4); + } > FLASH + + __text_load_start__ = LOADADDR(.text); + + .rodata : + { + __rodata_start__ = .; + *(.rodata*) - KEEP(*(.eh_frame*)) + __rodata_end__ = ALIGN(4); } > FLASH + __rodata_load_start__ = LOADADDR(.rodata); + + /* Fast section: for time-critical code/data to be copied from FLASH to RAM at startup. + No .fast content in this sample; symbols defined so crt0 startup copy is a no-op. */ + .fast (NOLOAD) : + { + __fast_start__ = .; + *(.fast*) + __fast_end__ = .; + } > RAM + + __fast_load_start__ = __fast_start__; + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) diff --git a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S index 36738f3d..3c630709 100644 --- a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -7,6 +8,7 @@ @ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ +@ Portions of this file were generated with AI assistance. @ @ @/**************************************************************************/ @@ -30,13 +32,11 @@ @#include "tx_timer.h" @ @ - .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory .global __RAM_segment_used_end__ .global _tx_thread_context_save .global _tx_thread_context_restore .global _tx_timer_interrupt - .global _vectors @ @ SYSTEM_CLOCK = 8000000 @@ -105,21 +105,6 @@ _tx_initialize_low_level: @ ORRS r1, r1, r2 @ Set the CYCCNTENA bit @ STR r1, [r0] @ Enable the cycle count register @ -@ /* Setup Vector Table Offset Register. */ -@ - LDR r0, =0xE000E000 @ Build address of NVIC registers - LDR r2, =0xD08 @ Offset to vector base register - ADD r0, r0, r2 @ Build vector base register - LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0] @ Set vector table address -@ -@ /* Set system stack pointer from vector value. */ -@ - LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer - LDR r1, =_vectors @ Pickup address of vector table - LDR r1, [r1] @ Pickup reset stack pointer - STR r1, [r0] @ Save system stack pointer -@ @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ LDR r0, =0xE000E000 @ Build address of NVIC registers diff --git a/ports/cortex_m0/gnu/inc/tx_port.h b/ports/cortex_m0/gnu/inc/tx_port.h index 4e5270de..6d8a77c9 100644 --- a/ports/cortex_m0/gnu/inc/tx_port.h +++ b/ports/cortex_m0/gnu/inc/tx_port.h @@ -9,7 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ -// Some portions generated by Gemini (Gemini 2.0 Flash). +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -324,13 +324,13 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); - __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); + __asm__ volatile ("dsb sy \n isb sy " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); - __asm__ volatile ("isb 0xF " : : : "memory"); + __asm__ volatile ("isb sy " : : : "memory"); } } @@ -359,7 +359,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/GNU Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/GNU Version 6.5.2.202603 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S index 96854867..68fd5251 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S @@ -85,7 +85,14 @@ _tx_thread_context_restore: /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function - POP {r0, lr} // Recover return address + POP {r0, r1} // Recover r0 and the return address + MOV lr, r1 // This core cannot POP into LR: the + // 16-bit Thumb POP takes r0-r7 and + // pc only. MOV to a high register + // is permitted, so restore LR from + // a scratch register. r1 is free -- + // the BL above may clobber r0-r3, + // which is why r0 is saved at all. #endif BX lr @} diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_save.S b/ports/cortex_m0/gnu/src/tx_thread_context_save.S index 9866da13..e62a2871 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_save.S @@ -76,7 +76,14 @@ _tx_thread_context_save: /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function - POP {r0, lr} // Recover return address + POP {r0, r1} // Recover r0 and the return address + MOV lr, r1 // This core cannot POP into LR: the + // 16-bit Thumb POP takes r0-r7 and + // pc only. MOV to a high register + // is permitted, so restore LR from + // a scratch register. r1 is free -- + // the BL above may clobber r0-r3, + // which is why r0 is saved at all. #endif /* Context is already saved - just return. */ diff --git a/ports/cortex_m0/gnu/src/tx_thread_schedule.S b/ports/cortex_m0/gnu/src/tx_thread_schedule.S index 21b6118a..787d4e10 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m0/gnu/src/tx_thread_schedule.S @@ -95,8 +95,8 @@ _tx_thread_schedule: @ @ /* Enter the scheduler for the first time. */ @ - LDR r0, =#0x10000000 @ Load PENDSVSET bit - LDR r1, =#0xE000ED04 @ Load NVIC base + LDR r0, =0x10000000 @ Load PENDSVSET bit + LDR r1, =0xE000ED04 @ Load NVIC base STR r0, [r1] @ Set PENDSVBIT in ICSR DSB @ Complete all memory accesses ISB @ Flush pipeline diff --git a/ports/cortex_m0/gnu/src/tx_thread_system_return.S b/ports/cortex_m0/gnu/src/tx_thread_system_return.S index 6019b299..b03e03ba 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m0/gnu/src/tx_thread_system_return.S @@ -8,7 +8,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ -// Some portions generated by Gemini (Gemini 2.0 Flash). +@ Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -26,7 +26,10 @@ #include "tx_user.h" #endif - .text 32 +@ Plain .text rather than a numbered subsection: with .text 32, clang places +@ the constant pool for the LDR literals below outside the range a Thumb-1 +@ PC-relative load can reach. GNU as accepts either form. + .text .align 4 .syntax unified @/**************************************************************************/ diff --git a/ports/cortex_m0/iar/CMakeLists.txt b/ports/cortex_m0/iar/CMakeLists.txt index 57be3aeb..e9583502 100644 --- a/ports/cortex_m0/iar/CMakeLists.txt +++ b/ports/cortex_m0/iar/CMakeLists.txt @@ -16,6 +16,7 @@ target_sources(${PROJECT_NAME} ) target_include_directories(${PROJECT_NAME} + SYSTEM PUBLIC ${CMAKE_CURRENT_LIST_DIR}/inc ) diff --git a/ports/cortex_m0/iar/example_build/tx.ewp b/ports/cortex_m0/iar/example_build/tx.ewp index 94481d2e..a3b29c58 100644 --- a/ports/cortex_m0/iar/example_build/tx.ewp +++ b/ports/cortex_m0/iar/example_build/tx.ewp @@ -1047,7 +1047,7 @@ </option> <option> <name>IarchiveOutput</name> - <state>C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\Debug\Exe\tx.a</state> + <state>###Unitialized###</state> </option> </data> </settings> diff --git a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s index 991f7809..9f83fa06 100644 --- a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -20,10 +22,8 @@ ;/**************************************************************************/ ; ; - EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_timer_interrupt - EXTERN __vector_table EXTERN _tx_execution_isr_enter EXTERN _tx_execution_isr_exit ; @@ -100,21 +100,6 @@ _tx_initialize_low_level: ; ORRS r1, r1, r2 ; Set the CYCCNTENA bit ; STR r1, [r0] ; Enable the cycle count register ; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD08 ; Offset to vector base register - ADD r0, r0, r2 ; Build vector base register - LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__vector_table ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers diff --git a/ports/cortex_m0/iar/inc/tx_port.h b/ports/cortex_m0/iar/inc/tx_port.h index 2dcb7b4e..6c9621d6 100644 --- a/ports/cortex_m0/iar/inc/tx_port.h +++ b/ports/cortex_m0/iar/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -313,12 +315,13 @@ __istate_t interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); - __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); + __asm__ volatile ("dsb sy \n isb sy " : : : "memory"); if (__get_IPSR() == 0) { interrupt_save = __get_interrupt_state(); __enable_interrupt(); __set_interrupt_state(interrupt_save); + __asm__ volatile ("isb sy " : : : "memory"); } } @@ -339,7 +342,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/IAR Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/IAR Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/iar/src/tx_iar.c b/ports/cortex_m0/iar/src/tx_iar.c index 238b485e..ab6c209c 100644 --- a/ports/cortex_m0/iar/src/tx_iar.c +++ b/ports/cortex_m0/iar/src/tx_iar.c @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ /**************************************************************************/ @@ -270,7 +271,7 @@ TX_MUTEX *mutex_ptr; mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; /* Check for wrap-around on the next free mutex. */ - if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK) { /* Yes, set the free index back to 0. */ @@ -287,7 +288,7 @@ TX_MUTEX *mutex_ptr; } /* Determine if a free mutex was found. */ - if (i >= _MAX_LOCK) + if (i >= _MAX_FLOCK) { /* Error! No more free mutexes! */ @@ -678,7 +679,7 @@ TX_MUTEX *mutex_ptr; mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; /* Check for wrap-around on the next free mutex. */ - if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK) { /* Yes, set the free index back to 0. */ @@ -695,7 +696,7 @@ TX_MUTEX *mutex_ptr; } /* Determine if a free mutex was found. */ - if (i >= _MAX_LOCK) + if (i >= _MAX_FLOCK) { /* Error! No more free mutexes! */ diff --git a/ports/cortex_m0/iar/src/tx_thread_system_return.s b/ports/cortex_m0/iar/src/tx_thread_system_return.s index 9426a137..929b3a00 100644 --- a/ports/cortex_m0/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m0/iar/src/tx_thread_system_return.s @@ -9,7 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ -; Some portions generated by Gemini (Gemini 2.0 Flash). +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -79,6 +79,7 @@ _tx_thread_system_return: MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture + ISB SY ; Flush pipeline _isr_context: BX lr ; Return to caller ;} diff --git a/ports/cortex_m0/keil/example_build/ThreadX_Demo.uvoptx b/ports/cortex_m0/keil/example_build/ThreadX_Demo.uvoptx deleted file mode 100644 index 0d104bc0..00000000 --- a/ports/cortex_m0/keil/example_build/ThreadX_Demo.uvoptx +++ /dev/null @@ -1,224 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no" ?> -<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> - 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IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory IMPORT _tx_timer_interrupt IMPORT __main @@ -137,12 +138,6 @@ _tx_initialize_low_level ADDS r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000ED08 ; Build address of NVIC registers - LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register @@ -151,21 +146,6 @@ _tx_initialize_low_level ; ORRS r1, r1, r2 ; Set the CYCCNTENA bit ; STR r1, [r0] ; Enable the cycle count register ; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD08 ; Offset to vector base register - ADD r0, r0, r2 ; Build vector base register - LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__tx_vectors ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers diff --git a/ports/cortex_m0/keil/inc/tx_port.h b/ports/cortex_m0/keil/inc/tx_port.h index 5ddf74bb..53018a6f 100644 --- a/ports/cortex_m0/keil/inc/tx_port.h +++ b/ports/cortex_m0/keil/inc/tx_port.h @@ -312,7 +312,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; |