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-rw-r--r--ports/cortex_m33/ac6/CMakeLists.txt21
-rw-r--r--ports/cortex_m33/ac6/inc/tx_port.h23
-rw-r--r--ports/cortex_m33/ac6/src/tx_initialize_low_level.S278
-rw-r--r--ports/cortex_m33/ac6/src/tx_misra.S719
-rw-r--r--ports/cortex_m33/ac6/src/tx_thread_secure_stack.c3
-rw-r--r--ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S8
-rw-r--r--ports/cortex_m33/gnu/CMakeLists.txt21
-rw-r--r--ports/cortex_m33/gnu/inc/tx_port.h23
-rw-r--r--ports/cortex_m33/gnu/src/tx_misra.S719
-rw-r--r--ports/cortex_m33/gnu/src/tx_thread_secure_stack.c6
-rw-r--r--ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S8
-rw-r--r--ports/cortex_m33/iar/inc/tx_port.h23
-rw-r--r--ports/cortex_m33/iar/src/tx_misra.s559
-rw-r--r--ports/cortex_m33/iar/src/tx_thread_secure_stack.c12
-rw-r--r--ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s8
15 files changed, 2002 insertions, 429 deletions
diff --git a/ports/cortex_m33/ac6/CMakeLists.txt b/ports/cortex_m33/ac6/CMakeLists.txt
new file mode 100644
index 00000000..5ad3b8e7
--- /dev/null
+++ b/ports/cortex_m33/ac6/CMakeLists.txt
@@ -0,0 +1,21 @@
+target_sources(${PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
+ ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack.c
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_allocate.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_free.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
+)
+
+target_include_directories(${PROJECT_NAME} PUBLIC
+ inc
+)
diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h
index aaa02995..90573b50 100644
--- a/ports/cortex_m33/ac6/inc/tx_port.h
+++ b/ports/cortex_m33/ac6/inc/tx_port.h
@@ -25,8 +25,8 @@
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
-/* tx_port.h Cortex-M33 */
-/* 6.1.11 */
+/* tx_port.h Cortex-M33/AC6 */
+/* 6.1.12 */
/* */
/* AUTHOR */
/* */
@@ -61,16 +61,21 @@
/* added symbol to enable */
/* stack error handler, */
/* resulting in version 6.1.7 */
-/* 10-15-2021 Scott Larson Modified comment(s), improved */
+/* 10-15-2021 Scott Larson Modified comment(s), improved */
/* stack check error handling, */
/* resulting in version 6.1.9 */
-/* 01-31-2022 Scott Larson Modified comment(s), unified */
+/* 01-31-2022 Scott Larson Modified comment(s), unified */
/* this file across compilers, */
/* fixed predefined macro, */
/* resulting in version 6.1.10 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
+/* 07-29-2022 Scott Larson Modified comments and changed */
+/* secure stack initialization */
+/* macro to port-specific, */
+/* described BASEPRI usage, */
+/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
@@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
+/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts.
+If using BASEPRI is desired, define the following two symbols for both c and assembly files:
+TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK.
+TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask.
+Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run.
+*/
/* Define various constants for the ThreadX Cortex-M port. */
@@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID);
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
/* Initialize secure stacks for threads calling secure functions. */
extern void _tx_thread_secure_stack_initialize(void);
-#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize();
+#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize();
#endif
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
@@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
- "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.10 *";
+ "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1.12 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
diff --git a/ports/cortex_m33/ac6/src/tx_initialize_low_level.S b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S
new file mode 100644
index 00000000..a5e8e946
--- /dev/null
+++ b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S
@@ -0,0 +1,278 @@
+/**************************************************************************/
+/* */
+/* Copyright (c) Microsoft Corporation. All rights reserved. */
+/* */
+/* This software is licensed under the Microsoft Software License */
+/* Terms for Microsoft Azure RTOS. Full text of the license can be */
+/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
+/* and in the root directory of this software. */
+/* */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ThreadX Component */
+/** */
+/** Initialize */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+
+SYSTEM_CLOCK = 6000000
+SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
+
+/* Setup the stack and heap areas. */
+
+STACK_SIZE = 0x00000400
+HEAP_SIZE = 0x00000000
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* _tx_initialize_low_level Cortex-M33/AC6 */
+/* 6.1 */
+/* AUTHOR */
+/* */
+/* Scott Larson, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function is responsible for any low-level processor */
+/* initialization, including setting up interrupt vectors, setting */
+/* up a periodic timer interrupt source, saving the system stack */
+/* pointer for use in ISR processing later, and finding the first */
+/* available RAM memory address for tx_application_define. */
+/* */
+/* INPUT */
+/* */
+/* None */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* None */
+/* */
+/* CALLED BY */
+/* */
+/* _tx_initialize_kernel_enter ThreadX entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* 09-30-2020 Scott Larson Initial Version 6.1 */
+/* */
+/**************************************************************************/
+// VOID _tx_initialize_low_level(VOID)
+// {
+ .section .text
+ .balign 4
+ .syntax unified
+ .eabi_attribute Tag_ABI_align_preserved, 1
+ .global _tx_initialize_low_level
+ .thumb_func
+.type _tx_initialize_low_level, function
+_tx_initialize_low_level:
+
+ /* Disable interrupts during ThreadX initialization. */
+ CPSID i
+
+ /* Set base of available memory to end of non-initialised RAM area. */
+ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
+ LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address
+ ADD r1, r1, #4 //
+ STR r1, [r0] // Setup first unused memory pointer
+
+ /* Setup Vector Table Offset Register. */
+ MOV r0, #0xE000E000 // Build address of NVIC registers
+ LDR r1, =__Vectors // Pickup address of vector table
+ STR r1, [r0, #0xD08] // Set vector table address
+
+ /* Enable the cycle count register. */
+ LDR r0, =0xE0001000 // Build address of DWT register
+ LDR r1, [r0] // Pickup the current value
+ ORR r1, r1, #1 // Set the CYCCNTENA bit
+ STR r1, [r0] // Enable the cycle count register
+
+ /* Set system stack pointer from vector value. */
+ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
+ LDR r1, =__Vectors // Pickup address of vector table
+ LDR r1, [r1] // Pickup reset stack pointer
+ STR r1, [r0] // Save system stack pointer
+
+ /* Configure SysTick. */
+ MOV r0, #0xE000E000 // Build address of NVIC registers
+ LDR r1, =SYSTICK_CYCLES
+ STR r1, [r0, #0x14] // Setup SysTick Reload Value
+ MOV r1, #0x7 // Build SysTick Control Enable Value
+ STR r1, [r0, #0x10] // Setup SysTick Control
+
+ /* Configure handler priorities. */
+ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
+ STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers
+
+ LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
+ STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers
+ // Note: SVC must be lowest priority, which is 0xFF
+
+ LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
+ STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers
+ // Note: PnSV must be lowest priority, which is 0xFF
+
+ /* Return to caller. */
+ BX lr
+// }
+
+
+/* Define shells for each of the unused vectors. */
+ .section .text
+ .balign 4
+ .syntax unified
+ .eabi_attribute Tag_ABI_align_preserved, 1
+ .global __tx_BadHandler
+ .thumb_func
+.type __tx_BadHandler, function
+__tx_BadHandler:
+ B __tx_BadHandler
+
+
+ .section .text
+ .balign 4
+ .syntax unified
+ .eabi_attribute Tag_ABI_align_preserved, 1
+ .global __tx_IntHandler
+ .thumb_func
+.type __tx_IntHandler, function
+__tx_IntHandler:
+// VOID InterruptHandler (VOID)
+// {
+ PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
+#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
+ BL _tx_execution_isr_enter // Call the ISR enter function
+#endif
+ /* Do interrupt handler work here */
+ /* .... */
+#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
+ BL _tx_execution_isr_exit // Call the ISR exit function
+#endif
+ POP {r0,lr}
+ BX LR
+// }
+
+
+ .section .text
+ .balign 4
+ .syntax unified
+ .eabi_attribute Tag_ABI_align_preserved, 1
+ .global SysTick_Handler
+ .thumb_func
+.type SysTick_Handler, function
+SysTick_Handler:
+// VOID TimerInterruptHandler (VOID)
+// {
+ PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
+#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
+ BL _tx_execution_isr_enter // Call the ISR enter function
+#endif
+ BL _tx_timer_interrupt
+#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
+ BL _tx_execution_isr_exit // Call the ISR exit function
+#endif
+ POP {r0,lr}
+ BX LR
+// }
+
+
+ .section .text
+ .balign 4
+ .syntax unified
+ .eabi_attribute Tag_ABI_align_preserved, 1
+ .global HardFault_Handler
+ .thumb_func
+.type HardFault_Handler, function
+HardFault_Handler:
+ B HardFault_Handler
+
+
+ .section .text
+ .balign 4
+ .syntax unified
+ .eabi_attribute Tag_ABI_align_preserved, 1
+ .global UsageFault_Handler
+ .thumb_func
+.type UsageFault_Handler, function
+UsageFault_Handler:
+ CPSID i // Disable interrupts
+ // Check for stack limit fault
+ LDR r0, =0xE000ED28 // CFSR address
+ LDR r1,[r0] // Pick up CFSR
+ TST r1, #0x00100000 // Check for Stack Overflow
+_unhandled_usage_loop:
+ BEQ _unhandled_usage_loop // If not stack overflow then loop
+
+ // Handle stack overflow
+ STR r1, [r0] // Clear CFSR flag(s)
+
+#ifdef __ARM_PCS_VFP
+ LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address
+ LDR r1, [r0] // Load FPCCR
+ BIC r1, r1, #1 // Clear the lazy preservation active bit
+ STR r1, [r0] // Store the value
+#endif
+
+ LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
+ LDR r0,[r0] // Pick up current thread pointer
+ PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment)
+ BL _tx_thread_stack_error_handler // Call ThreadX/user handler
+ POP {r0,lr} // Restore LR and dummy reg
+
+#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
+ // Call the thread exit function to indicate the thread is no longer executing.
+ PUSH {r0, lr} // Save LR (and r0 just for alignment)
+ BL _tx_execution_thread_exit // Call the thread exit function
+ POP {r0, lr} // Recover LR
+#endif
+
+ MOV r1, #0 // Build NULL value
+ LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer
+ STR r1, [r0] // Clear current thread pointer
+
+ // Return from UsageFault_Handler exception
+ LDR r0, =0xE000ED04 // Load ICSR
+ LDR r1, =0x10000000 // Set PENDSVSET bit
+ STR r1, [r0] // Store ICSR
+ DSB // Wait for memory access to complete
+ CPSIE i // Enable interrupts
+ BX lr // Return from exception
+
+
+
+ .section .text
+ .balign 4
+ .syntax unified
+ .eabi_attribute Tag_ABI_align_preserved, 1
+ .global __tx_NMIHandler
+ .thumb_func
+.type __tx_NMIHandler, function
+__tx_NMIHandler:
+ B __tx_NMIHandler
+
+
+ .section .text
+ .balign 4
+ .syntax unified
+ .eabi_attribute Tag_ABI_align_preserved, 1
+ .global __tx_DBGHandler
+ .thumb_func
+.type __tx_DBGHandler, function
+__tx_DBGHandler:
+ B __tx_DBGHandler
+
+ .end
diff --git a/ports/cortex_m33/ac6/src/tx_misra.S b/ports/cortex_m33/ac6/src/tx_misra.S
new file mode 100644
index 00000000..155512be
--- /dev/null
+++ b/ports/cortex_m33/ac6/src/tx_misra.S
@@ -0,0 +1,719 @@
+/**************************************************************************/
+/* */
+/* Copyright (c) Microsoft Corporation. All rights reserved. */
+/* */
+/* This software is licensed under the Microsoft Software License */
+/* Terms for Microsoft Azure RTOS. Full text of the license can be */
+/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
+/* and in the root directory of this software. */
+/* */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ThreadX Component */
+/** */
+/** ThreadX MISRA Compliance */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ #define SHT_PROGBITS 0x1
+
+ .global __aeabi_memset
+ .global _tx_thread_current_ptr
+ .global _tx_thread_interrupt_disable
+ .global _tx_thread_interrupt_restore
+ .global _tx_thread_stack_analyze
+ .global _tx_thread_stack_error_handler
+ .global _tx_thread_system_state
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_trace_buffer_current_ptr
+ .global _tx_trace_buffer_end_ptr
+ .global _tx_trace_buffer_start_ptr
+ .global _tx_trace_event_enable_bits
+ .global _tx_trace_full_notify_function
+ .global _tx_trace_header_ptr
+#endif
+
+ .global _tx_misra_always_true
+ .global _tx_misra_block_pool_to_uchar_pointer_convert
+ .global _tx_misra_byte_pool_to_uchar_pointer_convert
+ .global _tx_misra_char_to_uchar_pointer_convert
+ .global _tx_misra_const_char_to_char_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_entry_to_uchar_pointer_convert
+#endif
+ .global _tx_misra_indirect_void_to_uchar_pointer_convert
+ .global _tx_misra_memset
+ .global _tx_misra_message_copy
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_object_to_uchar_pointer_convert
+#endif
+ .global _tx_misra_pointer_to_ulong_convert
+ .global _tx_misra_status_get
+ .global _tx_misra_thread_stack_check
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_time_stamp_get
+#endif
+ .global _tx_misra_timer_indirect_to_void_pointer_convert
+ .global _tx_misra_timer_pointer_add
+ .global _tx_misra_timer_pointer_dif
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_trace_event_insert
+#endif
+ .global _tx_misra_uchar_pointer_add
+ .global _tx_misra_uchar_pointer_dif
+ .global _tx_misra_uchar_pointer_sub
+ .global _tx_misra_uchar_to_align_type_pointer_convert
+ .global _tx_misra_uchar_to_block_pool_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_uchar_to_entry_pointer_convert
+ .global _tx_misra_uchar_to_header_pointer_convert
+#endif
+ .global _tx_misra_uchar_to_indirect_byte_pool_pointer_convert
+ .global _tx_misra_uchar_to_indirect_uchar_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_uchar_to_object_pointer_convert
+#endif
+ .global _tx_misra_uchar_to_void_pointer_convert
+ .global _tx_misra_ulong_pointer_add
+ .global _tx_misra_ulong_pointer_dif
+ .global _tx_misra_ulong_pointer_sub
+ .global _tx_misra_ulong_to_pointer_convert
+ .global _tx_misra_ulong_to_thread_pointer_convert
+ .global _tx_misra_user_timer_pointer_get
+ .global _tx_misra_void_to_block_pool_pointer_convert
+ .global _tx_misra_void_to_byte_pool_pointer_convert
+ .global _tx_misra_void_to_event_flags_pointer_convert
+ .global _tx_misra_void_to_indirect_uchar_pointer_convert
+ .global _tx_misra_void_to_mutex_pointer_convert
+ .global _tx_misra_void_to_queue_pointer_convert
+ .global _tx_misra_void_to_semaphore_pointer_convert
+ .global _tx_misra_void_to_thread_pointer_convert
+ .global _tx_misra_void_to_uchar_pointer_convert
+ .global _tx_misra_void_to_ulong_pointer_convert
+ .global _tx_misra_ipsr_get
+ .global _tx_misra_control_get
+ .global _tx_misra_control_set
+#ifdef __ARM_FP
+ .global _tx_misra_fpccr_get
+ .global _tx_misra_vfp_touch
+#endif
+
+ .global _tx_misra_event_flags_group_not_used
+ .global _tx_misra_event_flags_set_notify_not_used
+ .global _tx_misra_queue_not_used
+ .global _tx_misra_queue_send_notify_not_used
+ .global _tx_misra_semaphore_not_used
+ .global _tx_misra_semaphore_put_notify_not_used
+ .global _tx_misra_thread_entry_exit_notify_not_used
+ .global _tx_misra_thread_not_used
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .align 4
+ .syntax unified
+ .thumb_func
+_tx_misra_memset:
+ PUSH {R4,LR}
+ MOVS R4,R0
+ MOVS R0,R2
+ MOVS R2,R1
+ MOVS R1,R0
+ MOVS R0,R4
+ BL __aeabi_memset
+ POP {R4,PC} // return
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_uchar_pointer_add:
+ ADD R0,R0,R1
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_uchar_pointer_sub:
+ RSBS R1,R1,#+0
+ ADD R0,R0,R1
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_uchar_pointer_dif:
+ SUBS R0,R0,R1
+ BX LR // return
+
+
+/************************************************************************************************************************************/
+/************************************************************************************************************************************/
+/** */
+/** This single function serves all of the below prototypes. */
+/** */
+/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */
+/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */
+/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */
+/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */
+/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */
+/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */
+/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */
+/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */
+/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */
+/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */
+/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */
+/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */
+/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */
+/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */
+/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */
+/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */
+/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */
+/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */
+/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */
+/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */
+/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */
+/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */
+/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */
+/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */
+/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */
+/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */
+/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */
+/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */
+/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */
+/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */
+/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */
+/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */
+/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */
+/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */
+/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */
+/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */
+/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */
+/** */
+/************************************************************************************************************************************/
+/************************************************************************************************************************************/
+ .text
+ .thumb_func
+_tx_misra_pointer_to_ulong_convert:
+_tx_misra_ulong_to_pointer_convert:
+_tx_misra_indirect_void_to_uchar_pointer_convert:
+_tx_misra_uchar_to_indirect_uchar_pointer_convert:
+_tx_misra_block_pool_to_uchar_pointer_convert:
+_tx_misra_void_to_block_pool_pointer_convert:
+_tx_misra_void_to_uchar_pointer_convert:
+_tx_misra_uchar_to_block_pool_pointer_convert:
+_tx_misra_void_to_indirect_uchar_pointer_convert:
+_tx_misra_void_to_byte_pool_pointer_convert:
+_tx_misra_byte_pool_to_uchar_pointer_convert:
+_tx_misra_uchar_to_align_type_pointer_convert:
+_tx_misra_uchar_to_indirect_byte_pool_pointer_convert:
+_tx_misra_void_to_event_flags_pointer_convert:
+_tx_misra_void_to_ulong_pointer_convert:
+_tx_misra_void_to_mutex_pointer_convert:
+_tx_misra_void_to_queue_pointer_convert:
+_tx_misra_void_to_semaphore_pointer_convert:
+_tx_misra_uchar_to_void_pointer_convert:
+_tx_misra_ulong_to_thread_pointer_convert:
+_tx_misra_timer_indirect_to_void_pointer_convert:
+_tx_misra_const_char_to_char_pointer_convert:
+_tx_misra_void_to_thread_pointer_convert:
+#ifdef TX_ENABLE_EVENT_TRACE
+_tx_misra_object_to_uchar_pointer_convert:
+_tx_misra_uchar_to_object_pointer_convert:
+_tx_misra_uchar_to_header_pointer_convert:
+_tx_misra_uchar_to_entry_pointer_convert:
+_tx_misra_entry_to_uchar_pointer_convert:
+#endif
+_tx_misra_char_to_uchar_pointer_convert:
+_tx_misra_event_flags_group_not_used:
+_tx_misra_event_flags_set_notify_not_used:
+_tx_misra_queue_not_used:
+_tx_misra_queue_send_notify_not_used:
+_tx_misra_semaphore_not_used:
+_tx_misra_semaphore_put_notify_not_used:
+_tx_misra_thread_entry_exit_notify_not_used:
+_tx_misra_thread_not_used:
+
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_ulong_pointer_add:
+ ADD R0,R0,R1, LSL #+2
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_ulong_pointer_sub:
+ MVNS R2,#+3
+ MULS R1,R2,R1
+ ADD R0,R0,R1
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_ulong_pointer_dif:
+ SUBS R0,R0,R1
+ ASRS R0,R0,#+2
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */
+/** UINT size); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_message_copy:
+ PUSH {R4,R5}
+ LDR R3,[R0, #+0]
+ LDR R4,[R1, #+0]
+ LDR R5,[R3, #+0]
+ STR R5,[R4, #+0]
+ ADDS R4,R4,#+4
+ ADDS R3,R3,#+4
+ CMP R2,#+2
+ BCC.N _tx_misra_message_copy_0
+ SUBS R2,R2,#+1
+ B.N _tx_misra_message_copy_1
+_tx_misra_message_copy_2:
+ LDR R5,[R3, #+0]
+ STR R5,[R4, #+0]
+ ADDS R4,R4,#+4
+ ADDS R3,R3,#+4
+ SUBS R2,R2,#+1
+_tx_misra_message_copy_1:
+ CMP R2,#+0
+ BNE.N _tx_misra_message_copy_2
+_tx_misra_message_copy_0:
+ STR R3,[R0, #+0]
+ STR R4,[R1, #+0]
+ POP {R4,R5}
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */
+/** TX_TIMER_INTERNAL **ptr2); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_timer_pointer_dif:
+ SUBS R0,R0,R1
+ ASRS R0,R0,#+2
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */
+/** **ptr1, ULONG size); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_timer_pointer_add:
+ ADD R0,R0,R1, LSL #+2
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */
+/** *internal_timer, TX_TIMER **user_timer); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_user_timer_pointer_get:
+ SUBS R0,#8
+ STR R0,[R1, #+0]
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */
+/** VOID **highest_stack); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_thread_stack_check:
+ PUSH {R3-R5,LR}
+ MOVS R4,R0
+ MOVS R5,R1
+ BL _tx_thread_interrupt_disable
+ CMP R4,#+0
+ BEQ.N _tx_misra_thread_stack_check_0
+ LDR R1,[R4, #+0]
+ LDR R2,=0x54485244
+ CMP R1,R2
+ BNE.N _tx_misra_thread_stack_check_0
+ LDR R1,[R4, #+8]
+ LDR R2,[R5, #+0]
+ CMP R1,R2
+ BCS.N _tx_misra_thread_stack_check_1
+ LDR R1,[R4, #+8]
+ STR R1,[R5, #+0]
+_tx_misra_thread_stack_check_1:
+ LDR R1,[R4, #+12]
+ LDR R1,[R1, #+0]
+ CMP R1,#-269488145
+ BNE.N _tx_misra_thread_stack_check_2
+ LDR R1,[R4, #+16]
+ LDR R1,[R1, #+1]
+ CMP R1,#-269488145
+ BNE.N _tx_misra_thread_stack_check_2
+ LDR R1,[R5, #+0]
+ LDR R2,[R4, #+12]
+ CMP R1,R2
+ BCS.N _tx_misra_thread_stack_check_3
+_tx_misra_thread_stack_check_2:
+ BL _tx_thread_interrupt_restore
+ MOVS R0,R4
+ BL _tx_thread_stack_error_handler
+ BL _tx_thread_interrupt_disable
+_tx_misra_thread_stack_check_3:
+ LDR R1,[R5, #+0]
+ LDR R1,[R1, #-4]
+ CMP R1,#-269488145
+ BEQ.N _tx_misra_thread_stack_check_0
+ BL _tx_thread_interrupt_restore
+ MOVS R0,R4
+ BL _tx_thread_stack_analyze
+ BL _tx_thread_interrupt_disable
+_tx_misra_thread_stack_check_0:
+ BL _tx_thread_interrupt_restore
+ POP {R0,R4,R5,PC} // return
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_trace_event_insert(ULONG event_id, */
+/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */
+/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_trace_event_insert:
+ PUSH {R3-R7,LR}
+ LDR.N R4,DataTable2_1
+ LDR R4,[R4, #+0]
+ CMP R4,#+0
+ BEQ.N _tx_misra_trace_event_insert_0
+ LDR.N R5,DataTable2_2
+ LDR R5,[R5, #+0]
+ LDR R6,[SP, #+28]
+ TST R5,R6
+ BEQ.N _tx_misra_trace_event_insert_0
+ LDR.N R5,DataTable2_3
+ LDR R5,[R5, #+0]
+ LDR.N R6,DataTable2_4
+ LDR R6,[R6, #+0]
+ CMP R5,#+0
+ BNE.N _tx_misra_trace_event_insert_1
+ LDR R5,[R6, #+44]
+ LDR R7,[R6, #+60]
+ LSLS R7,R7,#+16
+ ORRS R7,R7,#0x80000000
+ ORRS R5,R7,R5
+ B.N _tx_misra_trace_event_insert_2
+_tx_misra_trace_event_insert_1:
+ CMP R5,#-252645136
+ BCS.N _tx_misra_trace_event_insert_3
+ MOVS R5,R6
+ MOVS R6,#-1
+ B.N _tx_misra_trace_event_insert_2
+_tx_misra_trace_event_insert_3:
+ MOVS R6,#-252645136
+ MOVS R5,#+0
+_tx_misra_trace_event_insert_2:
+ STR R6,[R4, #+0]
+ STR R5,[R4, #+4]
+ STR R0,[R4, #+8]
+ LDR R0,[SP, #+32]
+ STR R0,[R4, #+12]
+ STR R1,[R4, #+16]
+ STR R2,[R4, #+20]
+ STR R3,[R4, #+24]
+ LDR R0,[SP, #+24]
+ STR R0,[R4, #+28]
+ ADDS R4,R4,#+32
+ LDR.N R0,DataTable2_5
+ LDR R0,[R0, #+0]
+ CMP R4,R0
+ BCC.N _tx_misra_trace_event_insert_4
+ LDR.N R0,DataTable2_6
+ LDR R4,[R0, #+0]
+ LDR.N R0,DataTable2_1
+ STR R4,[R0, #+0]
+ LDR.N R0,DataTable2_7
+ LDR R0,[R0, #+0]
+ STR R4,[R0, #+32]
+ LDR.N R0,DataTable2_8
+ LDR R0,[R0, #+0]
+ CMP R0,#+0
+ BEQ.N _tx_misra_trace_event_insert_0
+ LDR.N R0,DataTable2_7
+ LDR R0,[R0, #+0]
+ LDR.N R1,DataTable2_8
+ LDR R1,[R1, #+0]
+ BLX R1
+ B.N _tx_misra_trace_event_insert_0
+_tx_misra_trace_event_insert_4:
+ LDR.N R0,DataTable2_1
+ STR R4,[R0, #+0]
+ LDR.N R0,DataTable2_7
+ LDR R0,[R0, #+0]
+ STR R4,[R0, #+32]
+_tx_misra_trace_event_insert_0:
+ POP {R0,R4-R7,PC} // return
+
+
+ .data
+DataTable2_1:
+ .word _tx_trace_buffer_current_ptr
+
+ .data
+DataTable2_2:
+ .word _tx_trace_event_enable_bits
+
+ .data
+DataTable2_5:
+ .word _tx_trace_buffer_end_ptr
+
+ .data
+DataTable2_6:
+ .word _tx_trace_buffer_start_ptr
+
+ .data
+DataTable2_7:
+ .word _tx_trace_header_ptr
+
+ .data
+DataTable2_8:
+ .word _tx_trace_full_notify_function
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG _tx_misra_time_stamp_get(VOID); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_time_stamp_get:
+ MOVS R0,#+0
+ BX LR // return
+
+#endif
+
+ .data
+DataTable2_3:
+ .word _tx_thread_system_state
+
+ .data
+DataTable2_4:
+ .word _tx_thread_current_ptr
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** UINT _tx_misra_always_true(void); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_always_true:
+ MOVS R0,#+1
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** UINT _tx_misra_status_get(UINT status); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_status_get:
+ MOVS R0,#+0
+ BX LR // return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** ULONG _tx_misra_ipsr_get(void); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_ipsr_get:
+ MRS R0, IPSR
+ BX LR // return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** ULONG _tx_misra_control_get(void); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_control_get:
+ MRS R0, CONTROL
+ BX LR // return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** void _tx_misra_control_set(ULONG value); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_control_set:
+ MSR CONTROL, R0
+ BX LR // return
+
+
+#ifdef __ARM_FP
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** ULONG _tx_misra_fpccr_get(void); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_fpccr_get:
+ LDR r0, =0xE000EF34 // Build FPCCR address
+ LDR r0, [r0] // Load FPCCR value
+ BX LR // return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** void _tx_misra_vfp_touch(void); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_vfp_touch:
+ vmov.f32 s0, s0
+ BX LR // return
+
+#endif
+
+
+ .data
+ .word 0
diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c
index d41bdbbe..099ae737 100644
--- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c
+++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c
@@ -219,7 +219,7 @@ TX_INTERRUPT_SAVE_AREA
UINT status;
TX_THREAD_SECURE_STACK_INFO *info_ptr;
UCHAR *stack_mem;
-INT secure_context_index;
+INT secure_context_index;
status = TX_SUCCESS;
@@ -241,7 +241,6 @@ INT secure_context_index;
else
{
-
TX_DISABLE
/* Allocate free index for secure stack info. */
diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S
index 4baf378a..a96e30ab 100644
--- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S
+++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S
@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */
-/* 6.1.7 */
+/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -49,13 +49,17 @@
/* */
/* CALLED BY */
/* */
-/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */
+/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
+/* 07-29-2022 Scott Larson Modified comments and changed */
+/* secure stack initialization */
+/* macro to port-specific, */
+/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)
diff --git a/ports/cortex_m33/gnu/CMakeLists.txt b/ports/cortex_m33/gnu/CMakeLists.txt
new file mode 100644
index 00000000..5ad3b8e7
--- /dev/null
+++ b/ports/cortex_m33/gnu/CMakeLists.txt
@@ -0,0 +1,21 @@
+target_sources(${PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
+ ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack.c
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_allocate.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_free.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
+ ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
+)
+
+target_include_directories(${PROJECT_NAME} PUBLIC
+ inc
+)
diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h
index aaa02995..24c5adf2 100644
--- a/ports/cortex_m33/gnu/inc/tx_port.h
+++ b/ports/cortex_m33/gnu/inc/tx_port.h
@@ -25,8 +25,8 @@
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
-/* tx_port.h Cortex-M33 */
-/* 6.1.11 */
+/* tx_port.h Cortex-M33/GNU */
+/* 6.1.12 */
/* */
/* AUTHOR */
/* */
@@ -61,16 +61,21 @@
/* added symbol to enable */
/* stack error handler, */
/* resulting in version 6.1.7 */
-/* 10-15-2021 Scott Larson Modified comment(s), improved */
+/* 10-15-2021 Scott Larson Modified comment(s), improved */
/* stack check error handling, */
/* resulting in version 6.1.9 */
-/* 01-31-2022 Scott Larson Modified comment(s), unified */
+/* 01-31-2022 Scott Larson Modified comment(s), unified */
/* this file across compilers, */
/* fixed predefined macro, */
/* resulting in version 6.1.10 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
+/* 07-29-2022 Scott Larson Modified comments and changed */
+/* secure stack initialization */
+/* macro to port-specific, */
+/* described BASEPRI usage, */
+/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
@@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
+/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts.
+If using BASEPRI is desired, define the following two symbols for both c and assembly files:
+TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK.
+TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask.
+Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run.
+*/
/* Define various constants for the ThreadX Cortex-M port. */
@@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID);
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
/* Initialize secure stacks for threads calling secure functions. */
extern void _tx_thread_secure_stack_initialize(void);
-#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize();
+#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize();
#endif
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
@@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
- "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.10 *";
+ "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/GNU Version 6.1.12 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
diff --git a/ports/cortex_m33/gnu/src/tx_misra.S b/ports/cortex_m33/gnu/src/tx_misra.S
new file mode 100644
index 00000000..155512be
--- /dev/null
+++ b/ports/cortex_m33/gnu/src/tx_misra.S
@@ -0,0 +1,719 @@
+/**************************************************************************/
+/* */
+/* Copyright (c) Microsoft Corporation. All rights reserved. */
+/* */
+/* This software is licensed under the Microsoft Software License */
+/* Terms for Microsoft Azure RTOS. Full text of the license can be */
+/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
+/* and in the root directory of this software. */
+/* */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ThreadX Component */
+/** */
+/** ThreadX MISRA Compliance */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ #define SHT_PROGBITS 0x1
+
+ .global __aeabi_memset
+ .global _tx_thread_current_ptr
+ .global _tx_thread_interrupt_disable
+ .global _tx_thread_interrupt_restore
+ .global _tx_thread_stack_analyze
+ .global _tx_thread_stack_error_handler
+ .global _tx_thread_system_state
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_trace_buffer_current_ptr
+ .global _tx_trace_buffer_end_ptr
+ .global _tx_trace_buffer_start_ptr
+ .global _tx_trace_event_enable_bits
+ .global _tx_trace_full_notify_function
+ .global _tx_trace_header_ptr
+#endif
+
+ .global _tx_misra_always_true
+ .global _tx_misra_block_pool_to_uchar_pointer_convert
+ .global _tx_misra_byte_pool_to_uchar_pointer_convert
+ .global _tx_misra_char_to_uchar_pointer_convert
+ .global _tx_misra_const_char_to_char_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_entry_to_uchar_pointer_convert
+#endif
+ .global _tx_misra_indirect_void_to_uchar_pointer_convert
+ .global _tx_misra_memset
+ .global _tx_misra_message_copy
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_object_to_uchar_pointer_convert
+#endif
+ .global _tx_misra_pointer_to_ulong_convert
+ .global _tx_misra_status_get
+ .global _tx_misra_thread_stack_check
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_time_stamp_get
+#endif
+ .global _tx_misra_timer_indirect_to_void_pointer_convert
+ .global _tx_misra_timer_pointer_add
+ .global _tx_misra_timer_pointer_dif
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_trace_event_insert
+#endif
+ .global _tx_misra_uchar_pointer_add
+ .global _tx_misra_uchar_pointer_dif
+ .global _tx_misra_uchar_pointer_sub
+ .global _tx_misra_uchar_to_align_type_pointer_convert
+ .global _tx_misra_uchar_to_block_pool_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_uchar_to_entry_pointer_convert
+ .global _tx_misra_uchar_to_header_pointer_convert
+#endif
+ .global _tx_misra_uchar_to_indirect_byte_pool_pointer_convert
+ .global _tx_misra_uchar_to_indirect_uchar_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+ .global _tx_misra_uchar_to_object_pointer_convert
+#endif
+ .global _tx_misra_uchar_to_void_pointer_convert
+ .global _tx_misra_ulong_pointer_add
+ .global _tx_misra_ulong_pointer_dif
+ .global _tx_misra_ulong_pointer_sub
+ .global _tx_misra_ulong_to_pointer_convert
+ .global _tx_misra_ulong_to_thread_pointer_convert
+ .global _tx_misra_user_timer_pointer_get
+ .global _tx_misra_void_to_block_pool_pointer_convert
+ .global _tx_misra_void_to_byte_pool_pointer_convert
+ .global _tx_misra_void_to_event_flags_pointer_convert
+ .global _tx_misra_void_to_indirect_uchar_pointer_convert
+ .global _tx_misra_void_to_mutex_pointer_convert
+ .global _tx_misra_void_to_queue_pointer_convert
+ .global _tx_misra_void_to_semaphore_pointer_convert
+ .global _tx_misra_void_to_thread_pointer_convert
+ .global _tx_misra_void_to_uchar_pointer_convert
+ .global _tx_misra_void_to_ulong_pointer_convert
+ .global _tx_misra_ipsr_get
+ .global _tx_misra_control_get
+ .global _tx_misra_control_set
+#ifdef __ARM_FP
+ .global _tx_misra_fpccr_get
+ .global _tx_misra_vfp_touch
+#endif
+
+ .global _tx_misra_event_flags_group_not_used
+ .global _tx_misra_event_flags_set_notify_not_used
+ .global _tx_misra_queue_not_used
+ .global _tx_misra_queue_send_notify_not_used
+ .global _tx_misra_semaphore_not_used
+ .global _tx_misra_semaphore_put_notify_not_used
+ .global _tx_misra_thread_entry_exit_notify_not_used
+ .global _tx_misra_thread_not_used
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .align 4
+ .syntax unified
+ .thumb_func
+_tx_misra_memset:
+ PUSH {R4,LR}
+ MOVS R4,R0
+ MOVS R0,R2
+ MOVS R2,R1
+ MOVS R1,R0
+ MOVS R0,R4
+ BL __aeabi_memset
+ POP {R4,PC} // return
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_uchar_pointer_add:
+ ADD R0,R0,R1
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_uchar_pointer_sub:
+ RSBS R1,R1,#+0
+ ADD R0,R0,R1
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_uchar_pointer_dif:
+ SUBS R0,R0,R1
+ BX LR // return
+
+
+/************************************************************************************************************************************/
+/************************************************************************************************************************************/
+/** */
+/** This single function serves all of the below prototypes. */
+/** */
+/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */
+/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */
+/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */
+/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */
+/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */
+/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */
+/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */
+/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */
+/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */
+/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */
+/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */
+/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */
+/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */
+/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */
+/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */
+/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */
+/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */
+/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */
+/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */
+/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */
+/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */
+/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */
+/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */
+/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */
+/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */
+/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */
+/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */
+/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */
+/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */
+/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */
+/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */
+/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */
+/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */
+/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */
+/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */
+/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */
+/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */
+/** */
+/************************************************************************************************************************************/
+/************************************************************************************************************************************/
+ .text
+ .thumb_func
+_tx_misra_pointer_to_ulong_convert:
+_tx_misra_ulong_to_pointer_convert:
+_tx_misra_indirect_void_to_uchar_pointer_convert:
+_tx_misra_uchar_to_indirect_uchar_pointer_convert:
+_tx_misra_block_pool_to_uchar_pointer_convert:
+_tx_misra_void_to_block_pool_pointer_convert:
+_tx_misra_void_to_uchar_pointer_convert:
+_tx_misra_uchar_to_block_pool_pointer_convert:
+_tx_misra_void_to_indirect_uchar_pointer_convert:
+_tx_misra_void_to_byte_pool_pointer_convert:
+_tx_misra_byte_pool_to_uchar_pointer_convert:
+_tx_misra_uchar_to_align_type_pointer_convert:
+_tx_misra_uchar_to_indirect_byte_pool_pointer_convert:
+_tx_misra_void_to_event_flags_pointer_convert:
+_tx_misra_void_to_ulong_pointer_convert:
+_tx_misra_void_to_mutex_pointer_convert:
+_tx_misra_void_to_queue_pointer_convert:
+_tx_misra_void_to_semaphore_pointer_convert:
+_tx_misra_uchar_to_void_pointer_convert:
+_tx_misra_ulong_to_thread_pointer_convert:
+_tx_misra_timer_indirect_to_void_pointer_convert:
+_tx_misra_const_char_to_char_pointer_convert:
+_tx_misra_void_to_thread_pointer_convert:
+#ifdef TX_ENABLE_EVENT_TRACE
+_tx_misra_object_to_uchar_pointer_convert:
+_tx_misra_uchar_to_object_pointer_convert:
+_tx_misra_uchar_to_header_pointer_convert:
+_tx_misra_uchar_to_entry_pointer_convert:
+_tx_misra_entry_to_uchar_pointer_convert:
+#endif
+_tx_misra_char_to_uchar_pointer_convert:
+_tx_misra_event_flags_group_not_used:
+_tx_misra_event_flags_set_notify_not_used:
+_tx_misra_queue_not_used:
+_tx_misra_queue_send_notify_not_used:
+_tx_misra_semaphore_not_used:
+_tx_misra_semaphore_put_notify_not_used:
+_tx_misra_thread_entry_exit_notify_not_used:
+_tx_misra_thread_not_used:
+
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_ulong_pointer_add:
+ ADD R0,R0,R1, LSL #+2
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_ulong_pointer_sub:
+ MVNS R2,#+3
+ MULS R1,R2,R1
+ ADD R0,R0,R1
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_ulong_pointer_dif:
+ SUBS R0,R0,R1
+ ASRS R0,R0,#+2
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */
+/** UINT size); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_message_copy:
+ PUSH {R4,R5}
+ LDR R3,[R0, #+0]
+ LDR R4,[R1, #+0]
+ LDR R5,[R3, #+0]
+ STR R5,[R4, #+0]
+ ADDS R4,R4,#+4
+ ADDS R3,R3,#+4
+ CMP R2,#+2
+ BCC.N _tx_misra_message_copy_0
+ SUBS R2,R2,#+1
+ B.N _tx_misra_message_copy_1
+_tx_misra_message_copy_2:
+ LDR R5,[R3, #+0]
+ STR R5,[R4, #+0]
+ ADDS R4,R4,#+4
+ ADDS R3,R3,#+4
+ SUBS R2,R2,#+1
+_tx_misra_message_copy_1:
+ CMP R2,#+0
+ BNE.N _tx_misra_message_copy_2
+_tx_misra_message_copy_0:
+ STR R3,[R0, #+0]
+ STR R4,[R1, #+0]
+ POP {R4,R5}
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */
+/** TX_TIMER_INTERNAL **ptr2); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_timer_pointer_dif:
+ SUBS R0,R0,R1
+ ASRS R0,R0,#+2
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */
+/** **ptr1, ULONG size); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_timer_pointer_add:
+ ADD R0,R0,R1, LSL #+2
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */
+/** *internal_timer, TX_TIMER **user_timer); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_user_timer_pointer_get:
+ SUBS R0,#8
+ STR R0,[R1, #+0]
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */
+/** VOID **highest_stack); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_thread_stack_check:
+ PUSH {R3-R5,LR}
+ MOVS R4,R0
+ MOVS R5,R1
+ BL _tx_thread_interrupt_disable
+ CMP R4,#+0
+ BEQ.N _tx_misra_thread_stack_check_0
+ LDR R1,[R4, #+0]
+ LDR R2,=0x54485244
+ CMP R1,R2
+ BNE.N _tx_misra_thread_stack_check_0
+ LDR R1,[R4, #+8]
+ LDR R2,[R5, #+0]
+ CMP R1,R2
+ BCS.N _tx_misra_thread_stack_check_1
+ LDR R1,[R4, #+8]
+ STR R1,[R5, #+0]
+_tx_misra_thread_stack_check_1:
+ LDR R1,[R4, #+12]
+ LDR R1,[R1, #+0]
+ CMP R1,#-269488145
+ BNE.N _tx_misra_thread_stack_check_2
+ LDR R1,[R4, #+16]
+ LDR R1,[R1, #+1]
+ CMP R1,#-269488145
+ BNE.N _tx_misra_thread_stack_check_2
+ LDR R1,[R5, #+0]
+ LDR R2,[R4, #+12]
+ CMP R1,R2
+ BCS.N _tx_misra_thread_stack_check_3
+_tx_misra_thread_stack_check_2:
+ BL _tx_thread_interrupt_restore
+ MOVS R0,R4
+ BL _tx_thread_stack_error_handler
+ BL _tx_thread_interrupt_disable
+_tx_misra_thread_stack_check_3:
+ LDR R1,[R5, #+0]
+ LDR R1,[R1, #-4]
+ CMP R1,#-269488145
+ BEQ.N _tx_misra_thread_stack_check_0
+ BL _tx_thread_interrupt_restore
+ MOVS R0,R4
+ BL _tx_thread_stack_analyze
+ BL _tx_thread_interrupt_disable
+_tx_misra_thread_stack_check_0:
+ BL _tx_thread_interrupt_restore
+ POP {R0,R4,R5,PC} // return
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** VOID _tx_misra_trace_event_insert(ULONG event_id, */
+/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */
+/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_trace_event_insert:
+ PUSH {R3-R7,LR}
+ LDR.N R4,DataTable2_1
+ LDR R4,[R4, #+0]
+ CMP R4,#+0
+ BEQ.N _tx_misra_trace_event_insert_0
+ LDR.N R5,DataTable2_2
+ LDR R5,[R5, #+0]
+ LDR R6,[SP, #+28]
+ TST R5,R6
+ BEQ.N _tx_misra_trace_event_insert_0
+ LDR.N R5,DataTable2_3
+ LDR R5,[R5, #+0]
+ LDR.N R6,DataTable2_4
+ LDR R6,[R6, #+0]
+ CMP R5,#+0
+ BNE.N _tx_misra_trace_event_insert_1
+ LDR R5,[R6, #+44]
+ LDR R7,[R6, #+60]
+ LSLS R7,R7,#+16
+ ORRS R7,R7,#0x80000000
+ ORRS R5,R7,R5
+ B.N _tx_misra_trace_event_insert_2
+_tx_misra_trace_event_insert_1:
+ CMP R5,#-252645136
+ BCS.N _tx_misra_trace_event_insert_3
+ MOVS R5,R6
+ MOVS R6,#-1
+ B.N _tx_misra_trace_event_insert_2
+_tx_misra_trace_event_insert_3:
+ MOVS R6,#-252645136
+ MOVS R5,#+0
+_tx_misra_trace_event_insert_2:
+ STR R6,[R4, #+0]
+ STR R5,[R4, #+4]
+ STR R0,[R4, #+8]
+ LDR R0,[SP, #+32]
+ STR R0,[R4, #+12]
+ STR R1,[R4, #+16]
+ STR R2,[R4, #+20]
+ STR R3,[R4, #+24]
+ LDR R0,[SP, #+24]
+ STR R0,[R4, #+28]
+ ADDS R4,R4,#+32
+ LDR.N R0,DataTable2_5
+ LDR R0,[R0, #+0]
+ CMP R4,R0
+ BCC.N _tx_misra_trace_event_insert_4
+ LDR.N R0,DataTable2_6
+ LDR R4,[R0, #+0]
+ LDR.N R0,DataTable2_1
+ STR R4,[R0, #+0]
+ LDR.N R0,DataTable2_7
+ LDR R0,[R0, #+0]
+ STR R4,[R0, #+32]
+ LDR.N R0,DataTable2_8
+ LDR R0,[R0, #+0]
+ CMP R0,#+0
+ BEQ.N _tx_misra_trace_event_insert_0
+ LDR.N R0,DataTable2_7
+ LDR R0,[R0, #+0]
+ LDR.N R1,DataTable2_8
+ LDR R1,[R1, #+0]
+ BLX R1
+ B.N _tx_misra_trace_event_insert_0
+_tx_misra_trace_event_insert_4:
+ LDR.N R0,DataTable2_1
+ STR R4,[R0, #+0]
+ LDR.N R0,DataTable2_7
+ LDR R0,[R0, #+0]
+ STR R4,[R0, #+32]
+_tx_misra_trace_event_insert_0:
+ POP {R0,R4-R7,PC} // return
+
+
+ .data
+DataTable2_1:
+ .word _tx_trace_buffer_current_ptr
+
+ .data
+DataTable2_2:
+ .word _tx_trace_event_enable_bits
+
+ .data
+DataTable2_5:
+ .word _tx_trace_buffer_end_ptr
+
+ .data
+DataTable2_6:
+ .word _tx_trace_buffer_start_ptr
+
+ .data
+DataTable2_7:
+ .word _tx_trace_header_ptr
+
+ .data
+DataTable2_8:
+ .word _tx_trace_full_notify_function
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ULONG _tx_misra_time_stamp_get(VOID); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_time_stamp_get:
+ MOVS R0,#+0
+ BX LR // return
+
+#endif
+
+ .data
+DataTable2_3:
+ .word _tx_thread_system_state
+
+ .data
+DataTable2_4:
+ .word _tx_thread_current_ptr
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** UINT _tx_misra_always_true(void); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_always_true:
+ MOVS R0,#+1
+ BX LR // return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** UINT _tx_misra_status_get(UINT status); */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_status_get:
+ MOVS R0,#+0
+ BX LR // return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** ULONG _tx_misra_ipsr_get(void); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_ipsr_get:
+ MRS R0, IPSR
+ BX LR // return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** ULONG _tx_misra_control_get(void); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_control_get:
+ MRS R0, CONTROL
+ BX LR // return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** void _tx_misra_control_set(ULONG value); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_control_set:
+ MSR CONTROL, R0
+ BX LR // return
+
+
+#ifdef __ARM_FP
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** ULONG _tx_misra_fpccr_get(void); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_fpccr_get:
+ LDR r0, =0xE000EF34 // Build FPCCR address
+ LDR r0, [r0] // Load FPCCR value
+ BX LR // return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** void _tx_misra_vfp_touch(void); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+ .text
+ .thumb_func
+_tx_misra_vfp_touch:
+ vmov.f32 s0, s0
+ BX LR // return
+
+#endif
+
+
+ .data
+ .word 0
diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c
index 0b064098..13bfc29a 100644
--- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c
+++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c
@@ -167,7 +167,7 @@ INT index;
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_mode_stack_allocate Cortex-M33/GNU */
-/* 6.1.10 */
+/* 6.1.11a */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -207,11 +207,15 @@ INT index;
/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */
/* secure stack allocation, */
/* resulting in version 6.1.10 */
+/* 05-02-2022 Scott Larson Modified comment(s), added */
+/* TX_INTERRUPT_SAVE_AREA, */
+/* resulting in version 6.1.11a*/
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
{
+TX_INTERRUPT_SAVE_AREA
UINT status;
TX_THREAD_SECURE_STACK_INFO *info_ptr;
UCHAR *stack_mem;
diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S
index 9e9642fc..a9f899f6 100644
--- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S
+++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S
@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M33/GNU */
-/* 6.1.7 */
+/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -49,13 +49,17 @@
/* */
/* CALLED BY */
/* */
-/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */
+/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
+/* 07-29-2022 Scott Larson Modified comments and changed */
+/* secure stack initialization */
+/* macro to port-specific, */
+/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)
diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h
index aaa02995..05fc5a6b 100644
--- a/ports/cortex_m33/iar/inc/tx_port.h
+++ b/ports/cortex_m33/iar/inc/tx_port.h
@@ -25,8 +25,8 @@
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
-/* tx_port.h Cortex-M33 */
-/* 6.1.11 */
+/* tx_port.h Cortex-M33/IAR */
+/* 6.1.12 */
/* */
/* AUTHOR */
/* */
@@ -61,16 +61,21 @@
/* added symbol to enable */
/* stack error handler, */
/* resulting in version 6.1.7 */
-/* 10-15-2021 Scott Larson Modified comment(s), improved */
+/* 10-15-2021 Scott Larson Modified comment(s), improved */
/* stack check error handling, */
/* resulting in version 6.1.9 */
-/* 01-31-2022 Scott Larson Modified comment(s), unified */
+/* 01-31-2022 Scott Larson Modified comment(s), unified */
/* this file across compilers, */
/* fixed predefined macro, */
/* resulting in version 6.1.10 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
+/* 07-29-2022 Scott Larson Modified comments and changed */
+/* secure stack initialization */
+/* macro to port-specific, */
+/* described BASEPRI usage, */
+/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
@@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
+/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts.
+If using BASEPRI is desired, define the following two symbols for both c and assembly files:
+TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK.
+TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask.
+Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run.
+*/
/* Define various constants for the ThreadX Cortex-M port. */
@@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID);
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
/* Initialize secure stacks for threads calling secure functions. */
extern void _tx_thread_secure_stack_initialize(void);
-#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize();
+#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize();
#endif
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
@@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
- "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.10 *";
+ "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.1.12 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
diff --git a/ports/cortex_m33/iar/src/tx_misra.s b/ports/cortex_m33/iar/src/tx_misra.s
index acb85cc9..c81c3e5c 100644
--- a/ports/cortex_m33/iar/src/tx_misra.s
+++ b/ports/cortex_m33/iar/src/tx_misra.s
@@ -96,6 +96,22 @@
PUBLIC _tx_misra_void_to_uchar_pointer_convert
PUBLIC _tx_misra_void_to_ulong_pointer_convert
PUBLIC _tx_misra_ipsr_get
+ PUBLIC _tx_misra_control_get
+ PUBLIC _tx_misra_control_set
+#ifdef __ARMVFP__
+ PUBLIC _tx_misra_fpccr_get
+ PUBLIC _tx_misra_vfp_touch
+#endif
+
+ PUBLIC _tx_misra_event_flags_group_not_used
+ PUBLIC _tx_misra_event_flags_set_notify_not_used
+ PUBLIC _tx_misra_queue_not_used
+ PUBLIC _tx_misra_queue_send_notify_not_used
+ PUBLIC _tx_misra_semaphore_not_used
+ PUBLIC _tx_misra_semaphore_put_notify_not_used
+ PUBLIC _tx_misra_thread_entry_exit_notify_not_used
+ PUBLIC _tx_misra_thread_not_used
+
PUBLIC _tx_version_id
@@ -109,7 +125,7 @@ _tx_version_id:
DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H
DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH
DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H
- DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 30H
+ DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 31H
DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H
DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H
DC8 6EH, 74H, 20H, 2AH, 0
@@ -133,7 +149,7 @@ _tx_misra_memset:
MOVS R1,R0
MOVS R0,R4
BL __aeabi_memset
- POP {R4,PC} ;; return
+ POP {R4,PC} // return
/**************************************************************************/
/**************************************************************************/
@@ -147,7 +163,7 @@ _tx_misra_memset:
THUMB
_tx_misra_uchar_pointer_add:
ADD R0,R0,R1
- BX LR ;; return
+ BX LR // return
/**************************************************************************/
@@ -163,7 +179,7 @@ _tx_misra_uchar_pointer_add:
_tx_misra_uchar_pointer_sub:
RSBS R1,R1,#+0
ADD R0,R0,R1
- BX LR ;; return
+ BX LR // return
/**************************************************************************/
@@ -178,21 +194,97 @@ _tx_misra_uchar_pointer_sub:
THUMB
_tx_misra_uchar_pointer_dif:
SUBS R0,R0,R1
- BX LR ;; return
+ BX LR // return
-/**************************************************************************/
-/**************************************************************************/
-/** */
-/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */
-/** */
-/**************************************************************************/
-/**************************************************************************/
-
+/************************************************************************************************************************************/
+/************************************************************************************************************************************/
+/** */
+/** This single function serves all of the below prototypes. */
+/** */
+/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */
+/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */
+/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */
+/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */
+/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */
+/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */
+/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */
+/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */
+/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */
+/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */
+/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */
+/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */
+/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */
+/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */
+/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */
+/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */
+/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */
+/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */
+/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */
+/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */
+/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */
+/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */
+/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */
+/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */
+/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */
+/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */
+/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */
+/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */
+/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */
+/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */
+/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */
+/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */
+/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */
+/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */
+/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */
+/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */
+/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */
+/** */
+/************************************************************************************************************************************/
+/************************************************************************************************************************************/
SECTION `.text`:CODE:NOROOT(1)
THUMB
_tx_misra_pointer_to_ulong_convert:
- BX LR ;; return
+_tx_misra_ulong_to_pointer_convert:
+_tx_misra_indirect_void_to_uchar_pointer_convert:
+_tx_misra_uchar_to_indirect_uchar_pointer_convert:
+_tx_misra_block_pool_to_uchar_pointer_convert:
+_tx_misra_void_to_block_pool_pointer_convert:
+_tx_misra_void_to_uchar_pointer_convert:
+_tx_misra_uchar_to_block_pool_pointer_convert:
+_tx_misra_void_to_indirect_uchar_pointer_convert:
+_tx_misra_void_to_byte_pool_pointer_convert:
+_tx_misra_byte_pool_to_uchar_pointer_convert:
+_tx_misra_uchar_to_align_type_pointer_convert:
+_tx_misra_uchar_to_indirect_byte_pool_pointer_convert:
+_tx_misra_void_to_event_flags_pointer_convert:
+_tx_misra_void_to_ulong_pointer_convert:
+_tx_misra_void_to_mutex_pointer_convert:
+_tx_misra_void_to_queue_pointer_convert:
+_tx_misra_void_to_semaphore_pointer_convert:
+_tx_misra_uchar_to_void_pointer_convert:
+_tx_misra_ulong_to_thread_pointer_convert:
+_tx_misra_timer_indirect_to_void_pointer_convert:
+_tx_misra_const_char_to_char_pointer_convert:
+_tx_misra_void_to_thread_pointer_convert:
+#ifdef TX_ENABLE_EVENT_TRACE
+_tx_misra_object_to_uchar_pointer_convert:
+_tx_misra_uchar_to_object_pointer_convert:
+_tx_misra_uchar_to_header_pointer_convert:
+_tx_misra_uchar_to_entry_pointer_convert:
+_tx_misra_entry_to_uchar_pointer_convert:
+#endif
+_tx_misra_char_to_uchar_pointer_convert:
+_tx_misra_event_flags_group_not_used:
+_tx_misra_event_flags_set_notify_not_used:
+_tx_misra_queue_not_used:
+_tx_misra_queue_send_notify_not_used:
+_tx_misra_semaphore_not_used:
+_tx_misra_semaphore_put_notify_not_used:
+_tx_misra_thread_entry_exit_notify_not_used:
+_tx_misra_thread_not_used:
+
+ BX LR // return
/**************************************************************************/
@@ -207,7 +299,7 @@ _tx_misra_pointer_to_ulong_convert:
THUMB
_tx_misra_ulong_pointer_add:
ADD R0,R0,R1, LSL #+2
- BX LR ;; return
+ BX LR // return
/**************************************************************************/
@@ -224,7 +316,7 @@ _tx_misra_ulong_pointer_sub:
MVNS R2,#+3
MULS R1,R2,R1
ADD R0,R0,R1
- BX LR ;; return
+ BX LR // return
/**************************************************************************/
@@ -240,21 +332,7 @@ _tx_misra_ulong_pointer_sub:
_tx_misra_ulong_pointer_dif:
SUBS R0,R0,R1
ASRS R0,R0,#+2
- BX LR ;; return
-
-
-/**************************************************************************/
-/**************************************************************************/
-/** */
-/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */
-/** */
-/**************************************************************************/
-/**************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_ulong_to_pointer_convert:
- BX LR ;; return
+ BX LR // return
/**************************************************************************/
@@ -293,7 +371,7 @@ _tx_misra_message_copy:
STR R3,[R0, #+0]
STR R4,[R1, #+0]
POP {R4,R5}
- BX LR ;; return
+ BX LR // return
/**************************************************************************/
@@ -310,7 +388,7 @@ _tx_misra_message_copy:
_tx_misra_timer_pointer_dif:
SUBS R0,R0,R1
ASRS R0,R0,#+2
- BX LR ;; return
+ BX LR // return
/**************************************************************************/
@@ -326,7 +404,7 @@ _tx_misra_timer_pointer_dif:
THUMB
_tx_misra_timer_pointer_add:
ADD R0,R0,R1, LSL #+2
- BX LR ;; return
+ BX LR // return
/**************************************************************************/
@@ -341,12 +419,9 @@ _tx_misra_timer_pointer_add:
SECTION `.text`:CODE:NOROOT(1)
THUMB
_tx_misra_user_timer_pointer_get:
- ADDS R2,R0,#+8
- SUBS R2,R2,R0
- RSBS R2,R2,#+0
- ADD R0,R0,R2
- STR R0,[R1, #+0]
- BX LR ;; return
+ SUBS R0,#8
+ STR R0,[R1, #+0]
+ BX LR // return
/**************************************************************************/
@@ -368,7 +443,7 @@ _tx_misra_thread_stack_check:
CMP R4,#+0
BEQ.N ??_tx_misra_thread_stack_check_0
LDR R1,[R4, #+0]
- LDR.N R2,??DataTable2 ;; 0x54485244
+ LDR.N R2,??DataTable2 // 0x54485244
CMP R1,R2
BNE.N ??_tx_misra_thread_stack_check_0
LDR R1,[R4, #+8]
@@ -406,7 +481,7 @@ _tx_misra_thread_stack_check:
BL _tx_thread_interrupt_disable
??_tx_misra_thread_stack_check_0:
BL _tx_thread_interrupt_restore
- POP {R0,R4,R5,PC} ;; return
+ POP {R0,R4,R5,PC} // return
#ifdef TX_ENABLE_EVENT_TRACE
@@ -494,7 +569,7 @@ _tx_misra_trace_event_insert:
LDR R0,[R0, #+0]
STR R4,[R0, #+32]
??_tx_misra_trace_event_insert_0:
- POP {R0,R4-R7,PC} ;; return
+ POP {R0,R4-R7,PC} // return
SECTION `.text`:CODE:NOROOT(2)
@@ -546,7 +621,7 @@ _tx_misra_trace_event_insert:
THUMB
_tx_misra_time_stamp_get:
MOVS R0,#+0
- BX LR ;; return
+ BX LR // return
#endif
@@ -581,203 +656,7 @@ _tx_misra_time_stamp_get:
THUMB
_tx_misra_always_true:
MOVS R0,#+1
- BX LR ;; return
-
-
-/******************************************************************************************/
-/******************************************************************************************/
-/** */
-/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */
-/** */
-/******************************************************************************************/
-/******************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_indirect_void_to_uchar_pointer_convert:
- BX LR ;; return
-
-
-/***************************************************************************************/
-/***************************************************************************************/
-/** */
-/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */
-/** */
-/***************************************************************************************/
-/***************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_uchar_to_indirect_uchar_pointer_convert:
- BX LR ;; return
-
-
-/***********************************************************************************/
-/***********************************************************************************/
-/** */
-/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */
-/** */
-/***********************************************************************************/
-/***********************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_block_pool_to_uchar_pointer_convert:
- BX LR ;; return
-
-
-/******************************************************************************************/
-/******************************************************************************************/
-/** */
-/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */
-/** */
-/******************************************************************************************/
-/******************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_block_pool_pointer_convert:
- BX LR ;; return
-
-
-/*****************************************************************************/
-/*****************************************************************************/
-/** */
-/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */
-/** */
-/*****************************************************************************/
-/*****************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_uchar_pointer_convert:
- BX LR ;; return
-
-
-/************************************************************************************/
-/************************************************************************************/
-/** */
-/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */
-/** */
-/************************************************************************************/
-/************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_uchar_to_block_pool_pointer_convert:
- BX LR ;; return
-
-
-/**************************************************************************************/
-/**************************************************************************************/
-/** */
-/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */
-/** */
-/**************************************************************************************/
-/**************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_indirect_uchar_pointer_convert:
- BX LR ;; return
-
-
-/*****************************************************************************************/
-/*****************************************************************************************/
-/** */
-/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */
-/** */
-/*****************************************************************************************/
-/*****************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_byte_pool_pointer_convert:
- BX LR ;; return
-
-
-/***************************************************************************************/
-/***************************************************************************************/
-/** */
-/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */
-/** */
-/***************************************************************************************/
-/***************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_byte_pool_to_uchar_pointer_convert:
- BX LR ;; return
-
-
-/*****************************************************************************************/
-/*****************************************************************************************/
-/** */
-/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */
-/** */
-/*****************************************************************************************/
-/*****************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_uchar_to_align_type_pointer_convert:
- BX LR ;; return
-
-
-/****************************************************************************************************/
-/****************************************************************************************************/
-/** */
-/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */
-/** */
-/****************************************************************************************************/
-/****************************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_uchar_to_indirect_byte_pool_pointer_convert:
- BX LR ;; return
-
-
-/**************************************************************************************************/
-/**************************************************************************************************/
-/** */
-/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */
-/** */
-/**************************************************************************************************/
-/**************************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_event_flags_pointer_convert:
- BX LR ;; return
-
-
-/*****************************************************************************/
-/*****************************************************************************/
-/** */
-/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */
-/** */
-/*****************************************************************************/
-/*****************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_ulong_pointer_convert:
- BX LR ;; return
-
-
-/********************************************************************************/
-/********************************************************************************/
-/** */
-/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */
-/** */
-/********************************************************************************/
-/********************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_mutex_pointer_convert:
- BX LR ;; return
+ BX LR // return
/**************************************************************************/
@@ -792,209 +671,89 @@ _tx_misra_void_to_mutex_pointer_convert:
THUMB
_tx_misra_status_get:
MOVS R0,#+0
- BX LR ;; return
-
-
-/********************************************************************************/
-/********************************************************************************/
-/** */
-/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */
-/** */
-/********************************************************************************/
-/********************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_queue_pointer_convert:
- BX LR ;; return
-
-
-/****************************************************************************************/
-/****************************************************************************************/
-/** */
-/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */
-/** */
-/****************************************************************************************/
-/****************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_semaphore_pointer_convert:
- BX LR ;; return
-
-
-/**************************************************************************/
-/**************************************************************************/
-/** */
-/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */
-/** */
-/**************************************************************************/
-/**************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_uchar_to_void_pointer_convert:
- BX LR ;; return
-
-
-/*********************************************************************************/
-/*********************************************************************************/
-/** */
-/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */
-/** */
-/*********************************************************************************/
-/*********************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_ulong_to_thread_pointer_convert:
- BX LR ;; return
-
-
-/***************************************************************************************************/
-/***************************************************************************************************/
-/** */
-/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */
-/** */
-/***************************************************************************************************/
-/***************************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_timer_indirect_to_void_pointer_convert:
- BX LR ;; return
-
-
-/***************************************************************************************/
-/***************************************************************************************/
-/** */
-/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */
-/** */
-/***************************************************************************************/
-/***************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_const_char_to_char_pointer_convert:
- BX LR ;; return
-
-
-/**********************************************************************************/
-/**********************************************************************************/
-/** */
-/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */
-/** */
-/**********************************************************************************/
-/**********************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_void_to_thread_pointer_convert:
- BX LR ;; return
-
-
-#ifdef TX_ENABLE_EVENT_TRACE
-
-/************************************************************************************************/
-/************************************************************************************************/
-/** */
-/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */
-/** */
-/************************************************************************************************/
-/************************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_object_to_uchar_pointer_convert:
- BX LR ;; return
-
-
-/************************************************************************************************/
-/************************************************************************************************/
-/** */
-/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */
-/** */
-/************************************************************************************************/
-/************************************************************************************************/
-
- SECTION `.text`:CODE:NOROOT(1)
- THUMB
-_tx_misra_uchar_to_object_pointer_convert:
- BX LR ;; return
+ BX LR // return
-/******************************************************************************************/
-/******************************************************************************************/
-/** */
-/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */
-/** */
-/******************************************************************************************/
-/******************************************************************************************/
+/***********************************************************************************************/
+/***********************************************************************************************/
+/** */
+/** ULONG _tx_misra_ipsr_get(void); */
+/** */
+/***********************************************************************************************/
+/***********************************************************************************************/
SECTION `.text`:CODE:NOROOT(1)
THUMB
-_tx_misra_uchar_to_header_pointer_convert:
- BX LR ;; return
+_tx_misra_ipsr_get:
+ MRS R0, IPSR
+ BX LR // return
/***********************************************************************************************/
/***********************************************************************************************/
/** */
-/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */
+/** ULONG _tx_misra_control_get(void); */
/** */
/***********************************************************************************************/
/***********************************************************************************************/
SECTION `.text`:CODE:NOROOT(1)
THUMB
-_tx_misra_uchar_to_entry_pointer_convert:
- BX LR ;; return
-
+_tx_misra_control_get:
+ MRS R0, CONTROL
+ BX LR // return
+
/***********************************************************************************************/
/***********************************************************************************************/
/** */
-/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */
+/** void _tx_misra_control_set(ULONG value); */
/** */
/***********************************************************************************************/
/***********************************************************************************************/
SECTION `.text`:CODE:NOROOT(1)
THUMB
-_tx_misra_entry_to_uchar_pointer_convert:
- BX LR ;; return
-#endif
+_tx_misra_control_set:
+ MSR CONTROL, R0
+ BX LR // return
+
+#ifdef __ARMVFP__
/***********************************************************************************************/
/***********************************************************************************************/
/** */
-/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */
+/** ULONG _tx_misra_fpccr_get(void); */
/** */
/***********************************************************************************************/
/***********************************************************************************************/
- SECTION `.text`:CODE:NOROOT(1)
+ SECTION `.text`:CODE:NOROOT(2)
THUMB
-_tx_misra_char_to_uchar_pointer_convert:
- BX LR ;; return
-
-
-***********************************************************************************************/
+_tx_misra_fpccr_get:
+ LDR r0, =0xE000EF34 // Build FPCCR address
+ LDR r0, [r0] // Load FPCCR value
+ BX LR // return
+
+
+/***********************************************************************************************/
/***********************************************************************************************/
/** */
-/** ULONG _tx_misra_ipsr_get(void); */
+/** void _tx_misra_vfp_touch(void); */
/** */
/***********************************************************************************************/
/***********************************************************************************************/
SECTION `.text`:CODE:NOROOT(1)
THUMB
-_tx_misra_ipsr_get:
- MRS R0, IPSR
- BX LR ;; return
-
-
+_tx_misra_vfp_touch:
+ vmov.f32 s0, s0
+ BX LR // return
+
+#endif
+
+
SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c
index 94d41db7..83e6c37d 100644
--- a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c
+++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c
@@ -165,7 +165,7 @@ INT index;
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_mode_stack_allocate Cortex-M33/IAR */
-/* 6.1.10 */
+/* 6.1.11a */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -209,11 +209,15 @@ INT index;
/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */
/* secure stack allocation, */
/* resulting in version 6.1.10 */
+/* 05-02-2022 Scott Larson Modified comment(s), added */
+/* TX_INTERRUPT_SAVE_AREA, */
+/* resulting in version 6.1.11a*/
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
{
+TX_INTERRUPT_SAVE_AREA
UINT status;
TX_THREAD_SECURE_STACK_INFO *info_ptr;
UCHAR *stack_mem;
@@ -314,7 +318,7 @@ INT secure_context_index;
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_mode_stack_free Cortex-M33/IAR */
-/* 6.1.10 */
+/* 6.1.11a */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -352,11 +356,15 @@ INT secure_context_index;
/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */
/* secure stack allocation, */
/* resulting in version 6.1.10 */
+/* 05-02-2022 Scott Larson Modified comment(s), added */
+/* TX_INTERRUPT_SAVE_AREA, */
+/* resulting in version 6.1.11a*/
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr)
{
+TX_INTERRUPT_SAVE_AREA
UINT status;
TX_THREAD_SECURE_STACK_INFO *info_ptr;
INT secure_context_index;
diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s
index 69e84264..4fb1bb3c 100644
--- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s
+++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s
@@ -27,7 +27,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M33/IAR */
-/* 6.1.7 */
+/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -50,13 +50,17 @@
/* */
/* CALLED BY */
/* */
-/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */
+/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
+/* 07-29-2022 Scott Larson Modified comments and changed */
+/* secure stack initialization */
+/* macro to port-specific, */
+/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)
generated by cgit v1.3.1 (git 2.54.0) at 2026-09-01 21:43:13 +0000