diff options
Diffstat (limited to 'ports/cortex_m85')
23 files changed, 805 insertions, 277 deletions
diff --git a/ports/cortex_m85/ac6/CMakeLists.txt b/ports/cortex_m85/ac6/CMakeLists.txt index 5ad3b8e7..81b479e0 100644 --- a/ports/cortex_m85/ac6/CMakeLists.txt +++ b/ports/cortex_m85/ac6/CMakeLists.txt @@ -16,6 +16,8 @@ target_sources(${PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S ) -target_include_directories(${PROJECT_NAME} PUBLIC +target_include_directories(${PROJECT_NAME} + SYSTEM + PUBLIC inc ) diff --git a/ports/cortex_m85/ac6/inc/tx_port.h b/ports/cortex_m85/ac6/inc/tx_port.h index 90917cbf..59203b70 100644 --- a/ports/cortex_m85/ac6/inc/tx_port.h +++ b/ports/cortex_m85/ac6/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -541,7 +543,7 @@ UINT posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } #else __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) @@ -554,6 +556,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -579,6 +582,7 @@ UINT interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb sy \n isb sy " : : : "memory"); if (_tx_ipsr_get() == 0) { interrupt_save = __get_interrupt_posture(); @@ -588,6 +592,7 @@ UINT interrupt_save; __enable_interrupts(); #endif __restore_interrupt(interrupt_save); + __asm__ volatile ("isb sy " : : : "memory"); } } @@ -613,7 +618,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/AC6 Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/AC6 Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/ac6/readme_threadx.txt b/ports/cortex_m85/ac6/readme_threadx.txt index abe80bf8..ea35c52d 100644 --- a/ports/cortex_m85/ac6/readme_threadx.txt +++ b/ports/cortex_m85/ac6/readme_threadx.txt @@ -218,7 +218,12 @@ information associated with this specific port of ThreadX: 03-02-2021 The following files were changed/added for version 6.1.5: tx_port.h Added ULONG64_DEFINED -09-30-2020 Initial ThreadX 6.1 version for Cortex-M85 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version of this Armv8-M port using AC6 tools. + + The dates above belong to this shared port, which every Armv8-M + core is generated from. They are not the date a particular core + gained a ThreadX port: that is when its name was added to + scripts/copy_armv8_m.sh. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m85/ac6/src/tx_initialize_low_level.S b/ports/cortex_m85/ac6/src/tx_initialize_low_level.S index a3daea70..31deaebb 100644 --- a/ports/cortex_m85/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m85/ac6/src/tx_initialize_low_level.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -87,25 +88,17 @@ _tx_initialize_low_level: ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer - /* Setup Vector Table Offset Register. */ - MOV r0, #0xE000E000 // Build address of NVIC registers - LDR r1, =__Vectors // Pickup address of vector table - STR r1, [r0, #0xD08] // Set vector table address - /* Enable the cycle count register. */ LDR r0, =0xE0001000 // Build address of DWT register LDR r1, [r0] // Pickup the current value ORR r1, r1, #1 // Set the CYCCNTENA bit STR r1, [r0] // Enable the cycle count register - /* Set system stack pointer from vector value. */ - LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer - LDR r1, =__Vectors // Pickup address of vector table - LDR r1, [r1] // Pickup reset stack pointer - STR r1, [r0] // Save system stack pointer - /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m85/ac6/src/tx_thread_schedule.S b/ports/cortex_m85/ac6/src/tx_thread_schedule.S index 62412fff..9132cc8d 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m85/ac6/src/tx_thread_schedule.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -129,7 +130,7 @@ __tx_ts_handler: BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -278,9 +279,19 @@ __tx_ts_wait: #endif #ifdef TX_ENABLE_WFI +#ifdef TX_PORT_USE_BASEPRI + CPSID i // Mask every interrupt with PRIMASK, which WFI ignores + MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it + MSR BASEPRI, r1 // is still able to wake the processor +#endif DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed +#ifdef TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask + MSR BASEPRI, r1 + CPSIE i // Clear PRIMASK; a pending interrupt is taken here +#endif #endif #ifdef TX_LOW_POWER diff --git a/ports/cortex_m85/ac6/src/tx_thread_system_return.S b/ports/cortex_m85/ac6/src/tx_thread_system_return.S index 2b335f8d..40eb6626 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m85/ac6/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -74,6 +76,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -82,10 +86,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #endif _isr_context: BX lr // Return to caller diff --git a/ports/cortex_m85/gnu/CMakeLists.txt b/ports/cortex_m85/gnu/CMakeLists.txt index 763a2696..a8e45b82 100644 --- a/ports/cortex_m85/gnu/CMakeLists.txt +++ b/ports/cortex_m85/gnu/CMakeLists.txt @@ -19,6 +19,7 @@ target_sources(${PROJECT_NAME} ) target_include_directories(${PROJECT_NAME} + SYSTEM PUBLIC ${CMAKE_CURRENT_LIST_DIR}/inc ) diff --git a/ports/cortex_m85/gnu/example_build/build_threadx.sh b/ports/cortex_m85/gnu/example_build/build_threadx.sh index 681a2050..cc87ce57 100755 --- a/ports/cortex_m85/gnu/example_build/build_threadx.sh +++ b/ports/cortex_m85/gnu/example_build/build_threadx.sh @@ -10,6 +10,7 @@ # SPDX-License-Identifier: MIT # # AI Disclosure: This file was largely AI-generated by Copilot (Claude Sonnet 4.6). +# Portions of this file were generated with AI assistance. # The AI-generated portions may be considered public domain (CC0-1.0) # and not subject to the project's licence. The human contributor has # reviewed and verified that the code is correct. @@ -20,228 +21,264 @@ set -e cd "$(dirname "$0")" +# Toolchain selection. The default is the GNU toolchain, so an existing +# invocation of this script behaves exactly as before. Set TOOLCHAIN=atfe to +# build with Arm Toolchain for Embedded, which is LLVM based and is the +# successor to Arm Compiler 6: +# +# TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx.sh +# +: "${TOOLCHAIN:=gnu}" +case "${TOOLCHAIN}" in + gnu) + CC="arm-none-eabi-gcc" + AR="arm-none-eabi-ar" + TARGET_FLAGS="" + ENTRY_FLAG="-ereset_handler" + SYSCALL_LIB="--specs=nosys.specs" + ;; + atfe) + CC="${ATFE_CLANG:-clang}" + # llvm-ar ships beside clang in the toolchain. + case "${CC}" in + */*) AR="$(dirname "${CC}")/llvm-ar" ;; + *) AR="llvm-ar" ;; + esac + TARGET_FLAGS="--target=arm-none-eabi" + ENTRY_FLAG="-Wl,--entry=reset_handler" + # picolibc leaves _exit to the application; the toolchain's own + # semihosting library supplies it, which suits an example that runs on + # a model. + SYSCALL_LIB="-lsemihost" + ;; + *) + echo "Unknown TOOLCHAIN '${TOOLCHAIN}'; expected gnu or atfe" >&2 + exit 1 + ;; +esac + rm -f tx.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_misra.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_context_restore.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_context_save.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_interrupt_control.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_interrupt_disable.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_interrupt_restore.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_schedule.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_secure_stack_allocate.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_secure_stack_free.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_secure_stack_initialize.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_stack_build.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_thread_system_return.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb ../src/tx_timer_interrupt.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_misra.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_context_restore.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_context_save.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_interrupt_control.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_interrupt_disable.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_interrupt_restore.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_schedule.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_secure_stack_allocate.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_secure_stack_free.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_secure_stack_initialize.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_stack_build.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_thread_system_return.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb ../src/tx_timer_interrupt.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb -I../../../../common/inc -I../inc ../src/tx_thread_secure_stack.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb -I../../../../common/inc -I../inc ../src/txe_thread_secure_stack_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb -I../../../../common/inc -I../inc ../src/txe_thread_secure_stack_free.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../src/tx_thread_secure_stack.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../src/txe_thread_secure_stack_allocate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../src/txe_thread_secure_stack_free.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m85 -mthumb -I../../../../common/inc -I../inc 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../../../../common/src/tx_event_flags_initialize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 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../../../../common/src/tx_queue_cleanup.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 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../../../../common/src/tx_semaphore_ceiling_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +"${CC}" ${TARGET_FLAGS} -c -g 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-I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +"${CC}" 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../../../../common/src/tx_thread_wait_abort.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard 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../../../../common/src/tx_timer_system_activate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +"${CC}" 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../../../../common/src/txe_block_pool_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c -arm-none-eabi-ar -r tx.a tx_misra.o tx_thread_context_restore.o tx_thread_context_save.o tx_thread_interrupt_control.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_schedule.o tx_thread_secure_stack_allocate.o tx_thread_secure_stack_free.o tx_thread_secure_stack_initialize.o -arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_system_return.o tx_timer_interrupt.o tx_thread_secure_stack.o txe_thread_secure_stack_allocate.o txe_thread_secure_stack_free.o tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o -arm-none-eabi-ar -r tx.a tx_block_pool_info_get.o tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o -arm-none-eabi-ar -r tx.a tx_byte_pool_info_get.o tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o -arm-none-eabi-ar -r tx.a tx_event_flags_get.o tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o -arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o -arm-none-eabi-ar -r tx.a tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o tx_queue_performance_system_info_get.o -arm-none-eabi-ar -r tx.a tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o -arm-none-eabi-ar -r tx.a tx_semaphore_initialize.o tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o -arm-none-eabi-ar -r tx.a tx_thread_info_get.o tx_thread_initialize.o tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o -arm-none-eabi-ar -r tx.a tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o tx_thread_terminate.o tx_thread_time_slice.o -arm-none-eabi-ar -r tx.a tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o -arm-none-eabi-ar -r tx.a tx_timer_expiration_process.o tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_buffer_full_notify.o tx_trace_enable.o -arm-none-eabi-ar -r tx.a tx_trace_event_filter.o tx_trace_event_unfilter.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o -arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o -arm-none-eabi-ar -r tx.a txe_byte_pool_prioritize.o txe_byte_release.o txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o -arm-none-eabi-ar -r tx.a txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o -arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o -arm-none-eabi-ar -r tx.a txe_semaphore_put_notify.o txe_thread_create.o txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o -arm-none-eabi-ar -r tx.a txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o +"${AR}" -r tx.a tx_misra.o tx_thread_context_restore.o tx_thread_context_save.o tx_thread_interrupt_control.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_schedule.o tx_thread_secure_stack_allocate.o tx_thread_secure_stack_free.o tx_thread_secure_stack_initialize.o +"${AR}" -r tx.a tx_thread_stack_build.o tx_thread_system_return.o tx_timer_interrupt.o tx_thread_secure_stack.o txe_thread_secure_stack_allocate.o txe_thread_secure_stack_free.o tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o +"${AR}" -r tx.a tx_block_pool_info_get.o tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o +"${AR}" -r tx.a tx_byte_pool_info_get.o tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o +"${AR}" -r tx.a tx_event_flags_get.o tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +"${AR}" -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o +"${AR}" -r tx.a tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o tx_queue_performance_system_info_get.o +"${AR}" -r tx.a tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o +"${AR}" -r tx.a tx_semaphore_initialize.o tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o +"${AR}" -r tx.a tx_thread_info_get.o tx_thread_initialize.o tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o +"${AR}" -r tx.a tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o tx_thread_terminate.o tx_thread_time_slice.o +"${AR}" -r tx.a tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o +"${AR}" -r tx.a tx_timer_expiration_process.o tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_buffer_full_notify.o tx_trace_enable.o +"${AR}" -r tx.a tx_trace_event_filter.o tx_trace_event_unfilter.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +"${AR}" -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o +"${AR}" -r tx.a txe_byte_pool_prioritize.o txe_byte_release.o txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o +"${AR}" -r tx.a txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +"${AR}" -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o +"${AR}" -r tx.a txe_semaphore_put_notify.o txe_thread_create.o txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o +"${AR}" -r tx.a txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_m85/gnu/example_build/build_threadx_sample.sh b/ports/cortex_m85/gnu/example_build/build_threadx_sample.sh new file mode 100755 index 00000000..795d9400 --- /dev/null +++ b/ports/cortex_m85/gnu/example_build/build_threadx_sample.sh @@ -0,0 +1,64 @@ +#!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +# +# AI Disclosure: This file was largely AI-generated by Copilot (Claude Sonnet 4.6). +# Portions of this file were generated with AI assistance. +# The AI-generated portions may be considered public domain (CC0-1.0) +# and not subject to the project's licence. The human contributor has +# reviewed and verified that the code is correct. +# +# SPDX-License-Identifier: MIT and CC0-1.0 +############################################################################## + +set -e +cd "$(dirname "$0")" + +# Toolchain selection. The default is the GNU toolchain, so an existing +# invocation of this script behaves exactly as before. Set TOOLCHAIN=atfe to +# build with Arm Toolchain for Embedded, which is LLVM based and is the +# successor to Arm Compiler 6: +# +# TOOLCHAIN=atfe ATFE_CLANG=/path/to/clang ./build_threadx_sample.sh +# +: "${TOOLCHAIN:=gnu}" +case "${TOOLCHAIN}" in + gnu) + CC="arm-none-eabi-gcc" + AR="arm-none-eabi-ar" + TARGET_FLAGS="" + ENTRY_FLAG="-ereset_handler" + SYSCALL_LIB="--specs=nosys.specs" + ;; + atfe) + CC="${ATFE_CLANG:-clang}" + # llvm-ar ships beside clang in the toolchain. + case "${CC}" in + */*) AR="$(dirname "${CC}")/llvm-ar" ;; + *) AR="llvm-ar" ;; + esac + TARGET_FLAGS="--target=arm-none-eabi" + ENTRY_FLAG="-Wl,--entry=reset_handler" + # picolibc leaves _exit to the application; the toolchain's own + # semihosting library supplies it, which suits an example that runs on + # a model. + SYSCALL_LIB="-lsemihost" + ;; + *) + echo "Unknown TOOLCHAIN '${TOOLCHAIN}'; expected gnu or atfe" >&2 + exit 1 + ;; +esac + +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb cortexm85_vectors.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb cortexm85_crt0.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb tx_initialize_low_level.S +"${CC}" ${TARGET_FLAGS} -c -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -I../../../../common/inc -I../inc sample_threadx.c +"${CC}" ${TARGET_FLAGS} -g -mcpu=cortex-m85 -mfloat-abi=hard -mthumb -T sample_threadx.ld ${ENTRY_FLAG} -nostartfiles -o sample_threadx.out -Wl,-Map=sample_threadx.map cortexm85_vectors.o cortexm85_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a ${SYSCALL_LIB} diff --git a/ports/cortex_m85/gnu/example_build/cortexm85_crt0.S b/ports/cortex_m85/gnu/example_build/cortexm85_crt0.S new file mode 100644 index 00000000..070871a3 --- /dev/null +++ b/ports/cortex_m85/gnu/example_build/cortexm85_crt0.S @@ -0,0 +1,118 @@ + .global _start + .extern main + + + .section .init, "ax" + .code 16 + .align 2 + .thumb_func + + +_start: + CPSID i + ldr r1, =__stack_end__ + mov sp, r1 + + /* Copy initialised sections into RAM if required. */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl crt0_memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl crt0_memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl crt0_memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl crt0_memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl crt0_memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl crt0_memory_copy + + + /* Zero bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + bl crt0_memory_set + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + sub r1, r1, r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + /* constructors in case of using C++ */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +crt0_ctor_loop: + cmp r0, r1 + beq crt0_ctor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b crt0_ctor_loop +crt0_ctor_end: + + /* Setup call frame for main() */ + mov r0, #0 + mov lr, r0 + mov r12, sp + +start: + /* Jump to main() */ + mov r0, #0 + mov r1, #0 + ldr r2, =main + blx r2 + /* when main returns, loop forever. */ +crt0_exit_loop: + b crt0_exit_loop + + + + /* Startup helper functions. */ + +crt0_memory_copy: + cmp r0, r1 + beq memory_copy_done + sub r2, r2, r1 + beq memory_copy_done +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + bne memory_copy_loop +memory_copy_done: + bx lr + +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits diff --git a/ports/cortex_m85/gnu/example_build/cortexm85_vectors.S b/ports/cortex_m85/gnu/example_build/cortexm85_vectors.S new file mode 100644 index 00000000..3ed01aad --- /dev/null +++ b/ports/cortex_m85/gnu/example_build/cortexm85_vectors.S @@ -0,0 +1,99 @@ +/************************************************************************** + * Copyright (c) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +/* Exception and interrupt vector table for the Cortex-M85 example. + * + * Armv8-M names its exception handlers the CMSIS way, so this table cannot be + * the Armv7-M one with the core name changed: the port and its low level + * initialisation export SVC_Handler, PendSV_Handler, SysTick_Handler and + * HardFault_Handler, where the Cortex-M3, M4 and M7 examples reference + * __tx_SVCallHandler, __tx_PendSVHandler, __tx_SysTickHandler and + * __tx_HardfaultHandler. Linking the Armv7-M table here fails to resolve every + * one of those. + * + * Slot 7 is SecureFault on Armv8-M, where Armv7-M leaves it reserved. + */ + + .global reset_handler + .global __tx_NMIHandler + .global __tx_BadHandler + .global SVC_Handler + .global PendSV_Handler + .global SysTick_Handler + .global HardFault_Handler + .global UsageFault_Handler + .global __tx_DBGHandler + + .syntax unified + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + +_vectors: + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler + .word HardFault_Handler + .word __tx_BadHandler // MemManage + .word __tx_BadHandler // BusFault + .word UsageFault_Handler + .word __tx_BadHandler // SecureFault, Armv8-M only + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // Used by the ThreadX scheduler + .word __tx_DBGHandler + .word 0 // Reserved + .word PendSV_Handler // Used by the ThreadX scheduler + .word SysTick_Handler // Used by the ThreadX timer + .word __tx_BadHandler // Populate with a user interrupt handler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + + .section .init, "ax" + .thumb_func +reset_handler: + // low level hardware config, such as PLL setup goes here + b _start diff --git a/ports/cortex_m85/gnu/example_build/sample_threadx.ld b/ports/cortex_m85/gnu/example_build/sample_threadx.ld new file mode 100644 index 00000000..107e0e41 --- /dev/null +++ b/ports/cortex_m85/gnu/example_build/sample_threadx.ld @@ -0,0 +1,165 @@ +MEMORY +{ + RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00800000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 +} + +__STACKSIZE__ = 1024; +__STACKSIZE_PROCESS__ = 0; +__HEAPSIZE__ = 128; + +SECTIONS +{ + .vectors : + { + KEEP(*(.vectors .vectors.*)) + } > FLASH + + .text : + { + __text_start__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + __ctors_load_start__ = .; + __ctors_start__ = ALIGN(4); + *(SORT(.ctors.*)) + *(.ctors) + __ctors_end__ = ALIGN(4); + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + __dtors_load_start__ = .; + __dtors_start__ = ALIGN(4); + *(SORT(.dtors.*)) + *(.dtors) + __dtors_end__ = ALIGN(4); + + KEEP(*(.eh_frame*)) + + __text_end__ = ALIGN(4); + } > FLASH + + __text_load_start__ = LOADADDR(.text); + + .rodata : + { + __rodata_start__ = .; + *(.rodata*) + __rodata_end__ = ALIGN(4); + } > FLASH + + __rodata_load_start__ = LOADADDR(.rodata); + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __data_load_start__ = ALIGN (4); + + /* Fast section: for time-critical code/data to be copied from FLASH to RAM at startup. + No .fast content in this sample; symbols defined so crt0 startup copy is a no-op. */ + .fast (NOLOAD) : + { + __fast_start__ = .; + *(.fast*) + __fast_end__ = .; + } > RAM + + __fast_load_start__ = __fast_start__; + + .data : AT (__data_load_start__) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + + } > RAM + + .heap (COPY): + { + __heap_start__ = ALIGN(4); + *(.heap) + . = ALIGN(. + __HEAPSIZE__, 4); + __heap_end__ = ALIGN(4); + } > RAM + + /* This port's tx.a carries tx_thread_secure_stack.c, which calls malloc and + free. That pulls newlib's allocator, whose _sbrk takes the heap base from + "end". The Cortex-M3, M4 and M7 examples never reference the allocator, so + their linker scripts do not define it and this section is the difference. */ + + PROVIDE(end = __heap_start__); + PROVIDE(_end = __heap_start__); + + /* picolibc, which Arm Toolchain for Embedded ships, takes the heap bounds + from __heap_start and __heap_end instead of from end. */ + + PROVIDE(__heap_start = __heap_start__); + PROVIDE(__heap_end = __heap_end__); + + .stack ALIGN(4) (NOLOAD) : + { + __stack_start__ = ALIGN(4); + *(.stack) + . = ALIGN(. + __STACKSIZE__, 4); + __stack_end__ = ALIGN(4); + } > RAM + + __RAM_segment_used_end__ = .; +} diff --git a/ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S index 22dc0780..eb6b5af7 100644 --- a/ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -87,25 +88,17 @@ _tx_initialize_low_level: ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer - /* Setup Vector Table Offset Register. */ - MOV r0, #0xE000E000 // Build address of NVIC registers - LDR r1, =_vectors // Pickup address of vector table - STR r1, [r0, #0xD08] // Set vector table address - /* Enable the cycle count register. */ LDR r0, =0xE0001000 // Build address of DWT register LDR r1, [r0] // Pickup the current value ORR r1, r1, #1 // Set the CYCCNTENA bit STR r1, [r0] // Enable the cycle count register - /* Set system stack pointer from vector value. */ - LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer - LDR r1, =_vectors // Pickup address of vector table - LDR r1, [r1] // Pickup reset stack pointer - STR r1, [r0] // Save system stack pointer - /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m85/gnu/inc/tx_port.h b/ports/cortex_m85/gnu/inc/tx_port.h index 0f67673b..353159b3 100644 --- a/ports/cortex_m85/gnu/inc/tx_port.h +++ b/ports/cortex_m85/gnu/inc/tx_port.h @@ -9,7 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ -// Some portions generated by Gemini (Gemini 2.0 Flash). +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -582,7 +582,7 @@ UINT interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); - __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); + __asm__ volatile ("dsb sy \n isb sy " : : : "memory"); if (_tx_ipsr_get() == 0) { interrupt_save = __get_interrupt_posture(); @@ -592,7 +592,7 @@ UINT interrupt_save; __enable_interrupts(); #endif __restore_interrupt(interrupt_save); - __asm__ volatile ("isb 0xF " : : : "memory"); + __asm__ volatile ("isb sy " : : : "memory"); } } @@ -618,7 +618,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/GNU Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/GNU Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/gnu/readme_threadx.txt b/ports/cortex_m85/gnu/readme_threadx.txt index d497b037..afebaf3e 100644 --- a/ports/cortex_m85/gnu/readme_threadx.txt +++ b/ports/cortex_m85/gnu/readme_threadx.txt @@ -200,7 +200,12 @@ information associated with this specific port of ThreadX: 03-02-2021 The following files were changed/added for version 6.1.5: tx_port.h Added ULONG64_DEFINED -09-30-2020 Initial ThreadX 6.1 version for Cortex-M85 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version of this Armv8-M port using GNU tools. + + The dates above belong to this shared port, which every Armv8-M + core is generated from. They are not the date a particular core + gained a ThreadX port: that is when its name was added to + scripts/copy_armv8_m.sh. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m85/gnu/src/tx_thread_schedule.S b/ports/cortex_m85/gnu/src/tx_thread_schedule.S index f46f5737..d9bcddee 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m85/gnu/src/tx_thread_schedule.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -125,7 +126,7 @@ __tx_ts_handler: BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -274,9 +275,19 @@ __tx_ts_wait: #endif #ifdef TX_ENABLE_WFI +#ifdef TX_PORT_USE_BASEPRI + CPSID i // Mask every interrupt with PRIMASK, which WFI ignores + MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it + MSR BASEPRI, r1 // is still able to wake the processor +#endif DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed +#ifdef TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask + MSR BASEPRI, r1 + CPSIE i // Clear PRIMASK; a pending interrupt is taken here +#endif #endif #ifdef TX_LOW_POWER diff --git a/ports/cortex_m85/gnu/src/tx_thread_system_return.S b/ports/cortex_m85/gnu/src/tx_thread_system_return.S index 35630094..94090d14 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m85/gnu/src/tx_thread_system_return.S @@ -9,7 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ -// Some portions generated by Gemini (Gemini 2.0 Flash). +// Portions of this file were generated with AI assistance. /**************************************************************************/ diff --git a/ports/cortex_m85/iar/inc/tx_port.h b/ports/cortex_m85/iar/inc/tx_port.h index 2d0024ab..15f845fd 100644 --- a/ports/cortex_m85/iar/inc/tx_port.h +++ b/ports/cortex_m85/iar/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -580,6 +582,7 @@ UINT interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb sy \n isb sy " : : : "memory"); if (_tx_ipsr_get() == 0) { interrupt_save = __get_interrupt_posture(); @@ -589,6 +592,7 @@ UINT interrupt_save; __enable_interrupts(); #endif __restore_interrupt(interrupt_save); + __asm__ volatile ("isb sy " : : : "memory"); } } @@ -614,7 +618,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/IAR Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/IAR Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; @@ -624,5 +628,3 @@ extern CHAR _tx_version_id[]; #endif #endif - -#endif diff --git a/ports/cortex_m85/iar/readme_threadx.txt b/ports/cortex_m85/iar/readme_threadx.txt index 6436cfa8..29a246cb 100644 --- a/ports/cortex_m85/iar/readme_threadx.txt +++ b/ports/cortex_m85/iar/readme_threadx.txt @@ -211,7 +211,12 @@ information associated with this specific port of ThreadX: 03-02-2021 The following files were changed/added for version 6.1.5: tx_port.h Added ULONG64_DEFINED -09-30-2020 Initial ThreadX 6.1 version for Cortex-M85 using IAR's ARM tools. +09-30-2020 Initial ThreadX 6.1 version of this Armv8-M port using IAR's ARM tools. + + The dates above belong to this shared port, which every Armv8-M + core is generated from. They are not the date a particular core + gained a ThreadX port: that is when its name was added to + scripts/copy_armv8_m.sh. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m85/iar/src/tx_iar.c b/ports/cortex_m85/iar/src/tx_iar.c index 238b485e..ab6c209c 100644 --- a/ports/cortex_m85/iar/src/tx_iar.c +++ b/ports/cortex_m85/iar/src/tx_iar.c @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ /**************************************************************************/ @@ -270,7 +271,7 @@ TX_MUTEX *mutex_ptr; mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; /* Check for wrap-around on the next free mutex. */ - if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK) { /* Yes, set the free index back to 0. */ @@ -287,7 +288,7 @@ TX_MUTEX *mutex_ptr; } /* Determine if a free mutex was found. */ - if (i >= _MAX_LOCK) + if (i >= _MAX_FLOCK) { /* Error! No more free mutexes! */ @@ -678,7 +679,7 @@ TX_MUTEX *mutex_ptr; mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; /* Check for wrap-around on the next free mutex. */ - if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK) { /* Yes, set the free index back to 0. */ @@ -695,7 +696,7 @@ TX_MUTEX *mutex_ptr; } /* Determine if a free mutex was found. */ - if (i >= _MAX_LOCK) + if (i >= _MAX_FLOCK) { /* Error! No more free mutexes! */ diff --git a/ports/cortex_m85/iar/src/tx_initialize_low_level.s b/ports/cortex_m85/iar/src/tx_initialize_low_level.s index 64260c52..60f5e18d 100644 --- a/ports/cortex_m85/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m85/iar/src/tx_initialize_low_level.s @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -24,11 +25,9 @@ #include "tx_user.h" #endif - EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_timer_interrupt EXTERN __main - EXTERN __vector_table EXTERN _tx_thread_current_ptr EXTERN _tx_thread_stack_error_handler @@ -89,25 +88,17 @@ _tx_initialize_low_level: LDR r1, =__tx_free_memory_start // Build first free address STR r1, [r0] // Setup first unused memory pointer - /* Setup Vector Table Offset Register. */ - MOV r0, #0xE000E000 // Build address of NVIC registers - LDR r1, =__vector_table // Pickup address of vector table - STR r1, [r0, #0xD08] // Set vector table address - /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit // STR r1, [r0] // Enable the cycle count register - /* Set system stack pointer from vector value. */ - LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer - LDR r1, =__vector_table // Pickup address of vector table - LDR r1, [r1] // Pickup reset stack pointer - STR r1, [r0] // Save system stack pointer - /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m85/iar/src/tx_thread_schedule.s b/ports/cortex_m85/iar/src/tx_thread_schedule.s index fa2d7ba0..c9f85bc1 100644 --- a/ports/cortex_m85/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m85/iar/src/tx_thread_schedule.s @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -129,7 +131,7 @@ __tx_ts_handler: BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -278,9 +280,19 @@ __tx_ts_wait: #endif #ifdef TX_ENABLE_WFI +#ifdef TX_PORT_USE_BASEPRI + CPSID i // Mask every interrupt with PRIMASK, which WFI ignores + MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it + MSR BASEPRI, r1 // is still able to wake the processor +#endif DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed +#ifdef TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask + MSR BASEPRI, r1 + CPSIE i // Clear PRIMASK; a pending interrupt is taken here +#endif #endif #ifdef TX_LOW_POWER diff --git a/ports/cortex_m85/iar/src/tx_thread_system_return.s b/ports/cortex_m85/iar/src/tx_thread_system_return.s index fcc87228..e3806f32 100644 --- a/ports/cortex_m85/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m85/iar/src/tx_thread_system_return.s @@ -9,7 +9,7 @@ ;* SPDX-License-Identifier: MIT ;************************************************************************** -; Some portions generated by Gemini (Gemini 2.0 Flash). +; Portions of this file were generated with AI assistance. ;************************************************************************** @@ -82,10 +82,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB SY // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB SY // Flush pipeline #endif _isr_context: BX lr // Return to caller |